Module Definition
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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
70 1 1
71 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Module : sysrst_ctrl_comboact
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT14,T6,T8
11CoveredT6,T8,T10

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT3,T6,T8
10CoveredT14,T2,T3
11CoveredT2,T3,T6

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT14,T2,T3
11CoveredT2,T3,T10

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT39,T36,T82
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT6,T8,T10
10CoveredT6,T8,T10

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT2,T3,T10
10CoveredT2,T3,T10

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT2,T3,T6

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT14,T2,T3

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

Branch Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T14,T2,T3
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 71 (timer_expired) ? -2-: 71 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T2,T3
0 1 Covered T4,T1,T5
0 0 Covered T14,T2,T3


LineNo. Expression -1-: 79 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
70 1 1
71 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT2,T6,T11
10CoveredT8,T10,T35
11CoveredT8,T10,T39

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT8,T39,T36
10CoveredT14,T2,T6
11CoveredT2,T6,T10

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT2,T6,T8
10CoveredT14,T3,T10
11CoveredT10,T34,T39

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT234,T238,T186
10CoveredT2,T6,T8
11CoveredT2,T6,T8

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT8,T10,T39
10CoveredT8,T10,T39

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT10,T34,T39
10CoveredT10,T34,T39

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT2,T6,T10

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT14,T2,T3

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T14,T2,T3
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 71 (timer_expired) ? -2-: 71 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T2,T3
0 1 Covered T4,T1,T5
0 0 Covered T14,T2,T3


LineNo. Expression -1-: 79 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
70 1 1
71 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT3,T34,T39
10CoveredT6,T10,T35
11CoveredT6,T10,T93

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT6,T10,T34
10CoveredT3,T35,T39
11CoveredT3,T39,T57

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT6,T180,T234
10CoveredT14,T3,T10
11CoveredT3,T10,T34

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT39,T82,T180
10CoveredT2,T3,T6
11CoveredT3,T6,T10

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT6,T10,T93
10CoveredT6,T10,T93

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT3,T10,T34
10CoveredT3,T10,T34

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT3,T39,T57

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT14,T2,T3

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T14,T2,T3
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 71 (timer_expired) ? -2-: 71 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T2,T3
0 1 Covered T4,T1,T5
0 0 Covered T14,T2,T3


LineNo. Expression -1-: 79 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
70 1 1
71 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT3,T34,T39
10CoveredT14,T8,T35
11CoveredT35,T36,T82

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT3,T39,T36
10CoveredT14,T6,T8
11CoveredT34,T35,T37

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT3,T34,T35
10CoveredT14,T2,T6
11CoveredT39,T36,T82

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT36,T82,T107
10CoveredT3,T6,T34
11CoveredT3,T34,T35

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT35,T36,T82
10CoveredT35,T36,T82

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT39,T36,T82
10CoveredT39,T36,T82

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT34,T35,T37

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT14,T2,T3

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T14,T2,T3
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 71 (timer_expired) ? -2-: 71 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T2,T3
0 1 Covered T4,T1,T5
0 0 Covered T14,T2,T3


LineNo. Expression -1-: 79 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
41 1 1
48 1 1
49 1 1
52 1 1
53 1 1
62 1 1
63 1 1
70 1 1
71 1 1
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT35,T39,T37
11CoveredT35,T39,T37

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT2,T34,T35
10CoveredT3,T6,T8
11CoveredT3,T8,T39

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT3,T228,T234
10CoveredT2,T6,T8
11CoveredT2,T8,T34

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT2,T3,T34
10CoveredT8,T10,T36
11CoveredT8,T36,T37

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT35,T39,T37
10CoveredT35,T39,T37

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT2,T8,T34
10CoveredT2,T8,T34

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT3,T8,T39

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT14,T2,T3

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT14,T2,T3

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT14,T2,T3
1CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 ((combo_ec_rst_pulse || ec_rst_l_det_pulse)) ? -2-: 63 (timer_expired) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T1,T5
0 1 Covered T14,T2,T3
0 0 Covered T4,T1,T5


LineNo. Expression -1-: 71 (timer_expired) ? -2-: 71 ((ec_rst_l_q == 1'b0)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T2,T3
0 1 Covered T4,T1,T5
0 0 Covered T14,T2,T3


LineNo. Expression -1-: 79 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%