Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1639

1

T14

2

T3

22

T25

6

auto[1]

753

1

T1

15

T14

2

T3

16

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T1

12

T14

2

T3

25

auto[1]

610

1

T1

3

T14

2

T3

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T1

13

T14

4

T3

13

auto[1]

598

1

T1

2

T3

25

T10

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1857

1

T1

2

T14

3

T3

33

auto[1]

535

1

T1

13

T14

1

T3

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255

1

T1

15

T14

4

T3

38

auto[1]

137

1

T10

3

T11

3

T70

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2189

1

T1

15

T14

4

T3

38

auto[1]

203

1

T10

3

T11

13

T70

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2157

1

T1

15

T14

2

T3

38

auto[1]

235

1

T14

2

T25

2

T10

7

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2117

1

T1

15

T14

3

T3

38

auto[1]

275

1

T14

1

T10

1

T11

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2250

1

T1

15

T14

4

T3

38

auto[1]

142

1

T25

2

T10

1

T11

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1702

1

T1

11

T14

3

T3

25

auto[1]

690

1

T1

4

T14

1

T3

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	974	1			T1	15		T3	38		T45	6
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	26	1			T31	4		T263	3		T227	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	44	1			T48	1		T247	6		T214	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	10	1			T345	4		T343	6		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	60	1			T262	3		T189	1		T346	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	8	1			T347	3		T342	5		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	38	1			T70	7		T186	7		T346	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T348	5		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	50	1			T14	1		T10	6		T68	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	20	1			T11	2		T349	3		T214	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T350	2		T343	3		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T343	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	77	1			T14	1		T11	1		T351	57
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	18	1			T263	2		T186	1		T352	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T10	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	66	1			T11	8		T248	6		T31	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	21	1			T10	3		T186	11		T349	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T11	5		T344	4		T350	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	45	1			T262	3		T263	3		T351	13
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T346	1		T258	2		T353	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	20	1			T349	3		T352	2		T354	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T70	2		T355	1		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T243	2		T356	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T214	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

121

1

T10

1

T55

6

T95

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

88

1

T70

2

T186

1

T82

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

111

1

T72

3

T77

5

T263

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

66

1

T10

6

T11

5

T68

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

54

1

T1

8

T72

4

T356

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T30

6

T262

6

T214

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T1

2

T248

3

T76

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

95

1

T3

14

T186

11

T357

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

97

1

T3

11

T11

8

T262

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T10

3

T33

3

T346

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T1

2

T155

1

T103

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T55

2

T248

3

T251

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T29

3

T30

3

T82

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T45

2

T330

8

T264

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

22

1

T31

2

T330

1

T197

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T11

2

T94

7

T357

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

83

1

T11

1

T70

7

T82

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T3

8

T252

4

T31

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

49

1

T14

1

T262

3

T358

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T247

6

T243

9

T214

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T1

3

T14

1

T47

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T45

4

T197

2

T349

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T3

5

T100

1

T265

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T48

1

T72

6

T359

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T33

3

T94

1

T359

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T30

3

T197

2

T331

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T33

1

T358

1

T360

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T252

2

T31

2

T338

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T47

1

T77

2

T100

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T82

2

T361

1

T227

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T357

1

T362

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded