Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T2

32

T12

13

T24

8

auto[1]

1093

1

T2

45

T12

7

T24

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T2

20

T12

4

T24

4

from_0to1

545

1

T2

19

T12

5

T24

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T2

38

T12

11

T24

9

auto[1]

1145

1

T2

39

T12

9

T24

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T2

35

T12

9

T24

11

auto[1]

1112

1

T2

42

T12

11

T24

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T2

3

T54

1

T195

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T2

1

T54

1

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T2

3

T12

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T2

3

T379

1

T306

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T24

2

T54

2

T379

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T2

5

T12

2

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T12

2

T54

1

T35

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T2

1

T195

1

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T2

2

T46

1

T128

2

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

3

T12

2

T46

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T2

4

T12

1

T24

3

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T2

1

T24

1

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T2

3

T46

1

T32

3

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T2

1

T54

1

T195

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T2

4

T12

1

T24

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T2

5

T24

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T2

39

T12

8

T24

7

auto[1]

1126

1

T2

38

T12

12

T24

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T2

23

T12

6

T24

5

from_0to1

536

1

T2

24

T12

5

T24

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T2

39

T12

10

T24

8

auto[1]

1093

1

T2

38

T12

10

T24

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T2

54

T12

9

T24

12

auto[1]

1098

1

T2

23

T12

11

T24

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T2

7

T24

2

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T2

1

T195

1

T32

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T2

1

T12

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T2

1

T306

1

T32

5

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T2

5

T54

1

T195

4

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T2

1

T12

1

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T2

5

T24

1

T46

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T2

3

T12

2

T54

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T2

4

T12

3

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T2

1

T24

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T2

5

T24

1

T195

1

auto[1]

from_1to0

auto[1]

auto[1]

88

1

T2

3

T12

2

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T2

3

T12

1

T54

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T2

3

T195

1

T35

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T24

1

T46

1

T306

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T2

4

T12

1

T24

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T2

41

T12

5

T24

13

auto[1]

1086

1

T2

36

T12

15

T24

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T2

23

T12

5

T24

4

from_0to1

549

1

T2

23

T12

6

T24

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T2

27

T12

8

T24

8

auto[1]

1073

1

T2

50

T12

12

T24

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T2

42

T12

10

T24

8

auto[1]

1095

1

T2

35

T12

10

T24

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T2

4

T12

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T2

2

T24

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T2

1

T306

1

T32

4

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T12

1

T54

1

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T2

1

T54

1

T195

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T2

2

T24

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T2

6

T195

1

T46

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T2

4

T12

1

T24

3

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T2

5

T12

1

T46

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T2

1

T12

1

T54

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T2

4

T12

1

T24

3

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T2

6

T54

1

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T2

2

T12

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

85

1

T2

2

T195

2

T379

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T2

2

T12

1

T24

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T2

4

T12

3

T46

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T2

30

T12

11

T24

6

auto[1]

1139

1

T2

47

T12

9

T24

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T2

18

T12

4

T24

7

from_0to1

529

1

T2

17

T12

4

T24

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T2

38

T12

11

T24

10

auto[1]

1088

1

T2

39

T12

9

T24

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T2

44

T12

9

T24

7

auto[1]

1105

1

T2

33

T12

11

T24

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T2

6

T54

1

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T2

2

T24

2

T54

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T2

1

T195

1

T46

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T2

1

T12

2

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T2

1

T12

2

T46

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T2

2

T379

2

T306

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T2

1

T54

1

T195

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T24

2

T54

1

T306

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T2

2

T12

2

T24

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T379

1

T32

2

T128

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T2

3

T24

2

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T2

3

T24

2

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T2

4

T24

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

81

1

T2

4

T12

1

T24

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T2

3

T54

1

T195

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T2

2

T12

1

T24

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T2

35

T12

12

T24

8

auto[1]

1111

1

T2

42

T12

8

T24

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T2

20

T12

5

T24

4

from_0to1

524

1

T2

20

T12

4

T24

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T2

37

T12

12

T24

10

auto[1]

1096

1

T2

40

T12

8

T24

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T2

35

T12

11

T24

11

auto[1]

1106

1

T2

42

T12

9

T24

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T2

2

T12

2

T24

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T2

5

T12

1

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T2

3

T54

1

T306

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T2

1

T195

1

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T54

2

T46

1

T32

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T2

3

T12

1

T195

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T2

5

T12

2

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T24

1

T306

1

T32

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T12

1

T379

2

T32

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T2

4

T24

1

T195

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

2

T12

1

T24

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T2

3

T24

1

T379

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T2

1

T24

2

T195

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T2

2

T12

1

T46

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T2

6

T195

1

T32

3

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T2

3

T24

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T2

41

T12

11

T24

11

auto[1]

1110

1

T2

36

T12

9

T24

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T2

18

T12

6

T24

6

from_0to1

528

1

T2

18

T12

6

T24

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T2

39

T12

7

T24

14

auto[1]

1108

1

T2

38

T12

13

T24

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T2

46

T12

14

T24

9

auto[1]

1102

1

T2

31

T12

6

T24

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T2

6

T12

2

T24

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T2

2

T12

2

T24

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T2

3

T12

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T2

1

T379

3

T306

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T2

4

T12

1

T46

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T2

2

T24

3

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T2

3

T12

2

T24

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T2

1

T54

2

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T2

1

T24

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T24

1

T54

1

T32

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T2

2

T12

1

T54

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T2

3

T24

1

T195

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T195

1

T46

1

T379

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T2

4

T24

2

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T2

4

T12

3

T195

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T24

1

T54

1

T379

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T2

42

T12

6

T24

6

auto[1]

1125

1

T2

35

T12

14

T24

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T2

22

T12

2

T24

4

from_0to1

560

1

T2

22

T12

3

T24

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T2

46

T12

12

T24

10

auto[1]

1082

1

T2

31

T12

8

T24

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T2

38

T12

11

T24

13

auto[1]

1117

1

T2

39

T12

9

T24

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T2

5

T24

1

T195

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T2

3

T12

1

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T2

1

T54

1

T195

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T2

2

T24

2

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T2

4

T12

1

T54

3

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T2

3

T195

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T2

1

T379

1

T32

2

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T2

4

T54

2

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T2

2

T24

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T2

3

T12

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T2

3

T54

2

T306

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T2

3

T195

2

T379

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T2

2

T12

2

T24

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T2

3

T195

2

T46

1

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T2

3

T24

2

T195

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T2

2

T24

1

T195

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T2

38

T12

13

T24

7

auto[1]

1132

1

T2

39

T12

7

T24

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T2

15

T12

3

T24

2

from_0to1

527

1

T2

15

T12

4

T24

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T2

40

T12

9

T24

10

auto[1]

1100

1

T2

37

T12

11

T24

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T2

44

T12

13

T24

11

auto[1]

1105

1

T2

33

T12

7

T24

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T2

1

T195

2

T306

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T2

1

T12

1

T24

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T2

2

T12

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T54

2

T46

1

T379

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T2

4

T379

1

T32

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T2

1

T12

1

T195

3

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T2

1

T24

1

T54

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T2

2

T46

1

T32

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T2

4

T54

1

T195

3

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T2

1

T54

2

T379

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T2

1

T12

1

T306

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T2

5

T24

1

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T2

1

T12

1

T54

3

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T2

3

T54

1

T32

3

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T2

2

T12

1

T46

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T2

1

T12

1

T24

1