Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118143

1

T1

284

T5

4

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143108	1			T1	407		T5	3		T6	2
values[0x0]	64753	1			T1	68		T2	252		T13	26
values[0x1]	66166	1			T1	65		T5	3		T2	241

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148017

1

T1

328

T5

4

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	839	1			T2	1		T16	1		T3	2
valid_sources[0x01]	1158	1			T2	3		T3	2		T10	6
valid_sources[0x02]	884	1			T2	1		T4	4		T40	1
valid_sources[0x03]	1025	1			T2	6		T15	11		T3	1
valid_sources[0x04]	844	1			T3	5		T10	3		T11	1
valid_sources[0x05]	921	1			T2	3		T3	1		T10	3
valid_sources[0x06]	894	1			T2	3		T3	3		T25	9
valid_sources[0x07]	751	1			T2	4		T16	1		T10	3
valid_sources[0x08]	869	1			T2	4		T3	7		T25	4
valid_sources[0x09]	1837	1			T2	5		T15	5		T40	2
valid_sources[0x0a]	1049	1			T2	4		T3	4		T10	6
valid_sources[0x0b]	977	1			T2	5		T3	2		T4	5
valid_sources[0x0c]	1074	1			T2	5		T3	2		T40	1
valid_sources[0x0d]	1103	1			T2	4		T16	2		T3	1
valid_sources[0x0e]	1045	1			T2	1		T3	10		T10	5
valid_sources[0x0f]	1427	1			T5	1		T2	8		T3	1
valid_sources[0x10]	894	1			T2	5		T3	2		T25	3
valid_sources[0x11]	977	1			T2	6		T16	3		T3	5
valid_sources[0x12]	870	1			T2	3		T3	2		T10	1
valid_sources[0x13]	886	1			T2	3		T3	3		T10	4
valid_sources[0x14]	1079	1			T2	5		T16	3		T3	2
valid_sources[0x15]	918	1			T2	5		T3	5		T10	4
valid_sources[0x16]	920	1			T2	6		T3	3		T10	8
valid_sources[0x17]	835	1			T2	5		T3	1		T10	2
valid_sources[0x18]	1049	1			T2	2		T16	1		T40	1
valid_sources[0x19]	1352	1			T2	9		T3	2		T10	4
valid_sources[0x1a]	1291	1			T2	5		T25	5		T10	10
valid_sources[0x1b]	862	1			T2	3		T3	3		T10	4
valid_sources[0x1c]	1113	1			T5	1		T2	2		T3	6
valid_sources[0x1d]	812	1			T2	4		T3	6		T10	7
valid_sources[0x1e]	850	1			T2	2		T3	5		T4	3
valid_sources[0x1f]	1096	1			T2	3		T3	5		T25	36
valid_sources[0x20]	1137	1			T2	3		T15	1		T3	4
valid_sources[0x21]	900	1			T2	4		T3	3		T4	4
valid_sources[0x22]	991	1			T2	5		T3	2		T10	1
valid_sources[0x23]	764	1			T2	4		T3	1		T4	4
valid_sources[0x24]	929	1			T2	4		T3	1		T10	3
valid_sources[0x25]	975	1			T2	4		T15	1		T16	2
valid_sources[0x26]	958	1			T2	5		T3	1		T25	7
valid_sources[0x27]	852	1			T2	6		T16	1		T3	9
valid_sources[0x28]	843	1			T2	4		T3	2		T10	10
valid_sources[0x29]	831	1			T2	4		T10	2		T11	2
valid_sources[0x2a]	1011	1			T2	1		T15	1		T3	8
valid_sources[0x2b]	924	1			T2	3		T3	2		T25	4
valid_sources[0x2c]	961	1			T2	4		T16	1		T3	3
valid_sources[0x2d]	859	1			T2	5		T13	1		T16	1
valid_sources[0x2e]	1704	1			T2	4		T3	6		T25	4
valid_sources[0x2f]	1002	1			T2	8		T10	4		T11	1
valid_sources[0x30]	1247	1			T2	6		T16	1		T3	4
valid_sources[0x31]	891	1			T6	1		T2	2		T10	9
valid_sources[0x32]	872	1			T2	3		T3	1		T10	6
valid_sources[0x33]	922	1			T2	6		T40	1		T10	4
valid_sources[0x34]	1111	1			T2	1		T3	2		T10	8
valid_sources[0x35]	762	1			T2	1		T16	2		T3	3
valid_sources[0x36]	1430	1			T2	9		T15	1		T3	2
valid_sources[0x37]	948	1			T2	8		T16	1		T3	4
valid_sources[0x38]	918	1			T2	3		T3	4		T25	9
valid_sources[0x39]	972	1			T2	1		T3	10		T10	5
valid_sources[0x3a]	1364	1			T2	3		T15	2		T3	5
valid_sources[0x3b]	787	1			T2	2		T13	11		T16	2
valid_sources[0x3c]	2048	1			T2	3		T25	4		T10	4
valid_sources[0x3d]	899	1			T2	8		T3	2		T10	5
valid_sources[0x3e]	1405	1			T2	5		T3	2		T25	5
valid_sources[0x3f]	942	1			T6	1		T2	6		T3	3
valid_sources[0x40]	1039	1			T2	6		T3	8		T10	7
valid_sources[0x41]	1063	1			T2	4		T3	6		T52	3
valid_sources[0x42]	1309	1			T2	2		T3	1		T9	17
valid_sources[0x43]	834	1			T2	5		T13	6		T10	5
valid_sources[0x44]	1104	1			T2	4		T3	4		T10	3
valid_sources[0x45]	875	1			T2	7		T3	6		T10	9
valid_sources[0x46]	1049	1			T5	1		T2	4		T3	3
valid_sources[0x47]	805	1			T2	6		T15	1		T3	5
valid_sources[0x48]	1874	1			T2	2		T14	876		T3	7
valid_sources[0x49]	1834	1			T2	6		T13	1		T16	2
valid_sources[0x4a]	949	1			T2	6		T3	1		T25	13
valid_sources[0x4b]	822	1			T2	4		T3	1		T25	5
valid_sources[0x4c]	1013	1			T2	6		T3	3		T10	2
valid_sources[0x4d]	878	1			T2	8		T3	5		T10	4
valid_sources[0x4e]	984	1			T2	3		T3	1		T10	8
valid_sources[0x4f]	849	1			T2	3		T3	3		T10	8
valid_sources[0x50]	767	1			T2	4		T16	1		T3	4
valid_sources[0x51]	735	1			T2	3		T3	4		T10	3
valid_sources[0x52]	1827	1			T2	7		T3	3		T8	3
valid_sources[0x53]	879	1			T2	5		T16	3		T3	4
valid_sources[0x54]	1100	1			T2	1		T3	2		T40	2
valid_sources[0x55]	746	1			T2	4		T13	1		T3	7
valid_sources[0x56]	873	1			T2	3		T15	1		T3	2
valid_sources[0x57]	921	1			T2	6		T3	1		T10	7
valid_sources[0x58]	901	1			T2	6		T3	1		T25	7
valid_sources[0x59]	866	1			T2	8		T3	4		T25	13
valid_sources[0x5a]	849	1			T2	1		T3	5		T10	3
valid_sources[0x5b]	819	1			T2	6		T3	3		T10	4
valid_sources[0x5c]	1325	1			T2	1		T10	4		T11	2
valid_sources[0x5d]	922	1			T2	9		T3	6		T10	4
valid_sources[0x5e]	883	1			T2	3		T3	1		T40	2
valid_sources[0x5f]	933	1			T2	4		T13	1		T16	1
valid_sources[0x60]	950	1			T5	1		T2	2		T3	1
valid_sources[0x61]	1337	1			T2	1		T3	2		T10	8
valid_sources[0x62]	1438	1			T2	13		T3	12		T25	14
valid_sources[0x63]	1233	1			T2	4		T3	3		T10	3
valid_sources[0x64]	1036	1			T2	8		T3	1		T40	1
valid_sources[0x65]	834	1			T2	5		T10	12		T11	7
valid_sources[0x66]	798	1			T2	4		T16	2		T3	3
valid_sources[0x67]	1029	1			T2	6		T3	1		T10	6
valid_sources[0x68]	2047	1			T2	5		T16	1		T3	3
valid_sources[0x69]	819	1			T2	6		T25	6		T10	5
valid_sources[0x6a]	1068	1			T2	2		T3	8		T10	5
valid_sources[0x6b]	1835	1			T2	8		T25	1		T10	5
valid_sources[0x6c]	1020	1			T2	5		T3	5		T25	1
valid_sources[0x6d]	1383	1			T2	2		T3	4		T4	1
valid_sources[0x6e]	791	1			T16	1		T3	1		T10	6
valid_sources[0x6f]	888	1			T3	7		T40	1		T10	1
valid_sources[0x70]	1022	1			T2	5		T3	4		T25	16
valid_sources[0x71]	1005	1			T2	1		T3	3		T25	6
valid_sources[0x72]	863	1			T2	4		T3	17		T11	11
valid_sources[0x73]	1098	1			T2	5		T3	4		T25	6
valid_sources[0x74]	852	1			T2	10		T3	2		T10	1
valid_sources[0x75]	957	1			T2	2		T13	5		T3	7
valid_sources[0x76]	872	1			T2	1		T3	2		T25	1
valid_sources[0x77]	948	1			T2	5		T16	1		T3	5
valid_sources[0x78]	839	1			T2	3		T3	2		T40	1
valid_sources[0x79]	1026	1			T2	6		T3	7		T10	5
valid_sources[0x7a]	1089	1			T2	9		T40	1		T10	5
valid_sources[0x7b]	855	1			T2	1		T13	3		T3	5
valid_sources[0x7c]	825	1			T2	4		T3	1		T25	9
valid_sources[0x7d]	887	1			T40	1		T25	3		T10	3
valid_sources[0x7e]	860	1			T2	9		T3	4		T4	3
valid_sources[0x7f]	1058	1			T2	5		T3	2		T40	1
valid_sources[0x80]	1025	1			T2	5		T3	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64629

1

T1

219

T5

3

T6

1

values[0x0]

all_enables

biggest_size

31270

1

T1

37

T2

113

T13

9

values[0x1]

all_enables

biggest_size

22244

1

T1

28

T5

1

T2

66