Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T16,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T16,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T16,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T4
1	0	Covered	T1,T6,T2
1	1	Covered	T16,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T3,T4
0	1	Covered	T105,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T3,T4
0	1	Covered	T16,T3,T4
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T3,T4
1	-	Covered	T16,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T3,T4
DetectSt	168	Covered	T16,T3,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T16,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T3,T4
DebounceSt->IdleSt	163	Covered	T75,T128,T129
DetectSt->IdleSt	186	Covered	T105,T106
DetectSt->StableSt	191	Covered	T16,T3,T4
IdleSt->DebounceSt	148	Covered	T16,T3,T4
StableSt->IdleSt	206	Covered	T16,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T3,T4
0	1	Covered	T16,T3,T4
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T3,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T129,T130,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T16,T3,T4
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T16,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	289	0	0
CntIncr_A	7510225	254127	0	0
CntNoWrap_A	7510225	6823897	0	0
DetectStDropOut_A	7510225	2	0	0
DetectedOut_A	7510225	870	0	0
DetectedPulseOut_A	7510225	134	0	0
DisabledIdleSt_A	7510225	6563384	0	0
DisabledNoDetection_A	7510225	6565792	0	0
EnterDebounceSt_A	7510225	158	0	0
EnterDetectSt_A	7510225	136	0	0
EnterStableSt_A	7510225	134	0	0
PulseIsPulse_A	7510225	134	0	0
StayInStableSt	7510225	736	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	7160	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	134	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	289	0	0
T3	42261	2	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	2	0	0
T40	2013	0	0	0
T41	36849	2	0	0
T42	0	6	0	0
T43	0	4	0	0
T44	0	4	0	0
T46	0	6	0	0
T50	0	4	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	254127	0	0
T3	42261	36	0	0
T4	2227	100	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	27	0	0
T40	2013	0	0	0
T41	36849	22	0	0
T42	0	227	0	0
T43	0	37969	0	0
T44	0	93	0	0
T46	0	152	0	0
T50	0	129	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823897	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39749	0	0
T4	2227	622	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	420	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2	0	0
T105	15310	1	0	0
T106	0	1	0	0
T113	502	0	0	0
T114	16669	0	0	0
T115	499	0	0	0
T116	3325	0	0	0
T117	494	0	0	0
T118	5126	0	0	0
T119	19629	0	0	0
T120	417	0	0	0
T121	6912	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	870	0	0
T3	42261	11	0	0
T4	2227	9	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	2	0	0
T40	2013	0	0	0
T41	36849	7	0	0
T42	0	25	0	0
T43	0	13	0	0
T44	0	10	0	0
T46	0	11	0	0
T50	0	12	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	134	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6563384	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39674	0	0
T4	2227	476	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	363	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6565792	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39695	0	0
T4	2227	479	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	365	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	158	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	136	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	134	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	134	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	736	0	0
T3	42261	10	0	0
T4	2227	8	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	6	0	0
T42	0	22	0	0
T43	0	11	0	0
T44	0	8	0	0
T46	0	8	0	0
T50	0	10	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	7160	0	0
T1	19868	13	0	0
T2	8913	37	0	0
T3	42261	33	0	0
T4	2227	5	0	0
T5	682	0	0	0
T6	426	2	0	0
T13	524	3	0	0
T14	10506	28	0	0
T15	490	9	0	0
T16	2025	10	0	0
T40	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	134	0	0
T3	42261	1	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T16	2025	1	0	0
T40	2013	0	0	0
T41	36849	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	3	0	0
T50	0	2	0	0
T51	402	0	0	0
T52	131225	0	0	0
T90	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T22,T23,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T1,T6,T2
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T33
0	1	Covered	T53,T46,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T33
0	1	Unreachable
1	0	Covered	T22,T23,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T22,T23,T53
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T22,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T53
DebounceSt->IdleSt	163	Covered	T8,T53,T46
DetectSt->IdleSt	186	Covered	T53,T46,T73
DetectSt->StableSt	191	Covered	T22,T23,T33
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T53
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T53,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T53,T46,T73
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T33
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	220	0	0
CntIncr_A	7510225	65654	0	0
CntNoWrap_A	7510225	6823966	0	0
DetectStDropOut_A	7510225	21	0	0
DetectedOut_A	7510225	9866	0	0
DetectedPulseOut_A	7510225	53	0	0
DisabledIdleSt_A	7510225	6139628	0	0
DisabledNoDetection_A	7510225	6142086	0	0
EnterDebounceSt_A	7510225	147	0	0
EnterDetectSt_A	7510225	74	0	0
EnterStableSt_A	7510225	53	0	0
PulseIsPulse_A	7510225	53	0	0
StayInStableSt	7510225	9813	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	7160	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_sticky_sva.StableStDropOut_A	7510225	386349	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	220	0	0
T8	1394	5	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	7259	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	3	0	0
T52	131225	0	0	0
T53	0	10	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	3	0	0
T74	0	5	0	0
T75	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	65654	0	0
T8	1394	475	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	68	0	0
T23	0	28	0	0
T25	7259	0	0	0
T33	0	89	0	0
T35	0	93	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	126	0	0
T52	131225	0	0	0
T53	0	203	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	68	0	0
T74	0	385	0	0
T75	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823966	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	21	0	0
T30	0	1	0	0
T37	607	0	0	0
T46	3687	1	0	0
T47	10973	0	0	0
T48	10817	0	0	0
T53	1336	3	0	0
T62	520	0	0	0
T73	0	1	0	0
T84	0	1	0	0
T94	0	4	0	0
T123	0	2	0	0
T131	0	3	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	430	0	0	0
T135	739	0	0	0
T136	422	0	0	0
T137	722	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9866	0	0
T22	860	267	0	0
T23	2232	128	0	0
T30	0	150	0	0
T33	0	555	0	0
T34	1103	0	0	0
T35	0	607	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	208	0	0
T84	0	1	0	0
T94	0	1	0	0
T123	0	95	0	0
T124	0	507	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	53	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	1	0	0
T84	0	1	0	0
T94	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6139628	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6142086	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	147	0	0
T8	1394	5	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	2	0	0
T52	131225	0	0	0
T53	0	7	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	2	0	0
T74	0	5	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	74	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	2	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T46	0	1	0	0
T53	0	3	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	1	0	0
T84	0	2	0	0
T123	0	3	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	53	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	1	0	0
T84	0	1	0	0
T94	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	53	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	1	0	0
T84	0	1	0	0
T94	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9813	0	0
T22	860	266	0	0
T23	2232	127	0	0
T30	0	149	0	0
T33	0	554	0	0
T34	1103	0	0	0
T35	0	606	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	207	0	0
T82	0	24	0	0
T86	0	430	0	0
T123	0	94	0	0
T124	0	506	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	7160	0	0
T1	19868	13	0	0
T2	8913	37	0	0
T3	42261	33	0	0
T4	2227	5	0	0
T5	682	0	0	0
T6	426	2	0	0
T13	524	3	0	0
T14	10506	28	0	0
T15	490	9	0	0
T16	2025	10	0	0
T40	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	386349	0	0
T22	860	76	0	0
T23	2232	222	0	0
T30	0	68	0	0
T33	0	82	0	0
T34	1103	0	0	0
T35	0	64	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T81	0	105	0	0
T84	0	43	0	0
T94	0	101	0	0
T123	0	96	0	0
T124	0	275	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T6,T2,T13
1	1	Covered	T6,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T6,T2,T13
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T53
0	1	Covered	T23,T89,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T53
0	1	Unreachable
1	0	Covered	T8,T22,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T8,T22,T23
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T22,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T22,T23
DebounceSt->IdleSt	163	Covered	T23,T74,T75
DetectSt->IdleSt	186	Covered	T23,T89,T86
DetectSt->StableSt	191	Covered	T8,T22,T53
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T8,T22,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T22,T23
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T6,T2,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T74,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T89,T86
DetectSt	-	-	-	-	0	1	-	Covered	T8,T22,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T22,T53
StableSt	-	-	-	-	-	-	0	Covered	T8,T22,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	231	0	0
CntIncr_A	7510225	278737	0	0
CntNoWrap_A	7510225	6823955	0	0
DetectStDropOut_A	7510225	18	0	0
DetectedOut_A	7510225	8828	0	0
DetectedPulseOut_A	7510225	50	0	0
DisabledIdleSt_A	7510225	6139628	0	0
DisabledNoDetection_A	7510225	6142086	0	0
EnterDebounceSt_A	7510225	164	0	0
EnterDetectSt_A	7510225	68	0	0
EnterStableSt_A	7510225	50	0	0
PulseIsPulse_A	7510225	50	0	0
StayInStableSt	7510225	8778	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_sticky_sva.StableStDropOut_A	7510225	77009	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	231	0	0
T8	1394	2	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	2	0	0
T23	0	7	0	0
T25	7259	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	2	0	0
T52	131225	0	0	0
T53	0	4	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	2	0	0
T74	0	5	0	0
T75	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	278737	0	0
T8	1394	77	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	75	0	0
T23	0	176	0	0
T25	7259	0	0	0
T33	0	36	0	0
T35	0	84	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	27	0	0
T52	131225	0	0	0
T53	0	78	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	11	0	0
T74	0	65	0	0
T75	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823955	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	18	0	0
T23	2232	3	0	0
T34	1103	0	0	0
T45	19308	0	0	0
T54	2254	0	0	0
T61	491	0	0	0
T65	524	0	0	0
T67	807	0	0	0
T86	0	4	0	0
T89	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0
T138	0	1	0	0
T139	0	3	0	0
T140	0	4	0	0
T141	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	8828	0	0
T8	1394	660	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	167	0	0
T25	7259	0	0	0
T30	0	173	0	0
T33	0	207	0	0
T35	0	388	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	70	0	0
T52	131225	0	0	0
T53	0	465	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	30	0	0
T81	0	164	0	0
T84	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	50	0	0
T8	1394	1	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T25	7259	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	2	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6139628	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6142086	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	164	0	0
T8	1394	1	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T23	0	4	0	0
T25	7259	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	2	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T74	0	5	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	68	0	0
T8	1394	1	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T25	7259	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	2	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T84	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	50	0	0
T8	1394	1	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T25	7259	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	2	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	50	0	0
T8	1394	1	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T25	7259	0	0	0
T30	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	2	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	8778	0	0
T8	1394	659	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	166	0	0
T25	7259	0	0	0
T30	0	172	0	0
T33	0	206	0	0
T35	0	387	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	69	0	0
T52	131225	0	0	0
T53	0	463	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	29	0	0
T81	0	163	0	0
T84	0	90	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	77009	0	0
T8	1394	205	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	181	0	0
T25	7259	0	0	0
T30	0	151	0	0
T33	0	477	0	0
T35	0	281	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	59	0	0
T52	131225	0	0	0
T53	0	304	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	114	0	0
T81	0	159	0	0
T84	0	124	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T22,T23,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T1,T6,T2
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T46
0	1	Covered	T84,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T46
0	1	Unreachable
1	0	Covered	T22,T23,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T22,T23,T46
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T22,T23,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T46
DebounceSt->IdleSt	163	Covered	T8,T53,T75
DetectSt->IdleSt	186	Covered	T84,T85,T86
DetectSt->StableSt	191	Covered	T22,T23,T46
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T22,T23,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T46
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T53,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T84,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T46
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	200	0	0
CntIncr_A	7510225	130184	0	0
CntNoWrap_A	7510225	6823986	0	0
DetectStDropOut_A	7510225	12	0	0
DetectedOut_A	7510225	209731	0	0
DetectedPulseOut_A	7510225	57	0	0
DisabledIdleSt_A	7510225	6139628	0	0
DisabledNoDetection_A	7510225	6142086	0	0
EnterDebounceSt_A	7510225	132	0	0
EnterDetectSt_A	7510225	69	0	0
EnterStableSt_A	7510225	57	0	0
PulseIsPulse_A	7510225	57	0	0
StayInStableSt	7510225	209674	0	0
gen_high_event_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_sticky_sva.StableStDropOut_A	7510225	223689	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	200	0	0
T8	1394	5	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	7259	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	2	0	0
T52	131225	0	0	0
T53	0	7	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	130184	0	0
T8	1394	190	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	50	0	0
T23	0	59	0	0
T25	7259	0	0	0
T33	0	10	0	0
T35	0	16	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	15	0	0
T52	131225	0	0	0
T53	0	693	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	40	0	0
T74	0	32	0	0
T75	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823986	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	12	0	0
T31	28011	0	0	0
T84	695	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T142	0	4	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	425	0	0	0
T148	503	0	0	0
T149	449	0	0	0
T150	402	0	0	0
T151	1671	0	0	0
T152	524	0	0	0
T153	32390	0	0	0
T154	953	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	209731	0	0
T22	860	230	0	0
T23	2232	271	0	0
T30	0	198	0	0
T33	0	50	0	0
T34	1103	0	0	0
T35	0	68	0	0
T46	0	23	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	98	0	0
T74	0	145	0	0
T84	0	1	0	0
T123	0	302	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	57	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T46	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T123	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6139628	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6142086	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	132	0	0
T8	1394	5	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T46	0	1	0	0
T52	131225	0	0	0
T53	0	7	0	0
T58	710	0	0	0
T59	437	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T46	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	57	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T46	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T123	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	57	0	0
T22	860	1	0	0
T23	2232	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	1103	0	0	0
T35	0	1	0	0
T46	0	1	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T123	0	1	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	209674	0	0
T22	860	229	0	0
T23	2232	270	0	0
T30	0	197	0	0
T33	0	49	0	0
T34	1103	0	0	0
T35	0	67	0	0
T46	0	22	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	97	0	0
T74	0	144	0	0
T94	0	649	0	0
T123	0	301	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	223689	0	0
T22	860	150	0	0
T23	2232	56	0	0
T30	0	151	0	0
T33	0	671	0	0
T34	1103	0	0	0
T35	0	682	0	0
T46	0	134	0	0
T61	491	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T67	807	0	0	0
T73	0	31	0	0
T74	0	342	0	0
T84	0	27	0	0
T123	0	374	0	0
T125	404	0	0	0
T126	431	0	0	0
T127	546	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T12,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T12,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T34
1	0	Covered	T1,T5,T6
1	1	Covered	T7,T12,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T34
0	1	Covered	T155,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T34
0	1	Covered	T12,T34,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T12,T34
1	-	Covered	T12,T34,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T34
DetectSt	168	Covered	T7,T12,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T12,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T34
DebounceSt->IdleSt	163	Covered	T75,T78
DetectSt->IdleSt	186	Covered	T155,T156
DetectSt->StableSt	191	Covered	T7,T12,T34
IdleSt->DebounceSt	148	Covered	T7,T12,T34
StableSt->IdleSt	206	Covered	T12,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T34
0	1	Covered	T7,T12,T34
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T34
DetectSt	-	-	-	-	1	-	-	Covered	T155,T156
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T34,T32
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	94	0	0
CntIncr_A	7510225	111056	0	0
CntNoWrap_A	7510225	6824092	0	0
DetectStDropOut_A	7510225	2	0	0
DetectedOut_A	7510225	25359	0	0
DetectedPulseOut_A	7510225	44	0	0
DisabledIdleSt_A	7510225	6405714	0	0
DisabledNoDetection_A	7510225	6408119	0	0
EnterDebounceSt_A	7510225	48	0	0
EnterDetectSt_A	7510225	46	0	0
EnterStableSt_A	7510225	44	0	0
PulseIsPulse_A	7510225	44	0	0
StayInStableSt	7510225	25289	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	94	0	0
T7	1122	2	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	8	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	4	0	0
T35	0	4	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	1	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	111056	0	0
T7	1122	100	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	176	0	0
T25	7259	0	0	0
T32	0	61	0	0
T33	0	189	0	0
T34	0	188	0	0
T35	0	126	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	42	0	0
T157	0	53	0	0
T158	0	56	0	0
T159	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824092	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2	0	0
T155	14510	1	0	0
T156	0	1	0	0
T160	502	0	0	0
T161	405	0	0	0
T162	428	0	0	0
T163	542	0	0	0
T164	800	0	0	0
T165	521	0	0	0
T166	521	0	0	0
T167	8955	0	0	0
T168	644	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	25359	0	0
T7	1122	381	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	335	0	0
T25	7259	0	0	0
T32	0	36	0	0
T33	0	83	0	0
T34	0	83	0	0
T35	0	82	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	43	0	0
T157	0	42	0	0
T158	0	46	0	0
T159	0	128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	44	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6405714	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6408119	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	48	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	46	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	44	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	44	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	25289	0	0
T7	1122	379	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	329	0	0
T25	7259	0	0	0
T32	0	35	0	0
T33	0	79	0	0
T34	0	81	0	0
T35	0	79	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T94	0	41	0	0
T157	0	40	0	0
T158	0	44	0	0
T159	0	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	18	0	0
T12	8563	2	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T103	0	1	0	0
T122	421	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T12
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T12
0	1	Covered	T80,T82,T174
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T12
0	1	Covered	T4,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T12
1	-	Covered	T4,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T12
DetectSt	168	Covered	T4,T9,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T12
DebounceSt->IdleSt	163	Covered	T4,T12,T75
DetectSt->IdleSt	186	Covered	T80,T82,T174
DetectSt->StableSt	191	Covered	T4,T9,T12
IdleSt->DebounceSt	148	Covered	T4,T9,T12
StableSt->IdleSt	206	Covered	T4,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T12
0	1	Covered	T4,T9,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T12,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T80,T82,T174
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	152	0	0
CntIncr_A	7510225	191142	0	0
CntNoWrap_A	7510225	6824034	0	0
DetectStDropOut_A	7510225	3	0	0
DetectedOut_A	7510225	76028	0	0
DetectedPulseOut_A	7510225	69	0	0
DisabledIdleSt_A	7510225	6411854	0	0
DisabledNoDetection_A	7510225	6414250	0	0
EnterDebounceSt_A	7510225	80	0	0
EnterDetectSt_A	7510225	72	0	0
EnterStableSt_A	7510225	69	0	0
PulseIsPulse_A	7510225	69	0	0
StayInStableSt	7510225	75928	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	2765	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	152	0	0
T4	2227	3	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	3	0	0
T24	0	2	0	0
T25	7259	0	0	0
T32	0	4	0	0
T33	0	6	0	0
T36	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	2	0	0
T80	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	191142	0	0
T4	2227	56	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	91	0	0
T10	16839	0	0	0
T12	0	104	0	0
T24	0	34	0	0
T25	7259	0	0	0
T32	0	122	0	0
T33	0	217	0	0
T36	0	51	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	72	0	0
T80	0	17376	0	0
T175	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824034	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	621	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3	0	0
T29	14138	0	0	0
T38	654	0	0	0
T39	9451	0	0	0
T57	1841	0	0	0
T80	35202	1	0	0
T82	0	1	0	0
T107	427	0	0	0
T108	528	0	0	0
T109	725	0	0	0
T110	430	0	0	0
T111	409	0	0	0
T174	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	76028	0	0
T4	2227	6	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	134	0	0
T10	16839	0	0	0
T12	0	10	0	0
T24	0	21	0	0
T25	7259	0	0	0
T32	0	160	0	0
T33	0	575	0	0
T35	0	53	0	0
T36	0	149	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	212	0	0
T175	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6411854	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6414250	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	80	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T36	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T80	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	72	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T36	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T80	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	75928	0	0
T4	2227	5	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	133	0	0
T10	16839	0	0	0
T12	0	9	0	0
T24	0	20	0	0
T25	7259	0	0	0
T32	0	157	0	0
T33	0	571	0	0
T35	0	52	0	0
T36	0	147	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	211	0	0
T175	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2765	0	0
T2	8913	40	0	0
T3	42261	12	0	0
T4	2227	2	0	0
T6	426	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	524	7	0	0
T14	10506	0	0	0
T15	490	5	0	0
T16	2025	10	0	0
T40	2013	4	0	0
T51	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	38	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T158	0	1	0	0
T176	0	1	0	0