Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T12,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T7,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T34
0	1	Covered	T9,T33,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T34
1	-	Covered	T9,T33,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T12
DetectSt	168	Covered	T9,T12,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T12,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T34
DebounceSt->IdleSt	163	Covered	T7,T75,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T12,T34
IdleSt->DebounceSt	148	Covered	T7,T9,T12
StableSt->IdleSt	206	Covered	T9,T12,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T12
0	1	Covered	T7,T9,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T33,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	74	0	0
CntIncr_A	7510225	2650	0	0
CntNoWrap_A	7510225	6824112	0	0
DetectStDropOut_A	7510225	0	0	0
DetectedOut_A	7510225	2996	0	0
DetectedPulseOut_A	7510225	35	0	0
DisabledIdleSt_A	7510225	6768997	0	0
DisabledNoDetection_A	7510225	6771400	0	0
EnterDebounceSt_A	7510225	39	0	0
EnterDetectSt_A	7510225	35	0	0
EnterStableSt_A	7510225	35	0	0
PulseIsPulse_A	7510225	35	0	0
StayInStableSt	7510225	2940	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	74	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	1	0	0
T82	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2650	0	0
T7	1122	100	0	0
T8	1394	0	0	0
T9	875	91	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	36	0	0
T25	7259	0	0	0
T33	0	182	0	0
T34	0	94	0	0
T35	0	63	0	0
T38	0	97	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	43	0	0
T82	0	43	0	0
T159	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824112	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2996	0	0
T9	875	15	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	156	0	0
T25	7259	0	0	0
T33	0	81	0	0
T34	0	41	0	0
T35	0	53	0	0
T38	0	42	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	65	0	0
T88	0	101	0	0
T159	0	10	0	0
T177	0	173	0	0
T178	780	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T159	0	1	0	0
T177	0	1	0	0
T178	780	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6768997	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6771400	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	39	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	0	1	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T52	131225	0	0	0
T58	710	0	0	0
T75	0	1	0	0
T82	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T159	0	1	0	0
T177	0	1	0	0
T178	780	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T159	0	1	0	0
T177	0	1	0	0
T178	780	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T159	0	1	0	0
T177	0	1	0	0
T178	780	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2940	0	0
T9	875	14	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	154	0	0
T25	7259	0	0	0
T33	0	78	0	0
T34	0	39	0	0
T35	0	52	0	0
T38	0	40	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	63	0	0
T88	0	100	0	0
T159	0	9	0	0
T177	0	171	0	0
T178	780	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	14	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	0	0	0
T25	7259	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T88	0	1	0	0
T103	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T178	780	0	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T12,T24,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T12,T24,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T12,T24,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T24,T137
1	0	Covered	T1,T5,T6
1	1	Covered	T12,T24,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T24,T36
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T24,T36
0	1	Covered	T12,T38,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T24,T36
1	-	Covered	T12,T38,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T24,T36
DetectSt	168	Covered	T12,T24,T36
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T12,T24,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T24,T36
DebounceSt->IdleSt	163	Covered	T33,T75,T180
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T12,T24,T36
IdleSt->DebounceSt	148	Covered	T12,T24,T36
StableSt->IdleSt	206	Covered	T12,T24,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T24,T36
0	1	Covered	T12,T24,T36
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T24,T36
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T24,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T24,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T180,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T24,T36
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T12,T24,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T38,T33
StableSt	-	-	-	-	-	-	0	Covered	T12,T24,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	138	0	0
CntIncr_A	7510225	123199	0	0
CntNoWrap_A	7510225	6824048	0	0
DetectStDropOut_A	7510225	1	0	0
DetectedOut_A	7510225	174953	0	0
DetectedPulseOut_A	7510225	64	0	0
DisabledIdleSt_A	7510225	6446175	0	0
DisabledNoDetection_A	7510225	6448573	0	0
EnterDebounceSt_A	7510225	73	0	0
EnterDetectSt_A	7510225	65	0	0
EnterStableSt_A	7510225	64	0	0
PulseIsPulse_A	7510225	64	0	0
StayInStableSt	7510225	174863	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	3117	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	138	0	0
T12	8563	2	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	2	0	0
T33	0	7	0	0
T36	0	2	0	0
T38	0	2	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	1	0	0
T80	0	2	0	0
T94	0	2	0	0
T122	421	0	0	0
T123	0	2	0	0
T182	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	123199	0	0
T12	8563	36	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	34	0	0
T33	0	314	0	0
T36	0	51	0	0
T38	0	97	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	42	0	0
T80	0	17376	0	0
T94	0	68	0	0
T122	421	0	0	0
T123	0	48	0	0
T182	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824048	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1	0	0
T81	55956	1	0	0
T97	5366	0	0	0
T183	3195	0	0	0
T184	410	0	0	0
T185	502	0	0	0
T186	27330	0	0	0
T187	404	0	0	0
T188	6981	0	0	0
T189	7895	0	0	0
T190	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	174953	0	0
T12	8563	135	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	37	0	0
T33	0	784	0	0
T36	0	149	0	0
T38	0	8	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	40	0	0
T82	0	331	0	0
T94	0	14	0	0
T122	421	0	0	0
T123	0	43	0	0
T182	0	178	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	64	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T33	0	3	0	0
T36	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T123	0	1	0	0
T182	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6446175	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6448573	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	73	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T33	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	1	0	0
T80	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T123	0	1	0	0
T182	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	65	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T33	0	3	0	0
T36	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T123	0	1	0	0
T182	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	64	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T33	0	3	0	0
T36	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T123	0	1	0	0
T182	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	64	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T33	0	3	0	0
T36	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T123	0	1	0	0
T182	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	174863	0	0
T12	8563	134	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	35	0	0
T33	0	779	0	0
T36	0	147	0	0
T38	0	7	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T80	0	38	0	0
T82	0	329	0	0
T94	0	13	0	0
T122	421	0	0	0
T123	0	41	0	0
T182	0	175	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3117	0	0
T2	8913	38	0	0
T3	42261	14	0	0
T4	2227	1	0	0
T5	682	3	0	0
T6	426	1	0	0
T7	0	2	0	0
T13	524	5	0	0
T14	10506	0	0	0
T15	490	3	0	0
T16	2025	7	0	0
T40	0	7	0	0
T51	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	38	0	0
T12	8563	1	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T44	677	0	0	0
T60	1414	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T87	0	1	0	0
T94	0	1	0	0
T122	421	0	0	0
T169	0	2	0	0
T170	0	2	0	0
T177	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T67,T103,T192
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T4,T7,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T7
1	-	Covered	T4,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T7
DetectSt	168	Covered	T2,T4,T7
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T7
DebounceSt->IdleSt	163	Covered	T75,T183,T78
DetectSt->IdleSt	186	Covered	T67,T103,T192
DetectSt->StableSt	191	Covered	T2,T4,T7
IdleSt->DebounceSt	148	Covered	T2,T4,T7
StableSt->IdleSt	206	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T193,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	1	-	-	Covered	T67,T103,T192
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	143	0	0
CntIncr_A	7510225	116223	0	0
CntNoWrap_A	7510225	6824043	0	0
DetectStDropOut_A	7510225	3	0	0
DetectedOut_A	7510225	75447	0	0
DetectedPulseOut_A	7510225	66	0	0
DisabledIdleSt_A	7510225	6553419	0	0
DisabledNoDetection_A	7510225	6555817	0	0
EnterDebounceSt_A	7510225	74	0	0
EnterDetectSt_A	7510225	69	0	0
EnterStableSt_A	7510225	66	0	0
PulseIsPulse_A	7510225	66	0	0
StayInStableSt	7510225	75351	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	143	0	0
T2	8913	2	0	0
T3	42261	0	0	0
T4	2227	4	0	0
T7	0	2	0	0
T12	0	4	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	4	0	0
T137	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	116223	0	0
T2	8913	28	0	0
T3	42261	0	0	0
T4	2227	56	0	0
T7	0	100	0	0
T12	0	104	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	34	0	0
T36	0	51	0	0
T37	0	73	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	144	0	0
T137	0	90	0	0
T157	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824043	0	0
T1	19868	19426	0	0
T2	8913	2733	0	0
T3	42261	39751	0	0
T4	2227	620	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3	0	0
T45	19308	0	0	0
T46	3687	0	0	0
T47	10973	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	1	0	0
T103	0	1	0	0
T127	546	0	0	0
T192	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	75447	0	0
T2	8913	98	0	0
T3	42261	0	0	0
T4	2227	115	0	0
T7	0	43	0	0
T12	0	157	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	20	0	0
T36	0	53	0	0
T37	0	44	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	40	0	0
T137	0	88	0	0
T157	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	66	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	1	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	1	0	0
T137	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6553419	0	0
T1	19868	19426	0	0
T2	8913	2604	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6555817	0	0
T1	19868	19433	0	0
T2	8913	2621	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	74	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	1	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	2	0	0
T137	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	1	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	2	0	0
T137	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	66	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	1	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	1	0	0
T137	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	66	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	1	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	1	0	0
T137	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	75351	0	0
T2	8913	96	0	0
T3	42261	0	0	0
T4	2227	112	0	0
T7	0	42	0	0
T12	0	154	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	19	0	0
T36	0	51	0	0
T37	0	42	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T67	0	38	0	0
T137	0	87	0	0
T157	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	36	0	0
T4	2227	1	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	3	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T137	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T24,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T24,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T24,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T24,T34
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T24,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T24,T34
0	1	Covered	T198
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T24,T34
0	1	Covered	T4,T34,T67
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T24,T34
1	-	Covered	T4,T34,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T24,T34
DetectSt	168	Covered	T4,T24,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T24,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T24,T34
DebounceSt->IdleSt	163	Covered	T75,T78
DetectSt->IdleSt	186	Covered	T198
DetectSt->StableSt	191	Covered	T4,T24,T34
IdleSt->DebounceSt	148	Covered	T4,T24,T34
StableSt->IdleSt	206	Covered	T4,T24,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T24,T34
0	1	Covered	T4,T24,T34
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T24,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T24,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T24,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T24,T34
DetectSt	-	-	-	-	1	-	-	Covered	T198
DetectSt	-	-	-	-	0	1	-	Covered	T4,T24,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T34,T67
StableSt	-	-	-	-	-	-	0	Covered	T4,T24,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	76	0	0
CntIncr_A	7510225	14451	0	0
CntNoWrap_A	7510225	6824110	0	0
DetectStDropOut_A	7510225	1	0	0
DetectedOut_A	7510225	9694	0	0
DetectedPulseOut_A	7510225	36	0	0
DisabledIdleSt_A	7510225	6763632	0	0
DisabledNoDetection_A	7510225	6766040	0	0
EnterDebounceSt_A	7510225	39	0	0
EnterDetectSt_A	7510225	37	0	0
EnterStableSt_A	7510225	36	0	0
PulseIsPulse_A	7510225	36	0	0
StayInStableSt	7510225	9636	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	6890	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	76	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	2	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	2	0	0
T75	0	1	0	0
T81	0	2	0	0
T137	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	14451	0	0
T4	2227	28	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	34	0	0
T25	7259	0	0	0
T33	0	98	0	0
T34	0	94	0	0
T35	0	63	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	72	0	0
T75	0	41	0	0
T81	0	57	0	0
T137	0	90	0	0
T176	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824110	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	622	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1	0	0
T198	20575	1	0	0
T199	427	0	0	0
T200	503	0	0	0
T201	438	0	0	0
T202	2576	0	0	0
T203	776	0	0	0
T204	10558	0	0	0
T205	495	0	0	0
T206	501	0	0	0
T207	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9694	0	0
T4	2227	62	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	38	0	0
T25	7259	0	0	0
T33	0	80	0	0
T34	0	16	0	0
T35	0	157	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	139	0	0
T81	0	76	0	0
T137	0	43	0	0
T176	0	40	0	0
T208	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	36	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T81	0	1	0	0
T137	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6763632	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6766040	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	39	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T81	0	1	0	0
T137	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	37	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T81	0	1	0	0
T137	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	36	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T81	0	1	0	0
T137	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	36	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T81	0	1	0	0
T137	0	1	0	0
T176	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9636	0	0
T4	2227	61	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	36	0	0
T25	7259	0	0	0
T33	0	79	0	0
T34	0	15	0	0
T35	0	156	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	138	0	0
T81	0	74	0	0
T137	0	41	0	0
T176	0	38	0	0
T208	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6890	0	0
T1	19868	13	0	0
T2	8913	36	0	0
T3	42261	27	0	0
T4	2227	1	0	0
T5	682	0	0	0
T6	426	2	0	0
T13	524	5	0	0
T14	10506	33	0	0
T15	490	7	0	0
T16	2025	7	0	0
T40	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	14	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T25	7259	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T88	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T12,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T9,T12,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T12,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T34
1	0	Covered	T1,T6,T2
1	1	Covered	T9,T12,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T34
0	1	Covered	T87,T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T34
0	1	Covered	T9,T12,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T34
1	-	Covered	T9,T12,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T34
DetectSt	168	Covered	T9,T12,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T12,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T34
DebounceSt->IdleSt	163	Covered	T75,T197,T78
DetectSt->IdleSt	186	Covered	T87,T210
DetectSt->StableSt	191	Covered	T9,T12,T34
IdleSt->DebounceSt	148	Covered	T9,T12,T34
StableSt->IdleSt	206	Covered	T9,T12,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T34
0	1	Covered	T9,T12,T34
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T197,T211,T202
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T34
DetectSt	-	-	-	-	1	-	-	Covered	T87,T210
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	130	0	0
CntIncr_A	7510225	106005	0	0
CntNoWrap_A	7510225	6824056	0	0
DetectStDropOut_A	7510225	2	0	0
DetectedOut_A	7510225	119107	0	0
DetectedPulseOut_A	7510225	61	0	0
DisabledIdleSt_A	7510225	6447362	0	0
DisabledNoDetection_A	7510225	6449763	0	0
EnterDebounceSt_A	7510225	68	0	0
EnterDetectSt_A	7510225	63	0	0
EnterStableSt_A	7510225	60	0	0
PulseIsPulse_A	7510225	60	0	0
StayInStableSt	7510225	119022	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	130	0	0
T9	875	2	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	2	0	0
T25	7259	0	0	0
T32	0	4	0	0
T33	0	4	0	0
T34	0	4	0	0
T38	0	2	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	2	0	0
T75	0	1	0	0
T128	0	4	0	0
T176	0	2	0	0
T178	780	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	106005	0	0
T9	875	91	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	36	0	0
T25	7259	0	0	0
T32	0	122	0	0
T33	0	182	0	0
T34	0	188	0	0
T38	0	97	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	72	0	0
T75	0	42	0	0
T128	0	158	0	0
T176	0	97	0	0
T178	780	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824056	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2	0	0
T87	674	1	0	0
T99	5116	0	0	0
T210	0	1	0	0
T212	524	0	0	0
T213	494	0	0	0
T214	23684	0	0	0
T215	409	0	0	0
T216	424	0	0	0
T217	5516	0	0	0
T218	418	0	0	0
T219	6861	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	119107	0	0
T9	875	13	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	44	0	0
T25	7259	0	0	0
T32	0	184	0	0
T33	0	107	0	0
T34	0	368	0	0
T38	0	9	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	325	0	0
T128	0	219	0	0
T159	0	83	0	0
T176	0	206	0	0
T178	780	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	61	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	1	0	0
T128	0	2	0	0
T159	0	2	0	0
T176	0	1	0	0
T178	780	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6447362	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6449763	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	68	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T128	0	2	0	0
T176	0	1	0	0
T178	780	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	63	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	1	0	0
T128	0	2	0	0
T159	0	2	0	0
T176	0	1	0	0
T178	780	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	60	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	1	0	0
T128	0	2	0	0
T159	0	2	0	0
T176	0	1	0	0
T178	780	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	60	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	1	0	0
T128	0	2	0	0
T159	0	2	0	0
T176	0	1	0	0
T178	780	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	119022	0	0
T9	875	12	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	43	0	0
T25	7259	0	0	0
T32	0	181	0	0
T33	0	104	0	0
T34	0	365	0	0
T38	0	8	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T67	0	323	0	0
T128	0	217	0	0
T159	0	80	0	0
T176	0	204	0	0
T178	780	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T9	875	1	0	0
T10	16839	0	0	0
T11	32311	0	0	0
T12	8563	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T42	778	0	0	0
T43	38538	0	0	0
T58	710	0	0	0
T59	437	0	0	0
T82	0	2	0	0
T94	0	1	0	0
T128	0	1	0	0
T159	0	1	0	0
T178	780	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T4,T7,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T7
1	-	Covered	T4,T7,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T7
DetectSt	168	Covered	T2,T4,T7
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T7
DebounceSt->IdleSt	163	Covered	T75,T35,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T4,T7
IdleSt->DebounceSt	148	Covered	T2,T4,T7
StableSt->IdleSt	206	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T35
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	87	0	0
CntIncr_A	7510225	53637	0	0
CntNoWrap_A	7510225	6824099	0	0
DetectStDropOut_A	7510225	0	0	0
DetectedOut_A	7510225	60197	0	0
DetectedPulseOut_A	7510225	42	0	0
DisabledIdleSt_A	7510225	6447057	0	0
DisabledNoDetection_A	7510225	6449456	0	0
EnterDebounceSt_A	7510225	45	0	0
EnterDetectSt_A	7510225	42	0	0
EnterStableSt_A	7510225	42	0	0
PulseIsPulse_A	7510225	42	0	0
StayInStableSt	7510225	60133	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	6382	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	87	0	0
T2	8913	2	0	0
T3	42261	0	0	0
T4	2227	4	0	0
T7	0	6	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	1	0	0
T94	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	53637	0	0
T2	8913	28	0	0
T3	42261	0	0	0
T4	2227	56	0	0
T7	0	300	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	61	0	0
T33	0	181	0	0
T34	0	94	0	0
T35	0	63	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	43	0	0
T94	0	69	0	0
T175	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824099	0	0
T1	19868	19426	0	0
T2	8913	2733	0	0
T3	42261	39751	0	0
T4	2227	620	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	60197	0	0
T2	8913	50	0	0
T3	42261	0	0	0
T4	2227	187	0	0
T7	0	124	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	116	0	0
T33	0	374	0	0
T34	0	42	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	83	0	0
T94	0	41	0	0
T175	0	45	0	0
T220	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	42	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	1	0	0
T94	0	1	0	0
T175	0	1	0	0
T220	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6447057	0	0
T1	19868	19426	0	0
T2	8913	2604	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6449456	0	0
T1	19868	19433	0	0
T2	8913	2621	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	45	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	1	0	0
T94	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	42	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	1	0	0
T94	0	1	0	0
T175	0	1	0	0
T220	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	42	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	1	0	0
T94	0	1	0	0
T175	0	1	0	0
T220	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	42	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T7	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	1	0	0
T94	0	1	0	0
T175	0	1	0	0
T220	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	60133	0	0
T2	8913	48	0	0
T3	42261	0	0	0
T4	2227	184	0	0
T7	0	120	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T32	0	115	0	0
T33	0	372	0	0
T34	0	41	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T81	0	82	0	0
T94	0	40	0	0
T175	0	43	0	0
T220	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6382	0	0
T1	19868	12	0	0
T2	8913	36	0	0
T3	42261	27	0	0
T4	2227	3	0	0
T5	682	0	0	0
T6	426	1	0	0
T13	524	4	0	0
T14	10506	28	0	0
T15	490	9	0	0
T16	2025	6	0	0
T40	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	20	0	0
T4	2227	1	0	0
T7	1122	2	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0