Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T34,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T34,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T34,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T37,T80
1	0	Covered	T1,T6,T2
1	1	Covered	T34,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Covered	T34,T37,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T37,T38
1	-	Covered	T34,T37,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T37,T38
DetectSt	168	Covered	T34,T37,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T34,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T37,T38
DebounceSt->IdleSt	163	Covered	T75,T35,T197
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T34,T37,T38
IdleSt->DebounceSt	148	Covered	T34,T37,T38
StableSt->IdleSt	206	Covered	T34,T37,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T37,T38
0	1	Covered	T34,T37,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T37,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T197,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T37,T33
StableSt	-	-	-	-	-	-	0	Covered	T34,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	142	0	0
CntIncr_A	7510225	21186	0	0
CntNoWrap_A	7510225	6824044	0	0
DetectStDropOut_A	7510225	0	0	0
DetectedOut_A	7510225	23538	0	0
DetectedPulseOut_A	7510225	67	0	0
DisabledIdleSt_A	7510225	6735058	0	0
DisabledNoDetection_A	7510225	6737461	0	0
EnterDebounceSt_A	7510225	75	0	0
EnterDetectSt_A	7510225	67	0	0
EnterStableSt_A	7510225	67	0	0
PulseIsPulse_A	7510225	67	0	0
StayInStableSt	7510225	23438	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	142	0	0
T33	0	8	0	0
T34	1103	4	0	0
T35	0	3	0	0
T37	0	2	0	0
T38	0	2	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T75	0	1	0	0
T94	0	3	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	4	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T197	0	1	0	0
T223	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	21186	0	0
T33	0	362	0	0
T34	1103	188	0	0
T35	0	126	0	0
T37	0	73	0	0
T38	0	97	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T75	0	43	0	0
T94	0	137	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	194	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T197	0	25	0	0
T223	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824044	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	23538	0	0
T33	0	539	0	0
T34	1103	195	0	0
T35	0	3	0	0
T37	0	8	0	0
T38	0	42	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	139	0	0
T94	0	43	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	88	0	0
T183	0	45	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T33	0	4	0	0
T34	1103	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	2	0	0
T94	0	1	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	2	0	0
T183	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6735058	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6737461	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	75	0	0
T33	0	4	0	0
T34	1103	2	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T75	0	1	0	0
T94	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	2	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T197	0	1	0	0
T223	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T33	0	4	0	0
T34	1103	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	2	0	0
T94	0	1	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	2	0	0
T183	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T33	0	4	0	0
T34	1103	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	2	0	0
T94	0	1	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	2	0	0
T183	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T33	0	4	0	0
T34	1103	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	2	0	0
T94	0	1	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	2	0	0
T183	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	23438	0	0
T33	0	533	0	0
T34	1103	193	0	0
T35	0	2	0	0
T37	0	7	0	0
T38	0	40	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	137	0	0
T94	0	41	0	0
T126	431	0	0	0
T127	546	0	0	0
T176	0	85	0	0
T183	0	43	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T223	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	34	0	0
T33	0	2	0	0
T34	1103	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T81	0	2	0	0
T87	0	1	0	0
T88	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T155	0	3	0	0
T176	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T34,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T34,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T34,T33,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T34,T137
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T34,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T33,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T33,T35
0	1	Covered	T34,T33,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T33,T35
1	-	Covered	T34,T33,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T34,T33
DetectSt	168	Covered	T34,T33,T35
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T34,T33,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T33,T35
DebounceSt->IdleSt	163	Covered	T4,T75,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T34,T33,T35
IdleSt->DebounceSt	148	Covered	T4,T34,T33
StableSt->IdleSt	206	Covered	T34,T33,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T34,T33
0	1	Covered	T4,T34,T33
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T33,T35
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T34,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T33,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T4
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T34,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T34,T33,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T33,T35
StableSt	-	-	-	-	-	-	0	Covered	T34,T33,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	73	0	0
CntIncr_A	7510225	104169	0	0
CntNoWrap_A	7510225	6824113	0	0
DetectStDropOut_A	7510225	0	0	0
DetectedOut_A	7510225	2792	0	0
DetectedPulseOut_A	7510225	35	0	0
DisabledIdleSt_A	7510225	6165012	0	0
DisabledNoDetection_A	7510225	6167421	0	0
EnterDebounceSt_A	7510225	38	0	0
EnterDetectSt_A	7510225	35	0	0
EnterStableSt_A	7510225	35	0	0
PulseIsPulse_A	7510225	35	0	0
StayInStableSt	7510225	2744	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	6369	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	73	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T25	7259	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T35	0	4	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T75	0	1	0	0
T87	0	2	0	0
T88	0	4	0	0
T128	0	2	0	0
T182	0	2	0	0
T221	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	104169	0	0
T4	2227	28	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T25	7259	0	0	0
T33	0	181	0	0
T34	0	188	0	0
T35	0	126	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T75	0	41	0	0
T87	0	26	0	0
T88	0	114	0	0
T128	0	79	0	0
T182	0	49	0	0
T221	0	134	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824113	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	623	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2792	0	0
T33	0	373	0	0
T34	1103	120	0	0
T35	0	222	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	70	0	0
T88	0	80	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	64	0	0
T155	0	39	0	0
T177	0	40	0	0
T182	0	35	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T33	0	2	0	0
T34	1103	2	0	0
T35	0	2	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	1	0	0
T155	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6165012	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6167421	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	38	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T25	7259	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T75	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T128	0	1	0	0
T182	0	1	0	0
T221	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T33	0	2	0	0
T34	1103	2	0	0
T35	0	2	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	1	0	0
T155	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T33	0	2	0	0
T34	1103	2	0	0
T35	0	2	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	1	0	0
T155	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T33	0	2	0	0
T34	1103	2	0	0
T35	0	2	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	1	0	0
T155	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2744	0	0
T33	0	371	0	0
T34	1103	117	0	0
T35	0	219	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	69	0	0
T88	0	77	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	63	0	0
T155	0	37	0	0
T177	0	39	0	0
T182	0	34	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6369	0	0
T1	19868	9	0	0
T2	8913	34	0	0
T3	42261	24	0	0
T4	2227	2	0	0
T5	682	0	0	0
T6	426	1	0	0
T13	524	4	0	0
T14	10506	24	0	0
T15	490	4	0	0
T16	2025	9	0	0
T40	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	22	0	0
T33	0	2	0	0
T34	1103	1	0	0
T35	0	1	0	0
T45	19308	0	0	0
T53	1336	0	0	0
T54	2254	0	0	0
T67	807	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T126	431	0	0	0
T127	546	0	0	0
T128	0	1	0	0
T171	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T194	445	0	0	0
T195	512	0	0	0
T196	424	0	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T12,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T24
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T24
0	1	Covered	T88,T203,T224
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T24
0	1	Covered	T4,T24,T67
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T12,T24
1	-	Covered	T4,T24,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T24
DetectSt	168	Covered	T4,T12,T24
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T12,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T24
DebounceSt->IdleSt	163	Covered	T75,T197,T179
DetectSt->IdleSt	186	Covered	T88,T203,T224
DetectSt->StableSt	191	Covered	T4,T12,T24
IdleSt->DebounceSt	148	Covered	T4,T12,T24
StableSt->IdleSt	206	Covered	T4,T12,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T12,T24
0	1	Covered	T4,T12,T24
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T24
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T197,T179,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T24
DetectSt	-	-	-	-	1	-	-	Covered	T88,T203,T224
DetectSt	-	-	-	-	0	1	-	Covered	T4,T12,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T24,T67
StableSt	-	-	-	-	-	-	0	Covered	T4,T12,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	126	0	0
CntIncr_A	7510225	60465	0	0
CntNoWrap_A	7510225	6824060	0	0
DetectStDropOut_A	7510225	3	0	0
DetectedOut_A	7510225	45042	0	0
DetectedPulseOut_A	7510225	56	0	0
DisabledIdleSt_A	7510225	6372982	0	0
DisabledNoDetection_A	7510225	6375386	0	0
EnterDebounceSt_A	7510225	67	0	0
EnterDetectSt_A	7510225	59	0	0
EnterStableSt_A	7510225	56	0	0
PulseIsPulse_A	7510225	56	0	0
StayInStableSt	7510225	44965	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	126	0	0
T4	2227	4	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	2	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	2	0	0
T75	0	1	0	0
T123	0	2	0	0
T128	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	60465	0	0
T4	2227	56	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	36	0	0
T24	0	34	0	0
T25	7259	0	0	0
T32	0	61	0	0
T33	0	28	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	72	0	0
T75	0	43	0	0
T123	0	48	0	0
T128	0	79	0	0
T157	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824060	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	620	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3	0	0
T88	6628	1	0	0
T169	9207	0	0	0
T177	690	0	0	0
T203	0	1	0	0
T224	0	1	0	0
T225	422	0	0	0
T226	402	0	0	0
T227	9625	0	0	0
T228	12542	0	0	0
T229	402	0	0	0
T230	5821	0	0	0
T231	732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	45042	0	0
T4	2227	169	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	40	0	0
T24	0	21	0	0
T25	7259	0	0	0
T32	0	140	0	0
T33	0	85	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	24	0	0
T123	0	1	0	0
T128	0	44	0	0
T157	0	42	0	0
T176	0	157	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	56	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6372982	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6375386	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	59	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	56	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	56	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	1	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	44965	0	0
T4	2227	166	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T12	0	38	0	0
T24	0	20	0	0
T25	7259	0	0	0
T32	0	139	0	0
T33	0	83	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	23	0	0
T94	0	38	0	0
T128	0	42	0	0
T157	0	40	0	0
T176	0	156	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	0	0	0
T10	16839	0	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T67	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T87	0	2	0	0
T94	0	1	0	0
T123	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T24,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T24,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T24,T66
1	0	Covered	T1,T6,T2
1	1	Covered	T24,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T32,T33
0	1	Covered	T232
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T32,T33
0	1	Covered	T33,T87,T177
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T32,T33
1	-	Covered	T33,T87,T177

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T32,T33
DetectSt	168	Covered	T24,T32,T33
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T24,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T32,T33
DebounceSt->IdleSt	163	Covered	T75,T78,T103
DetectSt->IdleSt	186	Covered	T232
DetectSt->StableSt	191	Covered	T24,T32,T33
IdleSt->DebounceSt	148	Covered	T24,T32,T33
StableSt->IdleSt	206	Covered	T24,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T32,T33
0	1	Covered	T24,T32,T33
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T32,T33
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T103,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T32,T33
DetectSt	-	-	-	-	1	-	-	Covered	T232
DetectSt	-	-	-	-	0	1	-	Covered	T24,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T87,T177
StableSt	-	-	-	-	-	-	0	Covered	T24,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	86	0	0
CntIncr_A	7510225	59546	0	0
CntNoWrap_A	7510225	6824100	0	0
DetectStDropOut_A	7510225	1	0	0
DetectedOut_A	7510225	3390	0	0
DetectedPulseOut_A	7510225	40	0	0
DisabledIdleSt_A	7510225	6405177	0	0
DisabledNoDetection_A	7510225	6407576	0	0
EnterDebounceSt_A	7510225	45	0	0
EnterDetectSt_A	7510225	41	0	0
EnterStableSt_A	7510225	40	0	0
PulseIsPulse_A	7510225	40	0	0
StayInStableSt	7510225	3322	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	6362	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	86	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	2	0	0
T32	0	2	0	0
T33	0	8	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	1	0	0
T82	0	2	0	0
T87	0	4	0	0
T123	0	2	0	0
T125	404	0	0	0
T155	0	2	0	0
T169	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	59546	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	34	0	0
T32	0	61	0	0
T33	0	384	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	42	0	0
T82	0	55	0	0
T87	0	52	0	0
T123	0	48	0	0
T125	404	0	0	0
T155	0	98	0	0
T169	0	83	0	0
T177	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824100	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1	0	0
T232	2875	1	0	0
T233	6691	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3390	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	37	0	0
T32	0	45	0	0
T33	0	788	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	59	0	0
T87	0	48	0	0
T123	0	43	0	0
T125	404	0	0	0
T155	0	41	0	0
T163	0	114	0	0
T169	0	38	0	0
T177	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	40	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T155	0	1	0	0
T163	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6405177	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6407576	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	45	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T75	0	1	0	0
T82	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T155	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	41	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T155	0	1	0	0
T163	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	40	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T155	0	1	0	0
T163	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	40	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T125	404	0	0	0
T155	0	1	0	0
T163	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	3322	0	0
T22	860	0	0	0
T23	2232	0	0	0
T24	8505	35	0	0
T32	0	43	0	0
T33	0	782	0	0
T44	677	0	0	0
T60	1414	0	0	0
T61	491	0	0	0
T64	551	0	0	0
T65	524	0	0	0
T66	539	0	0	0
T82	0	57	0	0
T87	0	45	0	0
T123	0	41	0	0
T125	404	0	0	0
T155	0	39	0	0
T163	0	112	0	0
T169	0	36	0	0
T177	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6362	0	0
T1	19868	10	0	0
T2	8913	35	0	0
T3	42261	29	0	0
T4	2227	2	0	0
T5	682	0	0	0
T6	426	3	0	0
T13	524	5	0	0
T14	10506	30	0	0
T15	490	6	0	0
T16	2025	8	0	0
T40	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	12	0	0
T33	32293	2	0	0
T35	8266	0	0	0
T75	7832	0	0	0
T76	8060	0	0	0
T87	0	1	0	0
T143	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0
T177	0	1	0	0
T179	0	1	0	0
T203	0	1	0	0
T223	515	0	0	0
T234	0	1	0	0
T235	0	1	0	0
T236	425	0	0	0
T237	1152	0	0	0
T238	527	0	0	0
T239	405	0	0	0
T240	490	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T12
0	1	Covered	T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T12
0	1	Covered	T4,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T12
1	-	Covered	T4,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T9
DetectSt	168	Covered	T4,T9,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T12
DebounceSt->IdleSt	163	Covered	T2,T75,T183
DetectSt->IdleSt	186	Covered	T177
DetectSt->StableSt	191	Covered	T4,T9,T12
IdleSt->DebounceSt	148	Covered	T2,T4,T9
StableSt->IdleSt	206	Covered	T4,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T12
0	1	Covered	T2,T4,T9
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T155,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T177
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	138	0	0
CntIncr_A	7510225	16131	0	0
CntNoWrap_A	7510225	6824048	0	0
DetectStDropOut_A	7510225	1	0	0
DetectedOut_A	7510225	16549	0	0
DetectedPulseOut_A	7510225	63	0	0
DisabledIdleSt_A	7510225	6729198	0	0
DisabledNoDetection_A	7510225	6731600	0	0
EnterDebounceSt_A	7510225	75	0	0
EnterDetectSt_A	7510225	64	0	0
EnterStableSt_A	7510225	63	0	0
PulseIsPulse_A	7510225	63	0	0
StayInStableSt	7510225	16457	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	138	0	0
T4	2227	4	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	4	0	0
T10	16839	0	0	0
T12	0	4	0	0
T24	0	2	0	0
T25	7259	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T75	0	1	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	16131	0	0
T2	8913	5	0	0
T3	42261	0	0	0
T4	2227	56	0	0
T9	0	182	0	0
T12	0	72	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	34	0	0
T32	0	122	0	0
T33	0	28	0	0
T34	0	94	0	0
T37	0	73	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T157	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824048	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	620	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1	0	0
T169	9207	0	0	0
T177	690	1	0	0
T226	402	0	0	0
T227	9625	0	0	0
T228	12542	0	0	0
T229	402	0	0	0
T230	5821	0	0	0
T231	732	0	0	0
T241	717	0	0	0
T242	433	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	16549	0	0
T4	2227	7	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	84	0	0
T10	16839	0	0	0
T12	0	98	0	0
T24	0	93	0	0
T25	7259	0	0	0
T32	0	86	0	0
T33	0	38	0	0
T34	0	351	0	0
T35	0	85	0	0
T37	0	44	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	63	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6729198	0	0
T1	19868	19426	0	0
T2	8913	2604	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6731600	0	0
T1	19868	19433	0	0
T2	8913	2621	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	75	0	0
T2	8913	1	0	0
T3	42261	0	0	0
T4	2227	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	64	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	63	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	63	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	2	0	0
T24	0	1	0	0
T25	7259	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	16457	0	0
T4	2227	5	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	81	0	0
T10	16839	0	0	0
T12	0	96	0	0
T24	0	91	0	0
T25	7259	0	0	0
T32	0	83	0	0
T33	0	36	0	0
T34	0	350	0	0
T35	0	81	0	0
T37	0	42	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T157	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	34	0	0
T4	2227	2	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T81	0	2	0	0
T82	0	2	0	0
T157	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T6,T2
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T4,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T9
1	-	Covered	T4,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T4,T7,T9
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T9
DebounceSt->IdleSt	163	Covered	T75,T35,T170
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T7,T9
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T4,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	106	0	0
CntIncr_A	7510225	15076	0	0
CntNoWrap_A	7510225	6824080	0	0
DetectStDropOut_A	7510225	0	0	0
DetectedOut_A	7510225	9852	0	0
DetectedPulseOut_A	7510225	51	0	0
DisabledIdleSt_A	7510225	6760728	0	0
DisabledNoDetection_A	7510225	6763127	0	0
EnterDebounceSt_A	7510225	55	0	0
EnterDetectSt_A	7510225	51	0	0
EnterStableSt_A	7510225	51	0	0
PulseIsPulse_A	7510225	51	0	0
StayInStableSt	7510225	9777	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7510225	7160	0	0
gen_low_level_sva.LowLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	106	0	0
T4	2227	4	0	0
T7	1122	2	0	0
T8	1394	0	0	0
T9	875	2	0	0
T10	16839	0	0	0
T12	0	4	0	0
T25	7259	0	0	0
T34	0	2	0	0
T35	0	3	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T157	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	15076	0	0
T4	2227	56	0	0
T7	1122	100	0	0
T8	1394	0	0	0
T9	875	91	0	0
T10	16839	0	0	0
T12	0	72	0	0
T25	7259	0	0	0
T34	0	94	0	0
T35	0	126	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	40	0	0
T75	0	41	0	0
T157	0	53	0	0
T176	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6824080	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	620	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9852	0	0
T4	2227	176	0	0
T7	1122	126	0	0
T8	1394	0	0	0
T9	875	14	0	0
T10	16839	0	0	0
T12	0	119	0	0
T25	7259	0	0	0
T34	0	41	0	0
T35	0	51	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	38	0	0
T157	0	42	0	0
T176	0	68	0	0
T182	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	51	0	0
T4	2227	2	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6760728	0	0
T1	19868	19426	0	0
T2	8913	2604	0	0
T3	42261	39751	0	0
T4	2227	320	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6763127	0	0
T1	19868	19433	0	0
T2	8913	2621	0	0
T3	42261	39772	0	0
T4	2227	322	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	55	0	0
T4	2227	2	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	51	0	0
T4	2227	2	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	51	0	0
T4	2227	2	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	51	0	0
T4	2227	2	0	0
T7	1122	1	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	2	0	0
T25	7259	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	9777	0	0
T4	2227	173	0	0
T7	1122	124	0	0
T8	1394	0	0	0
T9	875	13	0	0
T10	16839	0	0	0
T12	0	116	0	0
T25	7259	0	0	0
T34	0	39	0	0
T35	0	50	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T66	0	36	0	0
T157	0	40	0	0
T176	0	67	0	0
T182	0	122	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	7160	0	0
T1	19868	13	0	0
T2	8913	37	0	0
T3	42261	33	0	0
T4	2227	5	0	0
T5	682	0	0	0
T6	426	2	0	0
T13	524	3	0	0
T14	10506	28	0	0
T15	490	9	0	0
T16	2025	10	0	0
T40	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	27	0	0
T4	2227	1	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T9	875	1	0	0
T10	16839	0	0	0
T12	0	1	0	0
T25	7259	0	0	0
T35	0	1	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T52	131225	0	0	0
T81	0	2	0	0
T82	0	1	0	0
T169	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0
T191	0	1	0	0