Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T25,T10
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T25,T10
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T69,T71,T91
1	0	Covered	T68,T75,T243

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T25,T10
1	-	Covered	T14,T25,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T25,T10
DetectSt	168	Covered	T14,T25,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T14,T25,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T25,T10
DebounceSt->IdleSt	163	Covered	T75,T244,T78
DetectSt->IdleSt	186	Covered	T68,T69,T71
DetectSt->StableSt	191	Covered	T14,T25,T10
IdleSt->DebounceSt	148	Covered	T14,T25,T10
StableSt->IdleSt	206	Covered	T14,T25,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T25,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T14,T25,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T25,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T244,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T68,T69,T71
DetectSt	-	-	-	-	0	1	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	1	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	0	Covered	T14,T25,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	2973	0	0
CntIncr_A	7510225	100457	0	0
CntNoWrap_A	7510225	6821213	0	0
DetectStDropOut_A	7510225	477	0	0
DetectedOut_A	7510225	68811	0	0
DetectedPulseOut_A	7510225	813	0	0
DisabledIdleSt_A	7510225	6395938	0	0
DisabledNoDetection_A	7510225	6398223	0	0
EnterDebounceSt_A	7510225	1492	0	0
EnterDetectSt_A	7510225	1481	0	0
EnterStableSt_A	7510225	813	0	0
PulseIsPulse_A	7510225	813	0	0
StayInStableSt	7510225	67912	0	0
gen_high_event_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	718	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2973	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	46	0	0
T11	0	22	0	0
T14	10506	48	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	28	0	0
T39	0	22	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	54	0	0
T51	402	0	0	0
T68	0	30	0	0
T69	0	54	0	0
T70	0	8	0	0
T71	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	100457	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	943	0	0
T11	0	836	0	0
T14	10506	1536	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	826	0	0
T39	0	814	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	1971	0	0
T51	402	0	0	0
T68	0	930	0	0
T69	0	1135	0	0
T70	0	156	0	0
T71	0	159	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6821213	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10047	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	477	0	0
T29	14138	0	0	0
T39	9451	0	0	0
T57	1841	0	0	0
T69	4723	27	0	0
T70	24730	0	0	0
T71	5315	3	0	0
T75	0	1	0	0
T80	35202	0	0	0
T90	671	0	0	0
T91	0	21	0	0
T92	0	29	0	0
T93	0	18	0	0
T96	0	8	0	0
T97	0	10	0	0
T99	0	32	0	0
T107	427	0	0	0
T217	0	8	0	0
T245	657	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	68811	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	1544	0	0
T11	0	2148	0	0
T14	10506	2145	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	1354	0	0
T39	0	519	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	878	0	0
T51	402	0	0	0
T70	0	208	0	0
T246	0	85	0	0
T247	0	2411	0	0
T248	0	3390	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	813	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	23	0	0
T11	0	11	0	0
T14	10506	24	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	27	0	0
T51	402	0	0	0
T70	0	4	0	0
T246	0	1	0	0
T247	0	25	0	0
T248	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6395938	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	4062	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6398223	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	4062	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1492	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	23	0	0
T11	0	11	0	0
T14	10506	24	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	27	0	0
T51	402	0	0	0
T68	0	15	0	0
T69	0	27	0	0
T70	0	4	0	0
T71	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1481	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	23	0	0
T11	0	11	0	0
T14	10506	24	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	27	0	0
T51	402	0	0	0
T68	0	15	0	0
T69	0	27	0	0
T70	0	4	0	0
T71	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	813	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	23	0	0
T11	0	11	0	0
T14	10506	24	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	27	0	0
T51	402	0	0	0
T70	0	4	0	0
T246	0	1	0	0
T247	0	25	0	0
T248	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	813	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	23	0	0
T11	0	11	0	0
T14	10506	24	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	27	0	0
T51	402	0	0	0
T70	0	4	0	0
T246	0	1	0	0
T247	0	25	0	0
T248	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67912	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	1516	0	0
T11	0	2133	0	0
T14	10506	2120	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	1340	0	0
T39	0	508	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	850	0	0
T51	402	0	0	0
T70	0	202	0	0
T246	0	83	0	0
T247	0	2380	0	0
T248	0	3361	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	718	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	18	0	0
T11	0	7	0	0
T14	10506	23	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	11	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	26	0	0
T51	402	0	0	0
T70	0	2	0	0
T75	0	5	0	0
T247	0	19	0	0
T248	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Covered	T29,T77,T94
1	0	Covered	T75,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T14
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T14
DetectSt	168	Covered	T1,T2,T14
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T14
DebounceSt->IdleSt	163	Covered	T14,T3,T4
DetectSt->IdleSt	186	Covered	T29,T75,T77
DetectSt->StableSt	191	Covered	T1,T2,T14
IdleSt->DebounceSt	148	Covered	T1,T2,T14
StableSt->IdleSt	206	Covered	T1,T2,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T14
0	1	Covered	T1,T2,T14
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T14
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T3,T4
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T14
DetectSt	-	-	-	-	1	-	-	Covered	T29,T75,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T14
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T14
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	994	0	0
CntIncr_A	7510225	55218	0	0
CntNoWrap_A	7510225	6823192	0	0
DetectStDropOut_A	7510225	67	0	0
DetectedOut_A	7510225	15144	0	0
DetectedPulseOut_A	7510225	381	0	0
DisabledIdleSt_A	7510225	6409299	0	0
DisabledNoDetection_A	7510225	6410979	0	0
EnterDebounceSt_A	7510225	544	0	0
EnterDetectSt_A	7510225	452	0	0
EnterStableSt_A	7510225	381	0	0
PulseIsPulse_A	7510225	381	0	0
StayInStableSt	7510225	14741	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	994	0	0
T1	19868	4	0	0
T2	8913	2	0	0
T3	42261	17	0	0
T4	2227	1	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	8	0	0
T11	0	6	0	0
T12	0	1	0	0
T13	524	0	0	0
T14	10506	3	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	4	0	0
T40	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	55218	0	0
T1	19868	344	0	0
T2	8913	25	0	0
T3	42261	1353	0	0
T4	2227	20	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	208	0	0
T11	0	207	0	0
T12	0	20	0	0
T13	524	0	0	0
T14	10506	122	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	128	0	0
T40	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823192	0	0
T1	19868	19422	0	0
T2	8913	2733	0	0
T3	42261	39734	0	0
T4	2227	623	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10092	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	67	0	0
T29	14138	4	0	0
T38	654	0	0	0
T39	9451	0	0	0
T77	0	1	0	0
T91	4166	0	0	0
T94	0	2	0	0
T95	0	12	0	0
T98	0	9	0	0
T100	0	8	0	0
T101	0	3	0	0
T102	0	3	0	0
T103	0	3	0	0
T104	0	3	0	0
T107	427	0	0	0
T108	528	0	0	0
T109	725	0	0	0
T110	430	0	0	0
T111	409	0	0	0
T112	30384	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	15144	0	0
T1	19868	22	0	0
T2	8913	3	0	0
T3	42261	113	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	229	0	0
T11	0	1075	0	0
T13	524	0	0	0
T14	10506	62	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	3	0	0
T25	0	109	0	0
T45	0	127	0	0
T48	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	381	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	8	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T13	524	0	0	0
T14	10506	1	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T45	0	4	0	0
T48	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6409299	0	0
T1	19868	14099	0	0
T2	8913	2652	0	0
T3	42261	34711	0	0
T4	2227	586	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	7951	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6410979	0	0
T1	19868	14099	0	0
T2	8913	2669	0	0
T3	42261	34715	0	0
T4	2227	588	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	7952	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	544	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	9	0	0
T4	2227	1	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T12	0	1	0	0
T13	524	0	0	0
T14	10506	2	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	2	0	0
T40	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	452	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	8	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T13	524	0	0	0
T14	10506	1	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T45	0	4	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	381	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	8	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T13	524	0	0	0
T14	10506	1	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T45	0	4	0	0
T48	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	381	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	8	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	4	0	0
T11	0	3	0	0
T13	524	0	0	0
T14	10506	1	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T45	0	4	0	0
T48	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	14741	0	0
T1	19868	20	0	0
T2	8913	2	0	0
T3	42261	105	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	222	0	0
T11	0	1072	0	0
T13	524	0	0	0
T14	10506	60	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	2	0	0
T25	0	107	0	0
T45	0	123	0	0
T48	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	355	0	0
T1	19868	2	0	0
T2	8913	1	0	0
T3	42261	8	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	3	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T45	0	4	0	0
T55	0	2	0	0
T72	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T25,T10
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T25,T10
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T69,T71,T91
1	0	Covered	T247,T75,T189

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
1	0	Covered	T75,T249,T250

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T25,T10
1	-	Covered	T14,T25,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T25,T10
DetectSt	168	Covered	T14,T25,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T14,T25,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T25,T10
DebounceSt->IdleSt	163	Covered	T75,T244,T78
DetectSt->IdleSt	186	Covered	T69,T71,T91
DetectSt->StableSt	191	Covered	T14,T25,T10
IdleSt->DebounceSt	148	Covered	T14,T25,T10
StableSt->IdleSt	206	Covered	T14,T25,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T25,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T14,T25,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T25,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T244,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T69,T71,T91
DetectSt	-	-	-	-	0	1	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	1	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	0	Covered	T14,T25,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	2914	0	0
CntIncr_A	7510225	98203	0	0
CntNoWrap_A	7510225	6821272	0	0
DetectStDropOut_A	7510225	441	0	0
DetectedOut_A	7510225	88524	0	0
DetectedPulseOut_A	7510225	911	0	0
DisabledIdleSt_A	7510225	6380421	0	0
DisabledNoDetection_A	7510225	6382673	0	0
EnterDebounceSt_A	7510225	1462	0	0
EnterDetectSt_A	7510225	1452	0	0
EnterStableSt_A	7510225	911	0	0
PulseIsPulse_A	7510225	911	0	0
StayInStableSt	7510225	87494	0	0
gen_high_event_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	781	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2914	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	6	0	0
T11	0	20	0	0
T14	10506	26	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	16	0	0
T39	0	52	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	14	0	0
T51	402	0	0	0
T68	0	56	0	0
T69	0	70	0	0
T70	0	26	0	0
T71	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	98203	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	135	0	0
T11	0	730	0	0
T14	10506	858	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	416	0	0
T39	0	2132	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	497	0	0
T51	402	0	0	0
T68	0	1372	0	0
T69	0	1466	0	0
T70	0	416	0	0
T71	0	1188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6821272	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10069	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	441	0	0
T29	14138	0	0	0
T39	9451	0	0	0
T57	1841	0	0	0
T69	4723	35	0	0
T70	24730	0	0	0
T71	5315	22	0	0
T75	0	1	0	0
T80	35202	0	0	0
T90	671	0	0	0
T91	0	12	0	0
T92	0	8	0	0
T93	0	10	0	0
T97	0	28	0	0
T99	0	30	0	0
T107	427	0	0	0
T217	0	13	0	0
T245	657	0	0	0
T247	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	88524	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	243	0	0
T11	0	4289	0	0
T14	10506	691	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	139	0	0
T39	0	839	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	273	0	0
T51	402	0	0	0
T68	0	2665	0	0
T70	0	1795	0	0
T75	0	489	0	0
T248	0	3208	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	911	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	3	0	0
T11	0	10	0	0
T14	10506	13	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	28	0	0
T70	0	13	0	0
T75	0	5	0	0
T248	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6380421	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	5300	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6382673	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	5300	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1462	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	3	0	0
T11	0	10	0	0
T14	10506	13	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	28	0	0
T69	0	35	0	0
T70	0	13	0	0
T71	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1452	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	3	0	0
T11	0	10	0	0
T14	10506	13	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	28	0	0
T69	0	35	0	0
T70	0	13	0	0
T71	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	911	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	3	0	0
T11	0	10	0	0
T14	10506	13	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	28	0	0
T70	0	13	0	0
T75	0	5	0	0
T248	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	911	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	3	0	0
T11	0	10	0	0
T14	10506	13	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	28	0	0
T70	0	13	0	0
T75	0	5	0	0
T248	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	87494	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	239	0	0
T11	0	4278	0	0
T14	10506	677	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	131	0	0
T39	0	813	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	266	0	0
T51	402	0	0	0
T68	0	2632	0	0
T70	0	1775	0	0
T75	0	484	0	0
T248	0	3179	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	781	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	2	0	0
T11	0	9	0	0
T14	10506	12	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	8	0	0
T39	0	26	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	7	0	0
T51	402	0	0	0
T68	0	23	0	0
T70	0	6	0	0
T75	0	4	0	0
T248	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T76,T94,T251
1	0	Covered	T75,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T10
1	-	Covered	T1,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T10
DetectSt	168	Covered	T1,T3,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T10
DebounceSt->IdleSt	163	Covered	T47,T72,T75
DetectSt->IdleSt	186	Covered	T76,T75,T94
DetectSt->StableSt	191	Covered	T1,T3,T10
IdleSt->DebounceSt	148	Covered	T1,T3,T10
StableSt->IdleSt	206	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T72,T252
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T76,T75,T94
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	1046	0	0
CntIncr_A	7510225	62709	0	0
CntNoWrap_A	7510225	6823140	0	0
DetectStDropOut_A	7510225	78	0	0
DetectedOut_A	7510225	22042	0	0
DetectedPulseOut_A	7510225	414	0	0
DisabledIdleSt_A	7510225	6383549	0	0
DisabledNoDetection_A	7510225	6385272	0	0
EnterDebounceSt_A	7510225	551	0	0
EnterDetectSt_A	7510225	497	0	0
EnterStableSt_A	7510225	414	0	0
PulseIsPulse_A	7510225	414	0	0
StayInStableSt	7510225	21572	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1046	0	0
T1	19868	16	0	0
T2	8913	0	0	0
T3	42261	10	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	4	0	0
T47	0	13	0	0
T55	0	6	0	0
T68	0	10	0	0
T70	0	14	0	0
T72	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	62709	0	0
T1	19868	1184	0	0
T2	8913	0	0	0
T3	42261	505	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	58	0	0
T11	0	93	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	290	0	0
T47	0	425	0	0
T55	0	618	0	0
T68	0	245	0	0
T70	0	273	0	0
T72	0	1075	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823140	0	0
T1	19868	19410	0	0
T2	8913	2735	0	0
T3	42261	39741	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	78	0	0
T30	28898	0	0	0
T35	8266	0	0	0
T75	7832	0	0	0
T76	8060	3	0	0
T82	0	6	0	0
T92	5216	0	0	0
T94	0	1	0	0
T98	0	5	0	0
T103	0	4	0	0
T128	12911	0	0	0
T223	515	0	0	0
T239	405	0	0	0
T240	490	0	0	0
T251	0	8	0	0
T253	0	2	0	0
T254	0	5	0	0
T255	0	3	0	0
T256	0	5	0	0
T257	444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	22042	0	0
T1	19868	279	0	0
T2	8913	0	0	0
T3	42261	350	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	52	0	0
T11	0	334	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	50	0	0
T47	0	28	0	0
T55	0	103	0	0
T68	0	481	0	0
T70	0	388	0	0
T72	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	414	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	2	0	0
T47	0	5	0	0
T55	0	3	0	0
T68	0	5	0	0
T70	0	7	0	0
T72	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6383549	0	0
T1	19868	14099	0	0
T2	8913	2735	0	0
T3	42261	34711	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	9405	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6385272	0	0
T1	19868	14099	0	0
T2	8913	2753	0	0
T3	42261	34715	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	9406	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	551	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	2	0	0
T47	0	8	0	0
T55	0	3	0	0
T68	0	5	0	0
T70	0	7	0	0
T72	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	497	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	2	0	0
T47	0	5	0	0
T55	0	3	0	0
T68	0	5	0	0
T70	0	7	0	0
T72	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	414	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	2	0	0
T47	0	5	0	0
T55	0	3	0	0
T68	0	5	0	0
T70	0	7	0	0
T72	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	414	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	2	0	0
T47	0	5	0	0
T55	0	3	0	0
T68	0	5	0	0
T70	0	7	0	0
T72	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	21572	0	0
T1	19868	271	0	0
T2	8913	0	0	0
T3	42261	345	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	51	0	0
T11	0	333	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T45	0	48	0	0
T47	0	23	0	0
T55	0	100	0	0
T68	0	476	0	0
T70	0	374	0	0
T72	0	108	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	355	0	0
T1	19868	8	0	0
T2	8913	0	0	0
T3	42261	5	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	2	0	0
T45	0	2	0	0
T47	0	5	0	0
T55	0	3	0	0
T68	0	5	0	0
T72	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T25,T10
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T25,T10
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T68,T69,T70
1	0	Covered	T25,T10,T48

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T11,T39
0	1	Covered	T14,T11,T39
1	0	Covered	T258

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T11,T39
1	-	Covered	T14,T11,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T25,T10
DetectSt	168	Covered	T14,T25,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T14,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T25,T10
DebounceSt->IdleSt	163	Covered	T75,T244,T78
DetectSt->IdleSt	186	Covered	T25,T10,T48
DetectSt->StableSt	191	Covered	T14,T11,T39
IdleSt->DebounceSt	148	Covered	T14,T25,T10
StableSt->IdleSt	206	Covered	T14,T11,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T25,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T14,T25,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T25,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T244,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T25,T10,T48
DetectSt	-	-	-	-	0	1	-	Covered	T14,T11,T39
DetectSt	-	-	-	-	0	0	-	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	1	Covered	T14,T11,T39
StableSt	-	-	-	-	-	-	0	Covered	T14,T11,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	2926	0	0
CntIncr_A	7510225	102980	0	0
CntNoWrap_A	7510225	6821260	0	0
DetectStDropOut_A	7510225	422	0	0
DetectedOut_A	7510225	69980	0	0
DetectedPulseOut_A	7510225	894	0	0
DisabledIdleSt_A	7510225	6395455	0	0
DisabledNoDetection_A	7510225	6397733	0	0
EnterDebounceSt_A	7510225	1471	0	0
EnterDetectSt_A	7510225	1455	0	0
EnterStableSt_A	7510225	894	0	0
PulseIsPulse_A	7510225	894	0	0
StayInStableSt	7510225	68991	0	0
gen_high_event_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	778	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2926	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	18	0	0
T11	0	26	0	0
T14	10506	34	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	6	0	0
T39	0	48	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	24	0	0
T51	402	0	0	0
T68	0	60	0	0
T69	0	54	0	0
T70	0	24	0	0
T71	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	102980	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	419	0	0
T11	0	1235	0	0
T14	10506	1020	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	201	0	0
T39	0	1368	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	1014	0	0
T51	402	0	0	0
T68	0	1849	0	0
T69	0	1138	0	0
T70	0	480	0	0
T71	0	540	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6821260	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10061	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	422	0	0
T36	2107	0	0	0
T55	15302	0	0	0
T56	8393	0	0	0
T63	494	0	0	0
T68	18131	15	0	0
T69	4723	27	0	0
T70	24730	7	0	0
T71	0	10	0	0
T75	0	1	0	0
T91	0	11	0	0
T92	0	14	0	0
T93	0	2	0	0
T96	0	11	0	0
T157	574	0	0	0
T247	0	8	0	0
T259	696	0	0	0
T260	428	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69980	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	3259	0	0
T14	10506	415	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	3738	0	0
T39	0	2478	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	471	0	0
T243	0	1139	0	0
T248	0	478	0	0
T261	0	193	0	0
T262	0	1406	0	0
T263	0	2207	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	894	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	13	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	20	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	5	0	0
T243	0	15	0	0
T248	0	26	0	0
T261	0	12	0	0
T262	0	29	0	0
T263	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6395455	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	5727	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6397733	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	5728	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1471	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	9	0	0
T11	0	13	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	3	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	12	0	0
T51	402	0	0	0
T68	0	30	0	0
T69	0	27	0	0
T70	0	12	0	0
T71	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1455	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	9	0	0
T11	0	13	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	3	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	12	0	0
T51	402	0	0	0
T68	0	30	0	0
T69	0	27	0	0
T70	0	12	0	0
T71	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	894	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	13	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	20	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	5	0	0
T243	0	15	0	0
T248	0	26	0	0
T261	0	12	0	0
T262	0	29	0	0
T263	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	894	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	13	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	20	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	5	0	0
T243	0	15	0	0
T248	0	26	0	0
T261	0	12	0	0
T262	0	29	0	0
T263	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	68991	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	3244	0	0
T14	10506	398	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	3716	0	0
T39	0	2454	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	466	0	0
T243	0	1124	0	0
T248	0	452	0	0
T261	0	181	0	0
T262	0	1371	0	0
T263	0	2179	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	778	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T11	0	11	0	0
T14	10506	17	0	0
T15	490	0	0	0
T16	2025	0	0	0
T31	0	18	0	0
T39	0	24	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T51	402	0	0	0
T75	0	5	0	0
T243	0	15	0	0
T248	0	26	0	0
T261	0	12	0	0
T262	0	23	0	0
T263	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T95,T264,T82
1	0	Covered	T75,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T47,T72,T29
DetectSt->IdleSt	186	Covered	T75,T95,T264
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T72,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T75,T95,T264
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	789	0	0
CntIncr_A	7510225	45114	0	0
CntNoWrap_A	7510225	6823397	0	0
DetectStDropOut_A	7510225	35	0	0
DetectedOut_A	7510225	14308	0	0
DetectedPulseOut_A	7510225	330	0	0
DisabledIdleSt_A	7510225	6400755	0	0
DisabledNoDetection_A	7510225	6402489	0	0
EnterDebounceSt_A	7510225	420	0	0
EnterDetectSt_A	7510225	369	0	0
EnterStableSt_A	7510225	330	0	0
PulseIsPulse_A	7510225	330	0	0
StayInStableSt	7510225	13940	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	789	0	0
T1	19868	4	0	0
T2	8913	0	0	0
T3	42261	28	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	2	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	7	0	0
T32	0	2	0	0
T33	0	7	0	0
T39	0	1	0	0
T47	0	3	0	0
T72	0	1	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	45114	0	0
T1	19868	306	0	0
T2	8913	0	0	0
T3	42261	2058	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	88	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	248	0	0
T32	0	128	0	0
T33	0	578	0	0
T39	0	33	0	0
T47	0	94	0	0
T72	0	97	0	0
T76	0	117	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823397	0	0
T1	19868	19422	0	0
T2	8913	2735	0	0
T3	42261	39723	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	35	0	0
T82	0	2	0	0
T95	26733	1	0	0
T155	0	1	0	0
T174	0	1	0	0
T182	770	0	0	0
T254	0	1	0	0
T255	0	6	0	0
T256	0	1	0	0
T264	28103	2	0	0
T265	0	2	0	0
T266	0	1	0	0
T267	526	0	0	0
T268	406	0	0	0
T269	494	0	0	0
T270	406	0	0	0
T271	523	0	0	0
T272	526	0	0	0
T273	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	14308	0	0
T1	19868	62	0	0
T2	8913	0	0	0
T3	42261	351	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	339	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	171	0	0
T30	0	97	0	0
T32	0	37	0	0
T33	0	122	0	0
T47	0	4	0	0
T75	0	98	0	0
T76	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	330	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T47	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6400755	0	0
T1	19868	14099	0	0
T2	8913	2735	0	0
T3	42261	34711	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	9680	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6402489	0	0
T1	19868	14099	0	0
T2	8913	2753	0	0
T3	42261	34715	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	9682	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	420	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	4	0	0
T32	0	1	0	0
T33	0	4	0	0
T39	0	1	0	0
T47	0	2	0	0
T72	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	369	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T47	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	330	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T47	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	330	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T47	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	13940	0	0
T1	19868	60	0	0
T2	8913	0	0	0
T3	42261	337	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	338	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	168	0	0
T30	0	96	0	0
T32	0	35	0	0
T33	0	119	0	0
T47	0	3	0	0
T75	0	97	0	0
T76	0	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	289	0	0
T1	19868	2	0	0
T2	8913	0	0	0
T3	42261	14	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T11	0	1	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T33	0	3	0	0
T47	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T252	0	2	0	0