Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T25,T10
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T14,T25,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T25,T10
1	0	Covered	T14,T25,T10
1	1	Covered	T14,T25,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T68,T69,T70
1	0	Covered	T68,T70,T247

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T25,T10
1	-	Covered	T14,T25,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T25,T10
DetectSt	168	Covered	T14,T25,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T14,T25,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T25,T10
DebounceSt->IdleSt	163	Covered	T75,T244,T78
DetectSt->IdleSt	186	Covered	T68,T69,T70
DetectSt->StableSt	191	Covered	T14,T25,T10
IdleSt->DebounceSt	148	Covered	T14,T25,T10
StableSt->IdleSt	206	Covered	T14,T25,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T25,T10
0	1	Covered	T14,T25,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T25,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T25,T10
IdleSt	0	-	-	-	-	-	-	Covered	T14,T25,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T25,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T244,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	1	-	-	Covered	T68,T69,T70
DetectSt	-	-	-	-	0	1	-	Covered	T14,T25,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	1	Covered	T14,T25,T10
StableSt	-	-	-	-	-	-	0	Covered	T14,T25,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	2937	0	0
CntIncr_A	7510225	95513	0	0
CntNoWrap_A	7510225	6821249	0	0
DetectStDropOut_A	7510225	510	0	0
DetectedOut_A	7510225	58931	0	0
DetectedPulseOut_A	7510225	662	0	0
DisabledIdleSt_A	7510225	6404183	0	0
DisabledNoDetection_A	7510225	6406478	0	0
EnterDebounceSt_A	7510225	1478	0	0
EnterDetectSt_A	7510225	1460	0	0
EnterStableSt_A	7510225	662	0	0
PulseIsPulse_A	7510225	662	0	0
StayInStableSt	7510225	58194	0	0
gen_high_event_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	585	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	2937	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	28	0	0
T11	0	54	0	0
T14	10506	12	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	28	0	0
T39	0	42	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	62	0	0
T51	402	0	0	0
T68	0	60	0	0
T69	0	32	0	0
T70	0	46	0	0
T71	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	95513	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	532	0	0
T11	0	1701	0	0
T14	10506	390	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	756	0	0
T39	0	1281	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	1829	0	0
T51	402	0	0	0
T68	0	1849	0	0
T69	0	666	0	0
T70	0	933	0	0
T71	0	540	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6821249	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10083	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	510	0	0
T36	2107	0	0	0
T55	15302	0	0	0
T56	8393	0	0	0
T63	494	0	0	0
T68	18131	15	0	0
T69	4723	16	0	0
T70	24730	13	0	0
T71	0	10	0	0
T75	0	1	0	0
T91	0	20	0	0
T92	0	34	0	0
T93	0	7	0	0
T96	0	4	0	0
T157	574	0	0	0
T247	0	7	0	0
T259	696	0	0	0
T260	428	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	58931	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	826	0	0
T11	0	7007	0	0
T14	10506	117	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	219	0	0
T31	0	5637	0	0
T39	0	1149	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	2374	0	0
T51	402	0	0	0
T75	0	453	0	0
T248	0	500	0	0
T261	0	71	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	662	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	14	0	0
T11	0	27	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T31	0	18	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T75	0	5	0	0
T248	0	14	0	0
T261	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6404183	0	0
T1	19868	19426	0	0
T2	8913	2735	0	0
T3	42261	39751	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	5769	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6406478	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	5770	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1478	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	14	0	0
T11	0	27	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T68	0	30	0	0
T69	0	16	0	0
T70	0	23	0	0
T71	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	1460	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	14	0	0
T11	0	27	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T68	0	30	0	0
T69	0	16	0	0
T70	0	23	0	0
T71	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	662	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	14	0	0
T11	0	27	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T31	0	18	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T75	0	5	0	0
T248	0	14	0	0
T261	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	662	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	14	0	0
T11	0	27	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T31	0	18	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T75	0	5	0	0
T248	0	14	0	0
T261	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	58194	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	810	0	0
T11	0	6973	0	0
T14	10506	111	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	205	0	0
T31	0	5617	0	0
T39	0	1128	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	2343	0	0
T51	402	0	0	0
T75	0	448	0	0
T248	0	486	0	0
T261	0	63	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	585	0	0
T3	42261	0	0	0
T4	2227	0	0	0
T7	1122	0	0	0
T8	1394	0	0	0
T10	0	12	0	0
T11	0	20	0	0
T14	10506	6	0	0
T15	490	0	0	0
T16	2025	0	0	0
T25	0	14	0	0
T31	0	16	0	0
T39	0	21	0	0
T40	2013	0	0	0
T41	36849	0	0	0
T48	0	31	0	0
T51	402	0	0	0
T75	0	5	0	0
T248	0	14	0	0
T261	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T29,T76,T254
1	0	Covered	T75,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T10
1	-	Covered	T1,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T10
DetectSt	168	Covered	T1,T3,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T10
DebounceSt->IdleSt	163	Covered	T47,T29,T76
DetectSt->IdleSt	186	Covered	T29,T76,T75
DetectSt->StableSt	191	Covered	T1,T3,T10
IdleSt->DebounceSt	148	Covered	T1,T3,T10
StableSt->IdleSt	206	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T29,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T29,T76,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7510225	818	0	0
CntIncr_A	7510225	48550	0	0
CntNoWrap_A	7510225	6823368	0	0
DetectStDropOut_A	7510225	69	0	0
DetectedOut_A	7510225	13607	0	0
DetectedPulseOut_A	7510225	309	0	0
DisabledIdleSt_A	7510225	6408798	0	0
DisabledNoDetection_A	7510225	6410550	0	0
EnterDebounceSt_A	7510225	436	0	0
EnterDetectSt_A	7510225	383	0	0
EnterStableSt_A	7510225	309	0	0
PulseIsPulse_A	7510225	309	0	0
StayInStableSt	7510225	13272	0	0
gen_high_level_sva.HighLevelEvent_A	7510225	6826645	0	0
gen_not_sticky_sva.StableStDropOut_A	7510225	280	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	818	0	0
T1	19868	6	0	0
T2	8913	0	0	0
T3	42261	22	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	2	0	0
T11	0	10	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	5	0	0
T33	0	4	0	0
T47	0	7	0	0
T55	0	6	0	0
T72	0	8	0	0
T76	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	48550	0	0
T1	19868	276	0	0
T2	8913	0	0	0
T3	42261	1628	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	42	0	0
T11	0	330	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	298	0	0
T33	0	228	0	0
T47	0	236	0	0
T55	0	504	0	0
T72	0	428	0	0
T76	0	226	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6823368	0	0
T1	19868	19420	0	0
T2	8913	2735	0	0
T3	42261	39729	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	10095	0	0
T15	490	89	0	0
T16	2025	422	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	69	0	0
T29	14138	2	0	0
T38	654	0	0	0
T39	9451	0	0	0
T76	0	1	0	0
T91	4166	0	0	0
T107	427	0	0	0
T108	528	0	0	0
T109	725	0	0	0
T110	430	0	0	0
T111	409	0	0	0
T112	30384	0	0	0
T174	0	5	0	0
T198	0	1	0	0
T254	0	10	0	0
T274	0	5	0	0
T275	0	5	0	0
T276	0	5	0	0
T277	0	8	0	0
T278	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	13607	0	0
T1	19868	271	0	0
T2	8913	0	0	0
T3	42261	260	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	68	0	0
T11	0	1803	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	282	0	0
T33	0	175	0	0
T47	0	18	0	0
T55	0	217	0	0
T72	0	300	0	0
T75	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	309	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	6	0	0
T33	0	2	0	0
T47	0	3	0	0
T55	0	3	0	0
T72	0	4	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6408798	0	0
T1	19868	14099	0	0
T2	8913	2735	0	0
T3	42261	34711	0	0
T4	2227	624	0	0
T5	682	281	0	0
T6	426	25	0	0
T13	524	123	0	0
T14	10506	9978	0	0
T15	490	89	0	0
T16	2025	422	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6410550	0	0
T1	19868	14099	0	0
T2	8913	2753	0	0
T3	42261	34715	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	9980	0	0
T15	490	90	0	0
T16	2025	425	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	436	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	3	0	0
T33	0	2	0	0
T47	0	4	0	0
T55	0	3	0	0
T72	0	4	0	0
T76	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	383	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T47	0	3	0	0
T55	0	3	0	0
T72	0	4	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	309	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	6	0	0
T33	0	2	0	0
T47	0	3	0	0
T55	0	3	0	0
T72	0	4	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	309	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	6	0	0
T33	0	2	0	0
T47	0	3	0	0
T55	0	3	0	0
T72	0	4	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	13272	0	0
T1	19868	268	0	0
T2	8913	0	0	0
T3	42261	249	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	67	0	0
T11	0	1798	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	276	0	0
T33	0	173	0	0
T47	0	15	0	0
T55	0	214	0	0
T72	0	296	0	0
T75	0	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	6826645	0	0
T1	19868	19433	0	0
T2	8913	2753	0	0
T3	42261	39772	0	0
T4	2227	627	0	0
T5	682	282	0	0
T6	426	26	0	0
T13	524	124	0	0
T14	10506	10097	0	0
T15	490	90	0	0
T16	2025	425	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7510225	280	0	0
T1	19868	3	0	0
T2	8913	0	0	0
T3	42261	11	0	0
T4	2227	0	0	0
T5	682	0	0	0
T6	426	0	0	0
T10	0	1	0	0
T11	0	5	0	0
T13	524	0	0	0
T14	10506	0	0	0
T15	490	0	0	0
T16	2025	0	0	0
T30	0	6	0	0
T31	0	1	0	0
T33	0	2	0	0
T47	0	3	0	0
T55	0	3	0	0
T72	0	4	0	0