Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1492797775	9714	0	0
auto_block_debounce_ctl_rd_A	1492797775	2118	0	0
auto_block_out_ctl_rd_A	1492797775	2764	0	0
com_det_ctl_0_rd_A	1492797775	3727	0	0
com_det_ctl_1_rd_A	1492797775	3729	0	0
com_det_ctl_2_rd_A	1492797775	3594	0	0
com_det_ctl_3_rd_A	1492797775	3893	0	0
com_out_ctl_0_rd_A	1492797775	4122	0	0
com_out_ctl_1_rd_A	1492797775	4226	0	0
com_out_ctl_2_rd_A	1492797775	4047	0	0
com_out_ctl_3_rd_A	1492797775	4292	0	0
com_pre_det_ctl_0_rd_A	1492797775	1475	0	0
com_pre_det_ctl_1_rd_A	1492797775	1412	0	0
com_pre_det_ctl_2_rd_A	1492797775	1562	0	0
com_pre_det_ctl_3_rd_A	1492797775	1528	0	0
com_pre_sel_ctl_0_rd_A	1492797775	4488	0	0
com_pre_sel_ctl_1_rd_A	1492797775	4353	0	0
com_pre_sel_ctl_2_rd_A	1492797775	4486	0	0
com_pre_sel_ctl_3_rd_A	1492797775	4282	0	0
com_sel_ctl_0_rd_A	1492797775	4335	0	0
com_sel_ctl_1_rd_A	1492797775	4450	0	0
com_sel_ctl_2_rd_A	1492797775	4546	0	0
com_sel_ctl_3_rd_A	1492797775	4392	0	0
ec_rst_ctl_rd_A	1492797775	2428	0	0
intr_enable_rd_A	1492797775	2047	0	0
key_intr_ctl_rd_A	1492797775	3832	0	0
key_intr_debounce_ctl_rd_A	1492797775	1640	0	0
key_invert_ctl_rd_A	1492797775	5457	0	0
pin_allowed_ctl_rd_A	1492797775	5690	0	0
pin_out_ctl_rd_A	1492797775	4266	0	0
pin_out_value_rd_A	1492797775	4466	0	0
regwen_rd_A	1492797775	1767	0	0
ulp_ac_debounce_ctl_rd_A	1492797775	1625	0	0
ulp_ctl_rd_A	1492797775	1773	0	0
ulp_lid_debounce_ctl_rd_A	1492797775	1658	0	0
ulp_pwrb_debounce_ctl_rd_A	1492797775	1802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	9714	0	0
T2	114749	22	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T12	0	4	0	0
T13	131065	0	0	0
T14	520069	0	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T24	0	11	0	0
T32	0	20	0	0
T33	0	14	0	0
T35	0	13	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T46	0	3	0	0
T51	201160	0	0	0
T55	0	6	0	0
T56	0	2	0	0
T128	0	13	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2118	0	0
T3	202850	0	0	0
T4	993344	12	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	12	0	0
T33	0	8	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T44	0	16	0	0
T49	0	15	0	0
T51	201160	0	0	0
T52	111540	0	0	0
T55	0	12	0	0
T56	0	3	0	0
T112	0	9	0	0
T128	0	22	0	0
T245	0	18	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2764	0	0
T3	202850	0	0	0
T4	993344	4	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T9	227162	0	0	0
T16	253162	8	0	0
T33	0	13	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T44	0	15	0	0
T49	0	12	0	0
T51	201160	0	0	0
T52	111540	0	0	0
T55	0	27	0	0
T56	0	6	0	0
T112	0	9	0	0
T128	0	25	0	0
T245	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3727	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	88	0	0
T14	520069	18	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	20	0	0
T30	0	43	0	0
T33	0	58	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	72	0	0
T51	201160	0	0	0
T55	0	40	0	0
T56	0	1	0	0
T128	0	7	0	0
T153	0	6	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3729	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	83	0	0
T14	520069	56	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	39	0	0
T30	0	25	0	0
T33	0	45	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	62	0	0
T51	201160	0	0	0
T55	0	54	0	0
T56	0	1	0	0
T128	0	24	0	0
T153	0	2	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3594	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	86	0	0
T14	520069	42	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	13	0	0
T30	0	37	0	0
T33	0	65	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	48	0	0
T51	201160	0	0	0
T55	0	30	0	0
T56	0	3	0	0
T77	0	88	0	0
T128	0	18	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3893	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	84	0	0
T14	520069	57	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	31	0	0
T30	0	38	0	0
T33	0	55	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	63	0	0
T51	201160	0	0	0
T55	0	33	0	0
T56	0	10	0	0
T128	0	21	0	0
T153	0	13	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4122	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	83	0	0
T14	520069	49	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	29	0	0
T30	0	24	0	0
T33	0	55	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	70	0	0
T51	201160	0	0	0
T55	0	43	0	0
T56	0	8	0	0
T128	0	10	0	0
T153	0	4	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4226	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	76	0	0
T14	520069	69	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	17	0	0
T30	0	40	0	0
T33	0	43	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	61	0	0
T51	201160	0	0	0
T55	0	45	0	0
T77	0	86	0	0
T128	0	12	0	0
T153	0	5	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4047	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	71	0	0
T14	520069	45	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	13	0	0
T30	0	57	0	0
T33	0	54	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	90	0	0
T51	201160	0	0	0
T55	0	43	0	0
T56	0	8	0	0
T128	0	17	0	0
T153	0	3	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4292	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	84	0	0
T14	520069	39	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	8	0	0
T30	0	55	0	0
T33	0	43	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	62	0	0
T51	201160	0	0	0
T55	0	33	0	0
T56	0	9	0	0
T77	0	86	0	0
T128	0	13	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1475	0	0
T33	0	16	0	0
T55	361431	14	0	0
T56	926727	13	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T128	0	16	0	0
T139	0	37	0	0
T153	0	3	0	0
T157	71803	0	0	0
T169	0	23	0	0
T219	0	8	0	0
T245	157695	0	0	0
T254	0	15	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	14	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1412	0	0
T33	0	4	0	0
T55	361431	36	0	0
T56	926727	6	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T128	0	9	0	0
T139	0	33	0	0
T153	0	7	0	0
T157	71803	0	0	0
T169	0	37	0	0
T219	0	17	0	0
T245	157695	0	0	0
T254	0	24	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	6	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1562	0	0
T33	0	11	0	0
T55	361431	25	0	0
T56	926727	0	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T102	0	31	0	0
T128	0	7	0	0
T139	0	38	0	0
T157	71803	0	0	0
T169	0	34	0	0
T219	0	10	0	0
T245	157695	0	0	0
T254	0	8	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	20	0	0
T304	0	9	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1528	0	0
T33	0	10	0	0
T55	361431	16	0	0
T56	926727	6	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T128	0	8	0	0
T139	0	42	0	0
T153	0	11	0	0
T157	71803	0	0	0
T169	0	34	0	0
T219	0	13	0	0
T245	157695	0	0	0
T254	0	33	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	17	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4488	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	74	0	0
T14	520069	53	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	12	0	0
T30	0	49	0	0
T33	0	68	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	79	0	0
T51	201160	0	0	0
T55	0	31	0	0
T56	0	1	0	0
T128	0	27	0	0
T153	0	6	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4353	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	77	0	0
T14	520069	42	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	21	0	0
T30	0	39	0	0
T33	0	32	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	71	0	0
T51	201160	0	0	0
T55	0	37	0	0
T56	0	7	0	0
T128	0	17	0	0
T153	0	2	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4486	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	80	0	0
T14	520069	55	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	4	0	0
T30	0	27	0	0
T33	0	68	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	86	0	0
T51	201160	0	0	0
T55	0	52	0	0
T56	0	4	0	0
T128	0	15	0	0
T153	0	7	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4282	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	88	0	0
T14	520069	37	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	45	0	0
T30	0	53	0	0
T33	0	62	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	63	0	0
T51	201160	0	0	0
T55	0	39	0	0
T56	0	6	0	0
T128	0	24	0	0
T153	0	8	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4335	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	115	0	0
T14	520069	57	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	2	0	0
T30	0	34	0	0
T33	0	69	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	52	0	0
T51	201160	0	0	0
T55	0	42	0	0
T56	0	7	0	0
T128	0	13	0	0
T153	0	1	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4450	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	75	0	0
T14	520069	57	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	33	0	0
T30	0	44	0	0
T33	0	58	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	61	0	0
T51	201160	0	0	0
T55	0	34	0	0
T77	0	75	0	0
T128	0	4	0	0
T153	0	7	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4546	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	97	0	0
T14	520069	53	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	29	0	0
T30	0	48	0	0
T33	0	52	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	78	0	0
T51	201160	0	0	0
T55	0	38	0	0
T56	0	4	0	0
T128	0	14	0	0
T153	0	4	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4392	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	70	0	0
T14	520069	58	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T25	0	22	0	0
T30	0	50	0	0
T33	0	44	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	77	0	0
T51	201160	0	0	0
T55	0	39	0	0
T56	0	4	0	0
T77	0	75	0	0
T128	0	14	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2428	0	0
T3	202850	0	0	0
T4	993344	0	0	0
T7	291603	0	0	0
T8	61559	0	0	0
T11	0	23	0	0
T14	520069	5	0	0
T15	117671	0	0	0
T16	253162	0	0	0
T33	0	51	0	0
T40	100660	0	0	0
T41	184246	0	0	0
T45	0	19	0	0
T51	201160	0	0	0
T55	0	33	0	0
T56	0	15	0	0
T75	0	5	0	0
T91	0	2	0	0
T109	0	8	0	0
T128	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	2047	0	0
T33	0	19	0	0
T55	361431	9	0	0
T56	926727	0	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T101	0	25	0	0
T128	0	14	0	0
T139	0	66	0	0
T153	0	12	0	0
T157	71803	0	0	0
T169	0	27	0	0
T219	0	33	0	0
T245	157695	0	0	0
T254	0	20	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T305	0	5	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	3832	0	0
T9	227162	4	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T12	397136	0	0	0
T25	359318	0	0	0
T33	0	39	0	0
T38	0	3	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T55	0	25	0	0
T56	0	2	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T75	0	85	0	0
T80	0	3	0	0
T128	0	25	0	0
T153	0	6	0	0
T158	0	3	0	0
T178	54628	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1640	0	0
T33	0	10	0	0
T55	361431	15	0	0
T56	926727	5	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T128	0	10	0	0
T139	0	38	0	0
T157	71803	0	0	0
T169	0	22	0	0
T219	0	6	0	0
T245	157695	0	0	0
T254	0	14	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	12	0	0
T304	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	5457	0	0
T22	103220	0	0	0
T23	904480	64	0	0
T30	0	49	0	0
T33	0	89	0	0
T34	351891	0	0	0
T44	321985	0	0	0
T55	0	67	0	0
T56	0	162	0	0
T60	693149	26	0	0
T61	245484	0	0	0
T64	13778	0	0	0
T65	62968	0	0	0
T66	256274	0	0	0
T125	195900	0	0	0
T128	0	93	0	0
T153	0	8	0	0
T213	0	33	0	0
T219	0	15	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	5690	0	0
T33	0	20	0	0
T37	108220	0	0	0
T46	171441	0	0	0
T47	131677	0	0	0
T53	60674	0	0	0
T55	0	12	0	0
T56	0	5	0	0
T62	13010	0	0	0
T128	0	97	0	0
T134	206399	0	0	0
T135	351220	0	0	0
T136	211149	0	0	0
T148	0	65	0	0
T153	0	8	0	0
T195	28149	79	0	0
T196	53038	0	0	0
T306	0	77	0	0
T307	0	29	0	0
T308	0	71	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4266	0	0
T33	0	18	0	0
T37	108220	0	0	0
T46	171441	0	0	0
T47	131677	0	0	0
T53	60674	0	0	0
T55	0	13	0	0
T56	0	2	0	0
T62	13010	0	0	0
T128	0	129	0	0
T134	206399	0	0	0
T135	351220	0	0	0
T136	211149	0	0	0
T148	0	55	0	0
T195	28149	62	0	0
T196	53038	0	0	0
T219	0	64	0	0
T306	0	66	0	0
T307	0	53	0	0
T308	0	60	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	4466	0	0
T33	0	18	0	0
T37	108220	0	0	0
T46	171441	0	0	0
T47	131677	0	0	0
T53	60674	0	0	0
T55	0	22	0	0
T56	0	5	0	0
T62	13010	0	0	0
T128	0	123	0	0
T134	206399	0	0	0
T135	351220	0	0	0
T136	211149	0	0	0
T148	0	76	0	0
T153	0	5	0	0
T195	28149	79	0	0
T196	53038	0	0	0
T306	0	67	0	0
T307	0	54	0	0
T308	0	80	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1767	0	0
T33	0	32	0	0
T55	361431	18	0	0
T56	926727	0	0	0
T69	495923	0	0	0
T70	121183	0	0	0
T71	263144	0	0	0
T90	322173	0	0	0
T128	0	16	0	0
T139	0	34	0	0
T153	0	2	0	0
T157	71803	0	0	0
T169	0	38	0	0
T219	0	7	0	0
T245	157695	0	0	0
T254	0	19	0	0
T259	45325	0	0	0
T260	214250	0	0	0
T265	0	25	0	0
T304	0	15	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1625	0	0
T8	61559	4	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T22	0	5	0	0
T23	0	2	0	0
T25	359318	0	0	0
T33	0	8	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T52	111540	0	0	0
T55	0	21	0	0
T56	0	6	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T84	0	2	0	0
T128	0	19	0	0
T151	0	6	0	0
T153	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1773	0	0
T8	61559	5	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T23	0	7	0	0
T25	359318	0	0	0
T30	0	4	0	0
T33	0	25	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T52	111540	0	0	0
T55	0	29	0	0
T56	0	12	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T74	0	7	0	0
T128	0	7	0	0
T151	0	10	0	0
T237	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1658	0	0
T8	61559	4	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T22	0	1	0	0
T23	0	6	0	0
T25	359318	0	0	0
T33	0	20	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T52	111540	0	0	0
T55	0	35	0	0
T56	0	9	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T74	0	6	0	0
T84	0	3	0	0
T128	0	14	0	0
T151	0	19	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1492797775	1802	0	0
T8	61559	2	0	0
T9	227162	0	0	0
T10	808247	0	0	0
T11	145405	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T25	359318	0	0	0
T30	0	8	0	0
T33	0	30	0	0
T42	93497	0	0	0
T43	770762	0	0	0
T52	111540	0	0	0
T55	0	19	0	0
T56	0	10	0	0
T58	88844	0	0	0
T59	19697	0	0	0
T74	0	5	0	0
T128	0	33	0	0
T237	0	3	0	0