Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T9,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T33,T9,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T9,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T9,T50
1	0	Covered	T6,T1,T2
1	1	Covered	T33,T9,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T9,T50
0	1	Covered	T68,T116
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T9,T50
0	1	Covered	T33,T9,T50
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T9,T50
1	-	Covered	T33,T9,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T9,T50
DetectSt	168	Covered	T33,T9,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T33,T9,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T9,T50
DebounceSt->IdleSt	163	Covered	T33,T50,T55
DetectSt->IdleSt	186	Covered	T68,T61,T116
DetectSt->StableSt	191	Covered	T33,T9,T50
IdleSt->DebounceSt	148	Covered	T33,T9,T50
StableSt->IdleSt	206	Covered	T33,T9,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T9,T50
0	1	Covered	T33,T9,T50
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T9,T50
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T9,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T9,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T50,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T9,T50
DetectSt	-	-	-	-	1	-	-	Covered	T68,T61,T116
DetectSt	-	-	-	-	0	1	-	Covered	T33,T9,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T9,T50
StableSt	-	-	-	-	-	-	0	Covered	T33,T9,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	248	0	0
CntIncr_A	6669080	135315	0	0
CntNoWrap_A	6669080	6021090	0	0
DetectStDropOut_A	6669080	2	0	0
DetectedOut_A	6669080	749	0	0
DetectedPulseOut_A	6669080	112	0	0
DisabledIdleSt_A	6669080	5880379	0	0
DisabledNoDetection_A	6669080	5882724	0	0
EnterDebounceSt_A	6669080	137	0	0
EnterDetectSt_A	6669080	115	0	0
EnterStableSt_A	6669080	112	0	0
PulseIsPulse_A	6669080	112	0	0
StayInStableSt	6669080	637	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6746	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	111	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	248	0	0
T8	558	0	0	0
T9	2326	4	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	3	0	0
T42	0	4	0	0
T50	0	3	0	0
T51	0	4	0	0
T52	0	2	0	0
T55	0	5	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T68	0	2	0	0
T99	0	4	0	0
T100	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	135315	0	0
T8	558	0	0	0
T9	2326	163	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	154	0	0
T42	0	120	0	0
T50	0	123	0	0
T51	0	56	0	0
T52	0	12	0	0
T55	0	1918	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T68	0	29	0	0
T99	0	222	0	0
T100	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021090	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2	0	0
T68	8370	1	0	0
T71	29489	0	0	0
T72	495	0	0	0
T83	1374	0	0	0
T99	729	0	0	0
T116	0	1	0	0
T117	506	0	0	0
T118	818	0	0	0
T119	422	0	0	0
T120	906	0	0	0
T121	530	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	749	0	0
T8	558	0	0	0
T9	2326	7	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	6	0	0
T42	0	9	0	0
T50	0	12	0	0
T51	0	11	0	0
T52	0	4	0	0
T55	0	6	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	8	0	0
T100	0	21	0	0
T122	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	112	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	1	0	0
T42	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T122	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5880379	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5882724	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	137	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	2	0	0
T42	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	3	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T68	0	1	0	0
T99	0	3	0	0
T100	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	115	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	1	0	0
T42	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T68	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	112	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	1	0	0
T42	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T122	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	112	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	1	0	0
T42	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T122	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	637	0	0
T8	558	0	0	0
T9	2326	5	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	5	0	0
T42	0	7	0	0
T50	0	11	0	0
T51	0	9	0	0
T52	0	3	0	0
T55	0	4	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	7	0	0
T100	0	19	0	0
T122	0	32	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6746	0	0
T1	11087	31	0	0
T2	29615	11	0	0
T3	687	2	0	0
T6	606	3	0	0
T7	21017	10	0	0
T14	433	4	0	0
T15	8200	29	0	0
T16	12100	15	0	0
T17	496	11	0	0
T18	540	0	0	0
T30	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	111	0	0
T8	558	0	0	0
T9	2326	2	0	0
T10	1473	0	0	0
T26	123078	0	0	0
T32	522	0	0	0
T33	757	1	0	0
T42	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T55	0	2	0	0
T56	522	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T63	822	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T122	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T26
1	0	Covered	T6,T1,T2
1	1	Covered	T3,T10,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Covered	T10,T86,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Unreachable
1	0	Covered	T3,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T26
DetectSt	168	Covered	T3,T10,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T36
DebounceSt->IdleSt	163	Covered	T26,T84,T86
DetectSt->IdleSt	186	Covered	T10,T86,T96
DetectSt->StableSt	191	Covered	T3,T10,T36
IdleSt->DebounceSt	148	Covered	T3,T10,T26
StableSt->IdleSt	206	Covered	T3,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T26
0	1	Covered	T3,T10,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T84,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T26
DetectSt	-	-	-	-	1	-	-	Covered	T10,T86,T96
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	191	0	0
CntIncr_A	6669080	125629	0	0
CntNoWrap_A	6669080	6021147	0	0
DetectStDropOut_A	6669080	20	0	0
DetectedOut_A	6669080	502341	0	0
DetectedPulseOut_A	6669080	56	0	0
DisabledIdleSt_A	6669080	4811906	0	0
DisabledNoDetection_A	6669080	4814293	0	0
EnterDebounceSt_A	6669080	115	0	0
EnterDetectSt_A	6669080	76	0	0
EnterStableSt_A	6669080	56	0	0
PulseIsPulse_A	6669080	56	0	0
StayInStableSt	6669080	502285	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	6746	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_sticky_sva.StableStDropOut_A	6669080	378073	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	191	0	0
T3	687	2	0	0
T7	21017	0	0	0
T10	0	8	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	2	0	0
T62	870	0	0	0
T66	0	2	0	0
T67	0	4	0	0
T83	0	4	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	125629	0	0
T3	687	93	0	0
T7	21017	0	0	0
T10	0	296	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	43	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	91	0	0
T62	870	0	0	0
T66	0	63	0	0
T67	0	110	0	0
T83	0	90	0	0
T84	0	19	0	0
T85	0	29	0	0
T86	0	216	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021147	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	284	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	20	0	0
T10	1473	3	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	777	0	0	0
T26	123078	0	0	0
T50	706	0	0	0
T57	522	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T80	443	0	0	0
T86	0	1	0	0
T96	0	1	0	0
T125	0	3	0	0
T126	0	3	0	0
T127	0	3	0	0
T128	0	1	0	0
T129	0	3	0	0
T130	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	502341	0	0
T3	687	102	0	0
T7	21017	0	0	0
T10	0	1	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	48	0	0
T62	870	0	0	0
T66	0	58	0	0
T67	0	448	0	0
T83	0	283	0	0
T85	0	198	0	0
T93	0	16	0	0
T97	0	224596	0	0
T123	0	198891	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	56	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	1	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T85	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4811906	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	31	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4814293	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	32	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	115	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	76	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	56	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	1	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T85	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	56	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	1	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T85	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	502285	0	0
T3	687	101	0	0
T7	21017	0	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	47	0	0
T62	870	0	0	0
T66	0	57	0	0
T67	0	446	0	0
T83	0	281	0	0
T85	0	197	0	0
T93	0	15	0	0
T97	0	224595	0	0
T123	0	198890	0	0
T124	0	25038	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6746	0	0
T1	11087	31	0	0
T2	29615	11	0	0
T3	687	2	0	0
T6	606	3	0	0
T7	21017	10	0	0
T14	433	4	0	0
T15	8200	29	0	0
T16	12100	15	0	0
T17	496	11	0	0
T18	540	0	0	0
T30	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	378073	0	0
T3	687	46	0	0
T7	21017	0	0	0
T10	0	33	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	24	0	0
T62	870	0	0	0
T66	0	26	0	0
T67	0	305	0	0
T83	0	390	0	0
T85	0	253	0	0
T93	0	27	0	0
T97	0	327	0	0
T123	0	145	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T14,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T14,T3
1	1	Covered	T4,T14,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T26
1	0	Covered	T4,T14,T17
1	1	Covered	T3,T10,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Covered	T93,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Unreachable
1	0	Covered	T3,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T26
DetectSt	168	Covered	T3,T10,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T36
DebounceSt->IdleSt	163	Covered	T26,T66,T123
DetectSt->IdleSt	186	Covered	T93,T94,T95
DetectSt->StableSt	191	Covered	T3,T10,T36
IdleSt->DebounceSt	148	Covered	T3,T10,T26
StableSt->IdleSt	206	Covered	T3,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T26
0	1	Covered	T3,T10,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T14,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T66,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T26
DetectSt	-	-	-	-	1	-	-	Covered	T93,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	176	0	0
CntIncr_A	6669080	70552	0	0
CntNoWrap_A	6669080	6021162	0	0
DetectStDropOut_A	6669080	10	0	0
DetectedOut_A	6669080	431186	0	0
DetectedPulseOut_A	6669080	60	0	0
DisabledIdleSt_A	6669080	4811906	0	0
DisabledNoDetection_A	6669080	4814293	0	0
EnterDebounceSt_A	6669080	106	0	0
EnterDetectSt_A	6669080	70	0	0
EnterStableSt_A	6669080	60	0	0
PulseIsPulse_A	6669080	60	0	0
StayInStableSt	6669080	431126	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_sticky_sva.StableStDropOut_A	6669080	420692	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	176	0	0
T3	687	2	0	0
T7	21017	0	0	0
T10	0	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	2	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	4	0	0
T83	0	4	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	70552	0	0
T3	687	81	0	0
T7	21017	0	0	0
T10	0	88	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	60	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	77	0	0
T62	870	0	0	0
T66	0	61	0	0
T67	0	48	0	0
T83	0	136	0	0
T84	0	100	0	0
T85	0	70	0	0
T86	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021162	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	284	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	10	0	0
T93	23554	1	0	0
T94	0	3	0	0
T95	0	1	0	0
T126	0	2	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	566	0	0	0
T134	952	0	0	0
T135	20062	0	0	0
T136	427	0	0	0
T137	522	0	0	0
T138	402	0	0	0
T139	735	0	0	0
T140	494	0	0	0
T141	13523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	431186	0	0
T3	687	95	0	0
T7	21017	0	0	0
T10	0	190	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	27	0	0
T62	870	0	0	0
T67	0	196	0	0
T83	0	491	0	0
T84	0	83	0	0
T85	0	302	0	0
T86	0	352	0	0
T97	0	413	0	0
T124	0	248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	60	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4811906	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	31	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4814293	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	32	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	106	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	70	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T97	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	60	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	60	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	431126	0	0
T3	687	94	0	0
T7	21017	0	0	0
T10	0	188	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	26	0	0
T62	870	0	0	0
T67	0	194	0	0
T83	0	489	0	0
T84	0	82	0	0
T85	0	301	0	0
T86	0	351	0	0
T97	0	412	0	0
T124	0	247	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	420692	0	0
T3	687	61	0	0
T7	21017	0	0	0
T10	0	162	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	61	0	0
T62	870	0	0	0
T67	0	620	0	0
T83	0	121	0	0
T84	0	39882	0	0
T85	0	112	0	0
T86	0	67	0	0
T97	0	267789	0	0
T124	0	42336	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T26
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T10,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Covered	T26,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T36
0	1	Unreachable
1	0	Covered	T3,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T26
DetectSt	168	Covered	T3,T10,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T26
DebounceSt->IdleSt	163	Covered	T67,T84,T97
DetectSt->IdleSt	186	Covered	T26,T91,T92
DetectSt->StableSt	191	Covered	T3,T10,T36
IdleSt->DebounceSt	148	Covered	T3,T10,T26
StableSt->IdleSt	206	Covered	T3,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T26
0	1	Covered	T3,T10,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T84,T97
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	194	0	0
CntIncr_A	6669080	89675	0	0
CntNoWrap_A	6669080	6021144	0	0
DetectStDropOut_A	6669080	17	0	0
DetectedOut_A	6669080	7735	0	0
DetectedPulseOut_A	6669080	47	0	0
DisabledIdleSt_A	6669080	4811906	0	0
DisabledNoDetection_A	6669080	4814293	0	0
EnterDebounceSt_A	6669080	130	0	0
EnterDetectSt_A	6669080	64	0	0
EnterStableSt_A	6669080	47	0	0
PulseIsPulse_A	6669080	47	0	0
StayInStableSt	6669080	7688	0	0
gen_high_event_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_sticky_sva.StableStDropOut_A	6669080	777739	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	194	0	0
T3	687	2	0	0
T7	21017	0	0	0
T10	0	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	2	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	2	0	0
T62	870	0	0	0
T66	0	2	0	0
T67	0	7	0	0
T83	0	4	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	89675	0	0
T3	687	35	0	0
T7	21017	0	0	0
T10	0	196	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	40864	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	68	0	0
T62	870	0	0	0
T66	0	34	0	0
T67	0	210	0	0
T83	0	22	0	0
T84	0	40053	0	0
T85	0	68	0	0
T86	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021144	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	284	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	17	0	0
T11	28792	0	0	0
T12	17611	0	0	0
T13	777	0	0	0
T26	123078	1	0	0
T45	503	0	0	0
T50	706	0	0	0
T58	425	0	0	0
T59	1701	0	0	0
T75	528	0	0	0
T80	443	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T127	0	1	0	0
T131	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	7735	0	0
T3	687	92	0	0
T7	21017	0	0	0
T10	0	207	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	50	0	0
T62	870	0	0	0
T66	0	16	0	0
T83	0	63	0	0
T85	0	276	0	0
T86	0	204	0	0
T93	0	34	0	0
T123	0	393	0	0
T124	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4811906	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	31	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	4814293	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	32	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	130	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T67	0	7	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	64	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T26	0	1	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	47	0	0
T3	687	1	0	0
T7	21017	0	0	0
T10	0	2	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	1	0	0
T62	870	0	0	0
T66	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	7688	0	0
T3	687	91	0	0
T7	21017	0	0	0
T10	0	205	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	49	0	0
T62	870	0	0	0
T66	0	15	0	0
T83	0	61	0	0
T85	0	275	0	0
T86	0	203	0	0
T93	0	33	0	0
T123	0	392	0	0
T124	0	29	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	777739	0	0
T3	687	122	0	0
T7	21017	0	0	0
T10	0	58	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	0	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	0	0	0
T31	501	0	0	0
T36	0	49	0	0
T62	870	0	0	0
T66	0	117	0	0
T83	0	699	0	0
T85	0	155	0	0
T86	0	247	0	0
T93	0	31	0	0
T123	0	237624	0	0
T124	0	42646	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T45,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T45,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T45,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T45,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T45,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T45,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T45,T44
0	1	Covered	T44,T42,T48
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T45,T44
1	-	Covered	T44,T42,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T45,T44
DetectSt	168	Covered	T13,T45,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T45,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T45,T44
DebounceSt->IdleSt	163	Covered	T147,T148
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T45,T44
IdleSt->DebounceSt	148	Covered	T13,T45,T44
StableSt->IdleSt	206	Covered	T44,T42,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T45,T44
0	1	Covered	T13,T45,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T45,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T45,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T45,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T45,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T45,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T42,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T45,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	89	0	0
CntIncr_A	6669080	15051	0	0
CntNoWrap_A	6669080	6021249	0	0
DetectStDropOut_A	6669080	0	0	0
DetectedOut_A	6669080	6063	0	0
DetectedPulseOut_A	6669080	43	0	0
DisabledIdleSt_A	6669080	5929097	0	0
DisabledNoDetection_A	6669080	5931426	0	0
EnterDebounceSt_A	6669080	46	0	0
EnterDetectSt_A	6669080	43	0	0
EnterStableSt_A	6669080	43	0	0
PulseIsPulse_A	6669080	43	0	0
StayInStableSt	6669080	5999	0	0
gen_high_level_sva.HighLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	89	0	0
T13	777	2	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	2	0	0
T44	0	4	0	0
T45	503	2	0	0
T46	0	4	0	0
T48	0	2	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	6	0	0
T100	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	15051	0	0
T13	777	35	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	37	0	0
T44	0	122	0	0
T45	503	23	0	0
T46	0	136	0	0
T48	0	48	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	63	0	0
T100	0	82	0	0
T149	0	39	0	0
T150	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021249	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6063	0	0
T13	777	155	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	78	0	0
T44	0	168	0	0
T45	503	40	0	0
T46	0	49	0	0
T48	0	7	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	141	0	0
T100	0	73	0	0
T149	0	111	0	0
T150	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	43	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	503	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	3	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5929097	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5931426	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	46	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	503	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	3	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	43	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	503	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	3	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	43	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	503	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	3	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	43	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	503	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	3	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5999	0	0
T13	777	153	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T42	0	77	0	0
T44	0	165	0	0
T45	503	38	0	0
T46	0	46	0	0
T48	0	6	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	136	0	0
T100	0	72	0	0
T149	0	110	0	0
T150	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	20	0	0
T37	19642	0	0	0
T41	8850	0	0	0
T42	0	1	0	0
T44	1037	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T54	8521	0	0	0
T55	2417	0	0	0
T66	610	0	0	0
T67	1707	0	0	0
T69	495	0	0	0
T85	0	1	0	0
T100	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	421	0	0	0
T154	978	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T43,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T43,T41
1	0	Covered	T1,T2,T14
1	1	Covered	T13,T43,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T41
0	1	Covered	T124,T151,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T41
0	1	Covered	T13,T43,T41
1	0	Covered	T60,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T43,T41
1	-	Covered	T13,T43,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T43,T41
DetectSt	168	Covered	T13,T43,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T43,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T43,T41
DebounceSt->IdleSt	163	Covered	T93,T155,T156
DetectSt->IdleSt	186	Covered	T124,T151,T96
DetectSt->StableSt	191	Covered	T13,T43,T41
IdleSt->DebounceSt	148	Covered	T13,T43,T41
StableSt->IdleSt	206	Covered	T13,T43,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T43,T41
0	1	Covered	T13,T43,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T43,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T43,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T43,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T155,T156,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T43,T41
DetectSt	-	-	-	-	1	-	-	Covered	T124,T151,T96
DetectSt	-	-	-	-	0	1	-	Covered	T13,T43,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T43,T41
StableSt	-	-	-	-	-	-	0	Covered	T13,T43,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6669080	148	0	0
CntIncr_A	6669080	84011	0	0
CntNoWrap_A	6669080	6021190	0	0
DetectStDropOut_A	6669080	5	0	0
DetectedOut_A	6669080	86244	0	0
DetectedPulseOut_A	6669080	65	0	0
DisabledIdleSt_A	6669080	5809466	0	0
DisabledNoDetection_A	6669080	5811792	0	0
EnterDebounceSt_A	6669080	79	0	0
EnterDetectSt_A	6669080	70	0	0
EnterStableSt_A	6669080	65	0	0
PulseIsPulse_A	6669080	65	0	0
StayInStableSt	6669080	86150	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6669080	2539	0	0
gen_low_level_sva.LowLevelEvent_A	6669080	6023727	0	0
gen_not_sticky_sva.StableStDropOut_A	6669080	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	148	0	0
T13	777	2	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	8	0	0
T43	0	4	0	0
T45	503	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	2	0	0
T93	0	2	0	0
T100	0	4	0	0
T158	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	84011	0	0
T13	777	35	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	283	0	0
T43	0	102	0	0
T45	503	0	0	0
T46	0	51	0	0
T47	0	57	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	33	0	0
T93	0	17057	0	0
T100	0	145	0	0
T158	0	21	0	0
T159	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6021190	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5	0	0
T96	0	1	0	0
T103	29221	0	0	0
T124	44577	1	0	0
T151	0	1	0	0
T155	727	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	507	0	0	0
T163	47585	0	0	0
T164	414	0	0	0
T165	538	0	0	0
T166	722	0	0	0
T167	428	0	0	0
T168	938	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	86244	0	0
T13	777	142	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	201	0	0
T43	0	134	0	0
T45	503	0	0	0
T46	0	363	0	0
T47	0	86	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	101	0	0
T93	0	43	0	0
T100	0	500	0	0
T158	0	38	0	0
T159	0	100	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	65	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T43	0	2	0	0
T45	503	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5809466	0	0
T1	11087	10679	0	0
T2	29615	29145	0	0
T3	687	286	0	0
T4	520	119	0	0
T5	856	455	0	0
T6	606	205	0	0
T7	21017	20559	0	0
T14	433	32	0	0
T15	8200	7799	0	0
T16	12100	11678	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	5811792	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	79	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T43	0	2	0	0
T45	503	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T93	0	2	0	0
T100	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	70	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T43	0	2	0	0
T45	503	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	65	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T43	0	2	0	0
T45	503	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	65	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	4	0	0
T43	0	2	0	0
T45	503	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T100	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	86150	0	0
T13	777	141	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	196	0	0
T43	0	131	0	0
T45	503	0	0	0
T46	0	361	0	0
T47	0	85	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	100	0	0
T93	0	41	0	0
T100	0	496	0	0
T158	0	36	0	0
T159	0	99	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	2539	0	0
T3	687	0	0	0
T7	21017	0	0	0
T8	0	2	0	0
T9	0	6	0	0
T14	433	4	0	0
T15	8200	0	0	0
T16	12100	0	0	0
T17	496	4	0	0
T18	540	0	0	0
T19	405	0	0	0
T30	503	7	0	0
T31	0	5	0	0
T32	0	5	0	0
T56	0	2	0	0
T57	0	3	0	0
T58	0	2	0	0
T62	870	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	6023727	0	0
T1	11087	10681	0	0
T2	29615	29157	0	0
T3	687	287	0	0
T4	520	120	0	0
T5	856	456	0	0
T6	606	206	0	0
T7	21017	20567	0	0
T14	433	33	0	0
T15	8200	7800	0	0
T16	12100	11682	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6669080	34	0	0
T13	777	1	0	0
T27	493	0	0	0
T29	524	0	0	0
T36	1059	0	0	0
T41	0	3	0	0
T43	0	1	0	0
T45	503	0	0	0
T47	0	1	0	0
T50	706	0	0	0
T51	669	0	0	0
T64	1350	0	0	0
T75	528	0	0	0
T76	522	0	0	0
T85	0	1	0	0
T96	0	2	0	0
T151	0	1	0	0
T159	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0