Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_pin_in_value_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_pin_in_value_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_pin_in_value_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 0 16 100.00


Variables for Group Instance sysrst_ctrl_pin_in_value_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present 2 0 2 100.00 100 1 1 2
cp_ec_rst_l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l 2 0 2 100.00 100 1 1 2
cp_key0_in 2 0 2 100.00 100 1 1 2
cp_key1_in 2 0 2 100.00 100 1 1 2
cp_key2_in 2 0 2 100.00 100 1 1 2
cp_lid_open 2 0 2 100.00 100 1 1 2
cp_pwrb_in 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1251 1 T53 22 T109 7 T90 8
auto[1] 1256 1 T53 21 T370 3 T109 6



Summary for Variable cp_ec_rst_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1229 1 T53 20 T109 7 T90 14
auto[1] 1278 1 T53 23 T370 3 T109 6



Summary for Variable cp_flash_wp_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1243 1 T53 21 T370 2 T109 8
auto[1] 1264 1 T53 22 T370 1 T109 5



Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1238 1 T53 22 T370 2 T109 7
auto[1] 1269 1 T53 21 T370 1 T109 6



Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1235 1 T53 15 T370 1 T109 10
auto[1] 1272 1 T53 28 T370 2 T109 3



Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1249 1 T53 16 T370 2 T109 5
auto[1] 1258 1 T53 27 T370 1 T109 8



Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1214 1 T53 16 T370 1 T109 5
auto[1] 1293 1 T53 27 T370 2 T109 8



Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1250 1 T53 26 T370 3 T109 8
auto[1] 1257 1 T53 17 T109 5 T90 12

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