Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T2

4

T3

17

T7

4

auto[1]

689

1

T1

5

T3

3

T7

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2108

1

T1

4

T2

4

T3

20

auto[1]

576

1

T1

1

T7

5

T8

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2101

1

T2

4

T3

14

T7

1

auto[1]

583

1

T1

5

T3

6

T7

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T1

5

T2

3

T3

18

auto[1]

609

1

T2

1

T3

2

T7

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424

1

T1

5

T2

3

T3

17

auto[1]

260

1

T2

1

T3

3

T43

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2512

1

T1

5

T2

3

T3

11

auto[1]

172

1

T2

1

T3

9

T56

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T1

5

T2

3

T3

18

auto[1]

344

1

T2

1

T3

2

T56

11

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2480

1

T1

5

T2

4

T3

11

auto[1]

204

1

T3

9

T43

4

T237

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T1

5

T2

3

T3

20

auto[1]

178

1

T2

1

T20

1

T42

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2108

1

T1

1

T2

4

T3

12

auto[1]

576

1

T1

4

T3

8

T8

11

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	785	1			T1	5		T7	5		T8	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	104	1			T43	2		T237	3		T235	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	42	1			T20	1		T43	2		T340	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	24	1			T238	4		T25	1		T97	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	64	1			T43	4		T237	4		T161	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	24	1			T25	1		T26	4		T340	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T26	1		T341	3		T342	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	7	1			T245	5		T343	2		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	173	1			T3	2		T56	7		T43	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	26	1			T161	2		T344	4		T345	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	21	1			T237	2		T346	8		T336	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T320	2		T347	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T320	2		T348	4		T349	6
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T245	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T350	2		T351	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T320	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	48	1			T72	3		T317	1		T340	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T26	3		T96	6		T327	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	19	1			T161	1		T345	3		T352	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T353	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	13	1			T3	6		T318	3		T342	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	9	1			T3	3		T245	2		T318	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	18	1			T56	4		T72	3		T344	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T354	3		T342	1		T355	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T2	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	12	1			T236	3		T356	5		T357	4

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

138

1

T56

4

T72

3

T237

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

97

1

T3

3

T8

8

T46

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

56

1

T163

3

T317

1

T316

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

144

1

T2

1

T43

5

T92

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

82

1

T72

3

T95

12

T314

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T3

2

T75

6

T24

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T8

2

T239

1

T318

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

122

1

T237

3

T26

2

T245

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T3

3

T26

1

T28

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T3

3

T246

3

T358

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T1

4

T43

4

T241

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T25

1

T340

2

T335

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T329

1

T359

6

T190

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T318

3

T247

1

T248

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T98

1

T315

2

T314

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T56

7

T238

4

T25

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

91

1

T73

2

T27

5

T316

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T25

8

T161

6

T345

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T246

2

T360

1

T243

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T235

2

T239

2

T97

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T7

1

T151

1

T361

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T151

1

T314

4

T164

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T8

1

T95

3

T240

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

73

1

T7

4

T237

4

T245

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T1

1

T362

2

T358

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T43

2

T25

1

T138

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T75

2

T138

1

T319

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T20

1

T43

2

T235

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T315

3

T244

3

T363

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T313

2

T242

2

T364

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T243

3

T319

2

T365

3

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded