Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T4

12

T6

7

T18

9

auto[1]

1085

1

T4

8

T6

13

T18

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T4

4

T6

4

T18

5

from_0to1

535

1

T4

5

T6

5

T18

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T4

11

T6

7

T18

11

auto[1]

1118

1

T4

9

T6

13

T18

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T4

9

T6

14

T18

10

auto[1]

1108

1

T4

11

T6

6

T18

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T4

1

T6

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T18

1

T137

1

T376

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T4

1

T68

1

T137

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T4

1

T6

1

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

3

T18

1

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T68

1

T137

2

T51

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T6

1

T68

2

T137

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T4

1

T377

1

T287

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T68

1

T376

1

T51

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T18

1

T137

1

T88

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T6

2

T18

1

T137

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T137

1

T376

1

auto[1]

from_0to1

auto[0]

auto[0]

86

1

T6

2

T18

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T137

1

T377

2

T288

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T4

1

T6

2

T18

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T18

1

T51

1

T288

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T4

11

T6

8

T18

10

auto[1]

1108

1

T4

9

T6

12

T18

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T4

3

T6

4

T18

4

from_0to1

515

1

T4

4

T6

4

T18

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T4

11

T6

11

T18

13

auto[1]

1106

1

T4

9

T6

9

T18

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T4

11

T6

9

T18

10

auto[1]

1095

1

T4

9

T6

11

T18

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T6

1

T287

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T18

2

T137

1

T51

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T4

1

T18

1

T68

3

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T6

1

T68

1

T377

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T4

2

T68

1

T376

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T376

3

T288

1

T378

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T6

1

T137

1

T51

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T18

1

T377

1

T288

2

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T6

1

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T6

1

T18

1

T137

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T51

1

T287

1

T378

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T376

3

T377

1

T88

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T18

2

T68

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T4

1

T6

1

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T4

1

T68

1

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T6

2

T137

1

T51

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T4

9

T6

12

T18

7

auto[1]

1136

1

T4

11

T6

8

T18

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T4

5

T6

5

T18

5

from_0to1

524

1

T4

5

T6

5

T18

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T4

10

T6

9

T18

12

auto[1]

1076

1

T4

10

T6

11

T18

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T4

12

T6

9

T18

12

auto[1]

1078

1

T4

8

T6

11

T18

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T4

1

T6

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T288

2

T88

1

T36

2

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T4

2

T6

1

T137

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T4

1

T6

1

T51

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T68

1

T137

1

T377

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T6

2

T18

1

T137

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T68

1

T137

1

T377

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T4

1

T137

1

T376

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T4

1

T18

2

T68

2

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T6

2

T18

1

T137

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T18

2

T137

1

T376

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T68

1

T376

1

T51

1

auto[1]

from_0to1

auto[0]

auto[0]

92

1

T4

1

T18

2

T137

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T288

2

T88

1

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T4

2

T68

1

T137

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T4

1

T6

3

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T4

10

T6

8

T18

9

auto[1]

1109

1

T4

10

T6

12

T18

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T4

6

T6

5

T18

7

from_0to1

553

1

T4

5

T6

5

T18

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T4

12

T6

9

T18

11

auto[1]

1105

1

T4

8

T6

11

T18

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T4

10

T6

12

T18

10

auto[1]

1087

1

T4

10

T6

8

T18

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T4

1

T18

1

T137

3

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T4

2

T68

1

T379

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T6

1

T68

1

T51

2

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T4

1

T18

2

T137

1

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T4

1

T6

1

T18

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T4

2

T137

2

T377

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T6

1

T376

1

T51

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T68

1

T376

2

T51

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T6

1

T376

1

T51

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T4

1

T6

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T6

1

T18

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T6

1

T18

1

T137

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T6

2

T137

1

T377

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T4

1

T18

3

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T4

1

T18

1

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T137

1

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T4

8

T6

11

T18

11

auto[1]

1121

1

T4

12

T6

9

T18

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T4

5

T6

4

T18

3

from_0to1

521

1

T4

6

T6

4

T18

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T4

9

T6

10

T18

10

auto[1]

1075

1

T4

11

T6

10

T18

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T4

11

T6

9

T18

10

auto[1]

1083

1

T4

9

T6

11

T18

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T18

2

T68

1

T377

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T6

1

T68

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T4

1

T376

2

T379

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T4

1

T51

1

T287

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T4

2

T377

1

T163

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T6

1

T68

2

T287

2

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T137

1

T377

2

T287

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T6

1

T68

1

T376

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T4

1

T68

2

T51

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T4

2

T6

2

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

86

1

T18

1

T68

1

T137

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T6

1

T51

1

T88

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T6

2

T137

2

T88

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

2

T18

1

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T4

2

T18

2

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T68

1

T376

3

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T4

10

T6

10

T18

10

auto[1]

1068

1

T4

10

T6

10

T18

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T4

5

T6

4

T18

6

from_0to1

526

1

T4

5

T6

4

T18

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T4

9

T6

7

T18

9

auto[1]

1132

1

T4

11

T6

13

T18

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T4

9

T6

9

T18

11

auto[1]

1078

1

T4

11

T6

11

T18

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T6

2

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T18

1

T51

1

T377

3

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T4

1

T18

2

T68

2

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T6

1

T68

1

T137

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T4

1

T18

1

T377

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T137

2

T377

1

T36

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T18

1

T137

1

T51

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

1

T18

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T6

1

T287

1

T41

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T4

1

T18

1

T287

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T4

1

T18

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T4

1

T18

1

T137

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T18

1

T68

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T4

1

T18

2

T68

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T6

2

T51

2

T377

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T4

2

T6

2

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T4

10

T6

10

T18

16

auto[1]

1069

1

T4

10

T6

10

T18

4

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T4

3

T6

4

T18

6

from_0to1

528

1

T4

4

T6

4

T18

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T4

14

T6

14

T18

10

auto[1]

1052

1

T4

6

T6

6

T18

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T4

5

T6

10

T18

13

auto[1]

1108

1

T4

15

T6

10

T18

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T4

1

T6

2

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T376

1

T287

1

T288

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T18

1

T68

1

T51

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T6

1

T18

2

T68

2

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T18

2

T68

1

T137

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T6

1

T18

2

T51

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T4

1

T6

1

T18

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T18

1

T68

1

T137

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T18

1

T137

1

T51

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T4

2

T6

1

T287

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T18

1

T376

1

T287

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T137

1

T376

1

T287

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T137

1

T376

2

T377

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T4

1

T6

1

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T4

1

T6

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T4

1

T88

2

T378

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T4

8

T6

7

T18

7

auto[1]

1085

1

T4

12

T6

13

T18

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T4

4

T6

6

T18

6

from_0to1

531

1

T4

4

T6

5

T18

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T4

7

T6

9

T18

10

auto[1]

1132

1

T4

13

T6

11

T18

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T4

10

T6

11

T18

12

auto[1]

1076

1

T4

10

T6

9

T18

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T18

1

T137

3

T377

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T68

1

T376

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T4

1

T287

1

T36

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T68

1

T137

1

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T18

1

T377

2

T287

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T137

1

T376

1

T51

1

auto[0]

from_0to1

auto[1]

auto[0]

81

1

T6

1

T18

2

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T6

1

T18

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T6

1

T18

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T6

1

T18

2

T376

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T4

1

T6

4

T18

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T4

2

T18

1

T137

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T18

1

T68

1

T137

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T4

1

T6

1

T137

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T4

2

T6

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T4

1

T6

1

T68

1