Summary for Variable cp_h2l_pwrb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_h2l_pwrb
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
860 |
1 |
|
|
T4 |
13 |
|
T6 |
9 |
|
T8 |
2 |
auto[1] |
729 |
1 |
|
|
T4 |
3 |
|
T13 |
1 |
|
T6 |
7 |
Summary for Variable cp_h_ac_present
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_h_ac_present
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
997 |
1 |
|
|
T4 |
11 |
|
T6 |
8 |
|
T8 |
3 |
auto[1] |
592 |
1 |
|
|
T4 |
5 |
|
T13 |
1 |
|
T6 |
8 |
Summary for Variable cp_interrupt_gen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_interrupt_gen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1588 |
1 |
|
|
T4 |
16 |
|
T13 |
1 |
|
T6 |
16 |
auto[1] |
1 |
1 |
|
|
T298 |
1 |
|
- |
- |
|
- |
- |
Summary for Variable cp_l2h_lid_open
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_l2h_lid_open
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
938 |
1 |
|
|
T4 |
6 |
|
T6 |
10 |
|
T8 |
2 |
auto[1] |
651 |
1 |
|
|
T4 |
10 |
|
T13 |
1 |
|
T6 |
6 |
Summary for Variable cp_wakeup_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_wakeup_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1526 |
1 |
|
|
T4 |
16 |
|
T13 |
1 |
|
T6 |
15 |
auto[1] |
63 |
1 |
|
|
T6 |
1 |
|
T9 |
1 |
|
T11 |
1 |
Summary for Cross cross_wkup_sts
Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
23 |
15 |
8 |
34.78 |
15 |
Automatically Generated Cross Bins |
23 |
15 |
8 |
34.78 |
15 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cross_wkup_sts
Element holes
cp_wakeup_sts | cp_h2l_pwrb | cp_l2h_lid_open | cp_h_ac_present | cp_interrupt_gen | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[0]] |
* |
* |
* |
-- |
-- |
8 |
|
[auto[1]] |
[auto[1]] |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
2 |
|
[auto[1]] |
[auto[1]] |
[auto[1]] |
* |
* |
-- |
-- |
4 |
|
Uncovered bins
cp_wakeup_sts | cp_h2l_pwrb | cp_l2h_lid_open | cp_h_ac_present | cp_interrupt_gen | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[1]] |
[auto[0]] |
[auto[0]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_wakeup_sts | cp_h2l_pwrb | cp_l2h_lid_open | cp_h_ac_present | cp_interrupt_gen | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
382 |
1 |
|
|
T4 |
4 |
|
T6 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
137 |
1 |
|
|
T4 |
2 |
|
T6 |
3 |
|
T53 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
167 |
1 |
|
|
T4 |
5 |
|
T6 |
2 |
|
T17 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
173 |
1 |
|
|
T4 |
2 |
|
T6 |
2 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
227 |
1 |
|
|
T6 |
3 |
|
T53 |
2 |
|
T11 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
128 |
1 |
|
|
T6 |
1 |
|
T53 |
1 |
|
T66 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
157 |
1 |
|
|
T4 |
2 |
|
T8 |
1 |
|
T53 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
154 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T6 |
2 |
User Defined Cross Bins for cross_wkup_sts
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid0 |
0 |
Excluded |
invalid1 |
0 |
Excluded |