Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117529

1

T1

239

T2

169

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140739	1			T1	389		T2	104		T5	2
values[0x0]	65738	1			T1	39		T2	229		T12	4
values[0x1]	66449	1			T1	40		T2	233		T12	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125837	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147089

1

T1

282

T2

217

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1494	1			T1	6		T2	2		T4	1
valid_sources[0x01]	906	1			T1	3		T2	2		T4	1
valid_sources[0x02]	1035	1			T1	2		T2	3		T20	3
valid_sources[0x03]	950	1			T2	3		T4	3		T13	2
valid_sources[0x04]	1794	1			T2	2		T4	5		T20	3
valid_sources[0x05]	709	1			T1	3		T2	3		T3	9
valid_sources[0x06]	796	1			T1	2		T2	1		T4	3
valid_sources[0x07]	826	1			T1	3		T2	2		T3	1
valid_sources[0x08]	2027	1			T1	1		T2	3		T3	27
valid_sources[0x09]	930	1			T1	2		T2	3		T20	2
valid_sources[0x0a]	1103	1			T2	1		T3	9		T4	1
valid_sources[0x0b]	807	1			T1	1		T2	1		T3	33
valid_sources[0x0c]	1046	1			T2	2		T20	3		T44	3
valid_sources[0x0d]	861	1			T1	4		T2	1		T13	1
valid_sources[0x0e]	834	1			T1	2		T2	2		T20	3
valid_sources[0x0f]	1050	1			T1	5		T2	2		T4	8
valid_sources[0x10]	1151	1			T2	4		T7	1		T20	3
valid_sources[0x11]	801	1			T1	1		T2	2		T4	4
valid_sources[0x12]	768	1			T1	1		T2	2		T4	2
valid_sources[0x13]	853	1			T2	1		T7	8		T20	3
valid_sources[0x14]	1931	1			T1	1		T2	1		T4	1
valid_sources[0x15]	862	1			T1	3		T2	6		T20	4
valid_sources[0x16]	1031	1			T1	4		T2	6		T4	3
valid_sources[0x17]	838	1			T1	4		T3	55		T4	2
valid_sources[0x18]	1049	1			T1	1		T2	1		T5	1
valid_sources[0x19]	972	1			T1	3		T2	1		T4	5
valid_sources[0x1a]	863	1			T1	3		T2	4		T4	2
valid_sources[0x1b]	863	1			T1	1		T2	3		T4	1
valid_sources[0x1c]	1021	1			T1	1		T2	1		T3	11
valid_sources[0x1d]	998	1			T1	4		T2	1		T4	5
valid_sources[0x1e]	810	1			T2	2		T4	3		T20	2
valid_sources[0x1f]	2054	1			T1	2		T2	5		T3	38
valid_sources[0x20]	1989	1			T1	3		T2	2		T4	1
valid_sources[0x21]	926	1			T1	2		T2	3		T4	1
valid_sources[0x22]	784	1			T2	1		T4	1		T20	4
valid_sources[0x23]	899	1			T1	1		T2	2		T3	1
valid_sources[0x24]	1055	1			T1	2		T2	1		T3	57
valid_sources[0x25]	925	1			T1	5		T2	2		T20	1
valid_sources[0x26]	1254	1			T1	1		T4	2		T13	1
valid_sources[0x27]	1029	1			T1	3		T2	3		T4	1
valid_sources[0x28]	1442	1			T1	1		T3	15		T4	3
valid_sources[0x29]	952	1			T1	1		T2	1		T4	3
valid_sources[0x2a]	944	1			T1	4		T2	1		T4	2
valid_sources[0x2b]	811	1			T1	1		T2	2		T13	1
valid_sources[0x2c]	881	1			T1	4		T2	2		T4	2
valid_sources[0x2d]	704	1			T2	2		T4	3		T6	4
valid_sources[0x2e]	885	1			T1	3		T2	1		T4	2
valid_sources[0x2f]	1605	1			T1	1		T2	1		T4	5
valid_sources[0x30]	972	1			T2	1		T12	1		T20	4
valid_sources[0x31]	1281	1			T1	2		T2	3		T4	1
valid_sources[0x32]	1041	1			T1	3		T2	1		T3	7
valid_sources[0x33]	1576	1			T2	2		T3	30		T20	3
valid_sources[0x34]	980	1			T1	2		T2	1		T4	4
valid_sources[0x35]	932	1			T1	4		T2	3		T4	4
valid_sources[0x36]	818	1			T1	3		T2	6		T4	1
valid_sources[0x37]	840	1			T1	1		T2	2		T12	1
valid_sources[0x38]	1467	1			T1	1		T2	1		T4	1
valid_sources[0x39]	905	1			T1	1		T2	3		T4	2
valid_sources[0x3a]	856	1			T1	2		T2	3		T4	2
valid_sources[0x3b]	980	1			T2	1		T4	1		T13	1
valid_sources[0x3c]	901	1			T1	5		T2	4		T4	3
valid_sources[0x3d]	1929	1			T1	2		T2	1		T3	70
valid_sources[0x3e]	982	1			T1	2		T2	3		T4	1
valid_sources[0x3f]	1087	1			T1	4		T2	1		T4	1
valid_sources[0x40]	2102	1			T1	1		T2	1		T4	2
valid_sources[0x41]	1054	1			T1	1		T2	5		T3	39
valid_sources[0x42]	1527	1			T1	3		T2	2		T4	3
valid_sources[0x43]	1089	1			T1	2		T2	3		T12	1
valid_sources[0x44]	852	1			T1	2		T2	3		T4	1
valid_sources[0x45]	866	1			T2	1		T4	6		T6	1
valid_sources[0x46]	766	1			T1	5		T2	1		T4	2
valid_sources[0x47]	1002	1			T1	2		T2	3		T3	27
valid_sources[0x48]	1716	1			T1	1		T2	2		T13	1
valid_sources[0x49]	754	1			T2	3		T4	3		T20	2
valid_sources[0x4a]	1090	1			T1	7		T2	2		T13	1
valid_sources[0x4b]	899	1			T1	2		T2	2		T4	1
valid_sources[0x4c]	1130	1			T1	4		T2	2		T12	2
valid_sources[0x4d]	961	1			T2	3		T3	11		T4	3
valid_sources[0x4e]	803	1			T2	5		T4	2		T20	4
valid_sources[0x4f]	939	1			T2	3		T4	4		T7	3
valid_sources[0x50]	887	1			T1	4		T2	5		T4	1
valid_sources[0x51]	1146	1			T1	2		T4	3		T7	6
valid_sources[0x52]	986	1			T1	1		T2	4		T4	2
valid_sources[0x53]	814	1			T1	3		T2	1		T4	3
valid_sources[0x54]	1033	1			T2	7		T3	4		T4	5
valid_sources[0x55]	884	1			T1	2		T2	1		T4	1
valid_sources[0x56]	1607	1			T1	4		T2	4		T4	2
valid_sources[0x57]	1274	1			T2	1		T3	12		T4	5
valid_sources[0x58]	855	1			T1	2		T2	6		T3	12
valid_sources[0x59]	967	1			T1	5		T2	1		T3	34
valid_sources[0x5a]	1014	1			T1	1		T2	2		T4	1
valid_sources[0x5b]	1042	1			T1	4		T2	5		T4	2
valid_sources[0x5c]	745	1			T1	1		T2	4		T4	5
valid_sources[0x5d]	924	1			T2	3		T4	5		T13	1
valid_sources[0x5e]	942	1			T1	1		T2	2		T4	2
valid_sources[0x5f]	959	1			T1	1		T2	5		T4	2
valid_sources[0x60]	886	1			T2	3		T4	5		T20	5
valid_sources[0x61]	1117	1			T1	2		T4	3		T6	309
valid_sources[0x62]	917	1			T1	2		T2	3		T3	7
valid_sources[0x63]	1120	1			T1	3		T2	1		T7	1
valid_sources[0x64]	955	1			T1	1		T2	4		T4	1
valid_sources[0x65]	1240	1			T1	2		T3	51		T7	12
valid_sources[0x66]	1095	1			T1	1		T2	4		T3	9
valid_sources[0x67]	713	1			T1	3		T2	2		T4	4
valid_sources[0x68]	908	1			T1	3		T2	1		T4	4
valid_sources[0x69]	855	1			T1	1		T2	3		T3	5
valid_sources[0x6a]	1263	1			T2	3		T4	3		T7	6
valid_sources[0x6b]	1547	1			T2	1		T12	3		T4	2
valid_sources[0x6c]	997	1			T1	2		T2	2		T20	2
valid_sources[0x6d]	921	1			T2	2		T4	1		T20	4
valid_sources[0x6e]	948	1			T1	1		T2	3		T20	3
valid_sources[0x6f]	974	1			T1	2		T2	3		T4	4
valid_sources[0x70]	757	1			T1	5		T2	2		T20	7
valid_sources[0x71]	812	1			T1	3		T2	4		T7	2
valid_sources[0x72]	1218	1			T1	3		T2	3		T5	1
valid_sources[0x73]	814	1			T2	2		T4	6		T13	1
valid_sources[0x74]	2004	1			T1	2		T2	4		T4	2
valid_sources[0x75]	1857	1			T1	2		T2	3		T4	1
valid_sources[0x76]	1282	1			T1	1		T2	4		T13	1
valid_sources[0x77]	909	1			T2	2		T4	3		T7	1
valid_sources[0x78]	1199	1			T2	4		T4	1		T7	4
valid_sources[0x79]	728	1			T2	2		T7	1		T20	4
valid_sources[0x7a]	1988	1			T1	1		T2	2		T4	2
valid_sources[0x7b]	972	1			T1	2		T3	6		T4	2
valid_sources[0x7c]	725	1			T2	3		T4	1		T20	2
valid_sources[0x7d]	927	1			T1	1		T2	4		T20	1
valid_sources[0x7e]	1071	1			T1	1		T2	3		T3	92
valid_sources[0x7f]	924	1			T1	3		T2	2		T4	2
valid_sources[0x80]	905	1			T1	4		T2	3		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63548

1

T1

199

T2

49

T5

2

values[0x0]

all_enables

biggest_size

31650

1

T1

23

T2

84

T12

3

values[0x1]

all_enables

biggest_size

22331

1

T1

17

T2

36

T12

2