Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1272196423	9490	0	0
auto_block_debounce_ctl_rd_A	1272196423	2696	0	0
auto_block_out_ctl_rd_A	1272196423	3532	0	0
com_det_ctl_0_rd_A	1272196423	4596	0	0
com_det_ctl_1_rd_A	1272196423	4592	0	0
com_det_ctl_2_rd_A	1272196423	4653	0	0
com_det_ctl_3_rd_A	1272196423	4915	0	0
com_out_ctl_0_rd_A	1272196423	5407	0	0
com_out_ctl_1_rd_A	1272196423	5141	0	0
com_out_ctl_2_rd_A	1272196423	5353	0	0
com_out_ctl_3_rd_A	1272196423	5229	0	0
com_pre_det_ctl_0_rd_A	1272196423	1989	0	0
com_pre_det_ctl_1_rd_A	1272196423	2004	0	0
com_pre_det_ctl_2_rd_A	1272196423	2015	0	0
com_pre_det_ctl_3_rd_A	1272196423	2094	0	0
com_pre_sel_ctl_0_rd_A	1272196423	5631	0	0
com_pre_sel_ctl_1_rd_A	1272196423	5489	0	0
com_pre_sel_ctl_2_rd_A	1272196423	5555	0	0
com_pre_sel_ctl_3_rd_A	1272196423	5453	0	0
com_sel_ctl_0_rd_A	1272196423	5601	0	0
com_sel_ctl_1_rd_A	1272196423	5463	0	0
com_sel_ctl_2_rd_A	1272196423	5668	0	0
com_sel_ctl_3_rd_A	1272196423	5444	0	0
ec_rst_ctl_rd_A	1272196423	3034	0	0
intr_enable_rd_A	1272196423	2509	0	0
key_intr_ctl_rd_A	1272196423	4344	0	0
key_intr_debounce_ctl_rd_A	1272196423	2220	0	0
key_invert_ctl_rd_A	1272196423	6339	0	0
pin_allowed_ctl_rd_A	1272196423	7598	0	0
pin_out_ctl_rd_A	1272196423	5782	0	0
pin_out_value_rd_A	1272196423	5999	0	0
regwen_rd_A	1272196423	2179	0	0
ulp_ac_debounce_ctl_rd_A	1272196423	2122	0	0
ulp_ctl_rd_A	1272196423	2053	0	0
ulp_lid_debounce_ctl_rd_A	1272196423	2197	0	0
ulp_pwrb_debounce_ctl_rd_A	1272196423	2175	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	9490	0	0
T4	271768	7	0	0
T6	189497	3	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	3	0	0
T31	0	7	0	0
T36	0	22	0	0
T37	0	9	0	0
T39	0	2	0	0
T44	326649	0	0	0
T49	0	29	0	0
T53	243414	14	0	0
T163	0	16	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2696	0	0
T4	271768	32	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	11	0	0
T20	478002	0	0	0
T28	0	30	0	0
T44	326649	0	0	0
T48	0	8	0	0
T50	0	3	0	0
T53	243414	0	0	0
T108	0	10	0	0
T280	0	7	0	0
T281	0	22	0	0
T282	0	22	0	0
T283	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	3532	0	0
T4	271768	24	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	8	0	0
T20	478002	0	0	0
T28	0	32	0	0
T44	326649	0	0	0
T48	0	4	0	0
T50	0	5	0	0
T53	243414	0	0	0
T108	0	15	0	0
T280	0	4	0	0
T281	0	19	0	0
T282	0	22	0	0
T283	0	5	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	4596	0	0
T2	233086	12	0	0
T3	662248	0	0	0
T4	271768	27	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	25	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	16	0	0
T27	0	38	0	0
T28	0	31	0	0
T77	0	42	0	0
T93	0	34	0	0
T237	0	70	0	0
T238	0	44	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	4592	0	0
T2	233086	17	0	0
T3	662248	0	0	0
T4	271768	24	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	39	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	21	0	0
T27	0	79	0	0
T28	0	33	0	0
T77	0	78	0	0
T93	0	39	0	0
T237	0	47	0	0
T238	0	15	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	4653	0	0
T2	233086	10	0	0
T3	662248	0	0	0
T4	271768	20	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	54	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	42	0	0
T27	0	92	0	0
T28	0	22	0	0
T77	0	41	0	0
T93	0	46	0	0
T237	0	71	0	0
T238	0	19	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	4915	0	0
T2	233086	17	0	0
T3	662248	0	0	0
T4	271768	23	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	51	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	27	0	0
T27	0	76	0	0
T28	0	19	0	0
T77	0	46	0	0
T93	0	53	0	0
T237	0	77	0	0
T238	0	38	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5407	0	0
T2	233086	11	0	0
T3	662248	0	0	0
T4	271768	17	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	45	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	41	0	0
T27	0	73	0	0
T28	0	41	0	0
T77	0	47	0	0
T93	0	44	0	0
T237	0	52	0	0
T238	0	36	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5141	0	0
T2	233086	9	0	0
T3	662248	0	0	0
T4	271768	20	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	39	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	45	0	0
T27	0	69	0	0
T28	0	25	0	0
T77	0	38	0	0
T93	0	55	0	0
T237	0	47	0	0
T238	0	33	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5353	0	0
T2	233086	9	0	0
T3	662248	0	0	0
T4	271768	25	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	42	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	42	0	0
T27	0	66	0	0
T28	0	43	0	0
T77	0	70	0	0
T93	0	54	0	0
T237	0	76	0	0
T238	0	44	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5229	0	0
T2	233086	17	0	0
T3	662248	0	0	0
T4	271768	25	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	42	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	21	0	0
T27	0	81	0	0
T28	0	30	0	0
T77	0	60	0	0
T93	0	41	0	0
T237	0	59	0	0
T238	0	39	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	1989	0	0
T4	271768	21	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	10	0	0
T31	0	31	0	0
T37	0	34	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	32	0	0
T138	0	11	0	0
T154	0	21	0	0
T205	0	1	0	0
T214	0	5	0	0
T284	0	6	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2004	0	0
T4	271768	27	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	12	0	0
T31	0	24	0	0
T37	0	30	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	13	0	0
T138	0	11	0	0
T154	0	3	0	0
T214	0	11	0	0
T284	0	24	0	0
T285	0	11	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2015	0	0
T4	271768	6	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	13	0	0
T31	0	25	0	0
T37	0	50	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	24	0	0
T138	0	13	0	0
T154	0	5	0	0
T214	0	6	0	0
T284	0	11	0	0
T285	0	10	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2094	0	0
T4	271768	20	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	14	0	0
T31	0	27	0	0
T37	0	51	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	27	0	0
T138	0	14	0	0
T154	0	6	0	0
T205	0	18	0	0
T214	0	20	0	0
T284	0	7	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5631	0	0
T2	233086	13	0	0
T3	662248	0	0	0
T4	271768	28	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	70	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	21	0	0
T27	0	57	0	0
T28	0	37	0	0
T77	0	56	0	0
T93	0	44	0	0
T237	0	69	0	0
T238	0	40	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5489	0	0
T2	233086	6	0	0
T3	662248	0	0	0
T4	271768	9	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	56	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	26	0	0
T27	0	42	0	0
T28	0	31	0	0
T77	0	44	0	0
T93	0	55	0	0
T237	0	62	0	0
T238	0	28	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5555	0	0
T2	233086	25	0	0
T3	662248	0	0	0
T4	271768	31	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	28	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	55	0	0
T27	0	76	0	0
T28	0	57	0	0
T77	0	39	0	0
T93	0	54	0	0
T237	0	51	0	0
T238	0	39	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5453	0	0
T2	233086	20	0	0
T3	662248	0	0	0
T4	271768	19	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	46	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	37	0	0
T27	0	74	0	0
T28	0	29	0	0
T77	0	38	0	0
T93	0	71	0	0
T237	0	60	0	0
T238	0	34	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5601	0	0
T2	233086	11	0	0
T3	662248	0	0	0
T4	271768	17	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	60	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	32	0	0
T27	0	88	0	0
T28	0	34	0	0
T77	0	32	0	0
T93	0	52	0	0
T237	0	67	0	0
T238	0	56	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5463	0	0
T2	233086	13	0	0
T3	662248	0	0	0
T4	271768	29	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	35	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	40	0	0
T27	0	66	0	0
T28	0	24	0	0
T77	0	57	0	0
T93	0	57	0	0
T237	0	59	0	0
T238	0	42	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5668	0	0
T2	233086	15	0	0
T3	662248	0	0	0
T4	271768	23	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	35	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	37	0	0
T27	0	68	0	0
T28	0	40	0	0
T77	0	58	0	0
T93	0	44	0	0
T237	0	70	0	0
T238	0	39	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5444	0	0
T2	233086	12	0	0
T3	662248	0	0	0
T4	271768	6	0	0
T5	530543	0	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	33	0	0
T12	290415	0	0	0
T13	135978	0	0	0
T20	478002	0	0	0
T25	0	24	0	0
T27	0	64	0	0
T28	0	21	0	0
T77	0	31	0	0
T93	0	65	0	0
T237	0	54	0	0
T238	0	58	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	3034	0	0
T4	271768	26	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	29	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T25	0	13	0	0
T27	0	23	0	0
T28	0	37	0	0
T44	326649	1	0	0
T53	243414	0	0	0
T77	0	5	0	0
T93	0	2	0	0
T237	0	20	0	0
T238	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2509	0	0
T4	271768	26	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	27	0	0
T31	0	16	0	0
T37	0	67	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T132	0	7	0	0
T138	0	25	0	0
T154	0	26	0	0
T214	0	20	0	0
T284	0	22	0	0
T285	0	7	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	4344	0	0
T4	271768	21	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	1	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	12	0	0
T31	0	41	0	0
T37	0	52	0	0
T41	0	8	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T138	0	16	0	0
T150	0	4	0	0
T186	0	7	0	0
T214	0	6	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2220	0	0
T4	271768	15	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	10	0	0
T31	0	27	0	0
T37	0	40	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	24	0	0
T138	0	7	0	0
T154	0	23	0	0
T214	0	7	0	0
T284	0	1	0	0
T285	0	8	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	6339	0	0
T4	271768	127	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	12	0	0
T31	0	176	0	0
T37	0	141	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T65	0	74	0	0
T132	0	101	0	0
T138	0	83	0	0
T183	0	59	0	0
T214	0	10	0	0
T286	0	60	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	7598	0	0
T4	271768	89	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	24	0	0
T31	0	105	0	0
T37	0	40	0	0
T41	0	36	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T137	0	50	0	0
T138	0	160	0	0
T287	0	73	0	0
T288	0	84	0	0
T289	0	43	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5782	0	0
T4	271768	102	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	6	0	0
T31	0	116	0	0
T37	0	22	0	0
T41	0	37	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T137	0	61	0	0
T138	0	171	0	0
T287	0	68	0	0
T288	0	73	0	0
T289	0	28	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	5999	0	0
T4	271768	102	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	19	0	0
T31	0	87	0	0
T37	0	30	0	0
T41	0	30	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T137	0	65	0	0
T138	0	185	0	0
T287	0	69	0	0
T288	0	75	0	0
T289	0	46	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2179	0	0
T4	271768	9	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	15	0	0
T31	0	28	0	0
T37	0	27	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T102	0	20	0	0
T138	0	9	0	0
T154	0	9	0	0
T214	0	11	0	0
T284	0	3	0	0
T285	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2122	0	0
T4	271768	24	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T11	0	5	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	10	0	0
T31	0	20	0	0
T37	0	39	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T60	0	7	0	0
T81	0	13	0	0
T113	0	9	0	0
T138	0	12	0	0
T214	0	12	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2053	0	0
T4	271768	17	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T11	0	8	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	5	0	0
T31	0	14	0	0
T37	0	50	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T60	0	1	0	0
T113	0	8	0	0
T138	0	5	0	0
T214	0	24	0	0
T290	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2197	0	0
T4	271768	20	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	22	0	0
T31	0	33	0	0
T37	0	51	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T60	0	15	0	0
T81	0	3	0	0
T113	0	11	0	0
T138	0	15	0	0
T214	0	8	0	0
T291	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272196423	2175	0	0
T4	271768	20	0	0
T6	189497	0	0	0
T7	190377	0	0	0
T8	607144	0	0	0
T9	55123	0	0	0
T11	0	9	0	0
T13	135978	0	0	0
T19	386135	0	0	0
T20	478002	0	0	0
T28	0	15	0	0
T31	0	16	0	0
T37	0	41	0	0
T44	326649	0	0	0
T53	243414	0	0	0
T60	0	4	0	0
T113	0	1	0	0
T138	0	17	0	0
T214	0	28	0	0
T290	0	4	0	0