Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2151

1

T7

8

T1

14

T2

3

auto[1]

623

1

T1

2

T2

10

T10

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2069

1

T7

4

T1

14

T2

7

auto[1]

705

1

T7

4

T1

2

T2

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2074

1

T7

4

T1

12

T2

5

auto[1]

700

1

T7

4

T1

4

T2

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2092

1

T7

8

T1

14

T2

7

auto[1]

682

1

T1

2

T2

6

T9

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2538

1

T7

8

T1

14

T2

13

auto[1]

236

1

T1

2

T34

4

T37

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2522

1

T7

8

T1

16

T2

13

auto[1]

252

1

T9

8

T36

1

T34

16

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2581

1

T7

8

T1

14

T2

13

auto[1]

193

1

T1

2

T9

4

T54

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2566

1

T7

4

T1

16

T2

13

auto[1]

208

1

T7

4

T36

8

T37

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2527

1

T7

8

T1

12

T2

13

auto[1]

247

1

T1

4

T34

4

T37

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2109

1

T7

6

T1

16

T2

7

auto[1]

665

1

T7

2

T2

6

T9

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	995	1			T2	13		T10	5		T48	3
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	92	1			T1	2		T54	7		T292	14
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	121	1			T1	2		T37	6		T54	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	15	1			T37	4		T87	6		T328	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	78	1			T7	2		T36	8		T292	13
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	10	1			T37	3		T232	6		T76	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	23	1			T390	7		T391	13		T392	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	14	1			T292	11		T373	3		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	70	1			T9	4		T332	1		T278	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	16	1			T226	1		T393	3		T163	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T1	2		T286	1		T394	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T395	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	13	1			T393	2		T390	5		T353	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T284	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T292	8		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	98	1			T9	8		T36	1		T34	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T286	2		T396	1		T397	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T285	2		T383	16		T398	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T34	4		T286	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T226	4		T399	1		T383	11
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	12	1			T395	1		T400	4		T401	7
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T108	5		T277	5		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	19	1			T91	7		T232	5		T385	7
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	12	1			T54	4		T276	1		T391	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T402	9		T398	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T402	7		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T403	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

154

1

T108

5

T331

8

T281

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

92

1

T9

4

T40

1

T89

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T35

3

T36

4

T294

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

123

1

T36

1

T34

2

T279

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

42

1

T375

6

T99

5

T232

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

71

1

T54

4

T276

1

T382

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T48

3

T189

2

T404

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

174

1

T1

2

T50

10

T34

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

80

1

T2

6

T37

6

T139

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T294

7

T395

1

T378

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T2

1

T10

1

T181

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

101

1

T1

2

T9

8

T13

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T34

12

T289

2

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T293

3

T287

7

T286

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T33

1

T331

1

T282

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

105

1

T54

7

T40

1

T292

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T1

2

T89

6

T292

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

173

1

T279

6

T287

10

T292

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T10

4

T293

3

T374

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T37

4

T378

7

T393

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T280

10

T286

1

T405

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T2

2

T292

14

T152

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T2

3

T374

2

T281

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

83

1

T7

1

T108

7

T79

11

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T13

1

T50

2

T35

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T7

1

T152

1

T406

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T36

4

T279

1

T378

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T2

1

T13

2

T396

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T394

1

T97

2

T407

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T33

1

T152

1

T408

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T379

1

T409

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded