Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1248

1

T2

12

T16

9

T55

7

auto[1]

1132

1

T2

8

T16

11

T55

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

579

1

T2

5

T16

5

T55

6

from_0to1

567

1

T2

4

T16

5

T55

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T2

8

T16

8

T55

8

auto[1]

1193

1

T2

12

T16

12

T55

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1174

1

T2

7

T16

6

T55

13

auto[1]

1206

1

T2

13

T16

14

T55

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

86

1

T2

1

T16

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T16

1

T55

1

T57

2

auto[0]

from_1to0

auto[1]

auto[0]

82

1

T57

1

T68

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

94

1

T2

2

T57

1

T68

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T57

1

T41

2

T421

1

auto[0]

from_0to1

auto[0]

auto[1]

91

1

T16

1

T57

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T57

1

T68

2

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T2

2

T16

2

T55

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T55

2

T68

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T2

2

T16

2

T198

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T55

3

T57

1

T50

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T16

1

T68

1

T50

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T57

1

T68

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T2

1

T16

1

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T55

3

T198

2

T421

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T2

1

T16

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1204

1

T2

7

T16

9

T55

11

auto[1]

1176

1

T2

13

T16

11

T55

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T2

3

T16

7

T55

5

from_0to1

551

1

T2

3

T16

6

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T2

11

T16

13

T55

9

auto[1]

1204

1

T2

9

T16

7

T55

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T2

13

T16

11

T55

10

auto[1]

1184

1

T2

7

T16

9

T55

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T16

2

T50

1

T38

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T16

2

T55

1

T57

3

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T2

1

T16

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T55

1

T68

1

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T16

1

T55

1

T50

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T16

1

T55

1

T57

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T16

1

T55

1

T57

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T57

1

T50

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T2

2

T16

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T68

1

T50

2

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T55

1

T50

4

T58

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T16

1

T55

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T2

1

T16

2

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T2

1

T68

2

T50

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T50

3

T38

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T2

1

T16

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T2

9

T16

12

T55

10

auto[1]

1195

1

T2

11

T16

8

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

563

1

T2

3

T16

5

T55

5

from_0to1

570

1

T2

3

T16

4

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1231

1

T2

11

T16

11

T55

8

auto[1]

1149

1

T2

9

T16

9

T55

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T2

8

T16

9

T55

6

auto[1]

1198

1

T2

12

T16

11

T55

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T50

1

T38

1

T198

1

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T2

1

T16

1

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T57

1

T68

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T55

2

T68

1

T50

2

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T16

1

T55

2

T68

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T57

1

T50

2

T38

2

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T16

2

T57

1

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T2

1

T68

1

T58

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T16

1

T38

1

T198

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T2

1

T16

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T2

1

T55

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

84

1

T16

2

T55

1

T50

2

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T38

1

T198

1

T58

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T57

1

T50

4

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T57

1

T50

2

T198

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T2

2

T55

2

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1191

1

T2

7

T16

11

T55

9

auto[1]

1189

1

T2

13

T16

9

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

580

1

T2

5

T16

6

T55

4

from_0to1

568

1

T2

4

T16

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T2

13

T16

10

T55

12

auto[1]

1204

1

T2

7

T16

10

T55

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1236

1

T2

12

T16

11

T55

11

auto[1]

1144

1

T2

8

T16

9

T55

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T16

1

T68

3

T50

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T57

1

T50

2

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T2

1

T16

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T16

1

T55

2

T57

3

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T55

1

T50

2

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T2

1

T16

1

T57

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T2

1

T57

1

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T57

1

T68

3

T50

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T2

3

T68

1

T198

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T2

1

T55

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T55

1

T57

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T16

3

T50

2

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T2

1

T16

2

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T2

1

T16

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T16

1

T68

1

T50

2

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T55

1

T57

2

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1214

1

T2

13

T16

6

T55

14

auto[1]

1166

1

T2

7

T16

14

T55

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T2

2

T16

4

T55

5

from_0to1

565

1

T2

3

T16

5

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T2

13

T16

11

T55

10

auto[1]

1210

1

T2

7

T16

9

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T2

12

T16

12

T55

9

auto[1]

1185

1

T2

8

T16

8

T55

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T50

1

T38

2

T422

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T2

1

T55

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T55

1

T50

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T2

1

T68

1

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

84

1

T2

1

T55

1

T50

2

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T55

1

T57

1

T68

2

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T41

1

T58

1

T421

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T16

1

T55

1

T50

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T16

2

T57

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T16

1

T50

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T16

1

T55

2

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T55

1

T57

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T2

2

T16

1

T57

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T16

1

T68

1

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T16

2

T55

1

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T55

1

T57

1

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T2

12

T16

11

T55

11

auto[1]

1217

1

T2

8

T16

9

T55

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T2

6

T16

5

T55

4

from_0to1

563

1

T2

6

T16

4

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1232

1

T2

7

T16

11

T55

8

auto[1]

1148

1

T2

13

T16

9

T55

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1183

1

T2

11

T16

10

T55

12

auto[1]

1197

1

T2

9

T16

10

T55

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T16

1

T55

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T16

1

T68

1

T198

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T2

3

T57

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T2

1

T55

1

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T2

1

T16

2

T57

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T50

1

T38

1

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T57

1

T41

1

T58

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T2

2

T16

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T2

2

T16

2

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T57

1

T50

1

T38

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T16

1

T55

1

T57

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T50

1

T198

2

T41

3

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T2

1

T55

1

T57

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T55

1

T68

2

T50

3

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T2

1

T57

2

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T2

1

T16

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1188

1

T2

10

T16

8

T55

12

auto[1]

1192

1

T2

10

T16

12

T55

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

569

1

T2

6

T16

3

T55

3

from_0to1

573

1

T2

6

T16

3

T55

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199

1

T2

7

T16

11

T55

7

auto[1]

1181

1

T2

13

T16

9

T55

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T2

7

T16

12

T55

14

auto[1]

1207

1

T2

13

T16

8

T55

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T16

1

T55

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T57

2

T50

3

T38

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T55

2

T68

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T2

3

T57

1

T68

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T16

1

T57

3

T50

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T2

1

T50

2

T41

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T2

1

T68

1

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T2

1

T57

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T198

2

T58

2

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T2

1

T16

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T41

2

T422

1

T340

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T2

2

T16

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T16

1

T55

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

81

1

T55

1

T50

2

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T2

1

T55

1

T57

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T2

2

T16

1

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T2

13

T16

11

T55

10

auto[1]

1198

1

T2

7

T16

9

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

584

1

T2

5

T16

7

T55

6

from_0to1

589

1

T2

6

T16

7

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T2

9

T16

11

T55

6

auto[1]

1187

1

T2

11

T16

9

T55

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T2

12

T16

9

T55

9

auto[1]

1194

1

T2

8

T16

11

T55

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T2

2

T68

1

T422

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T55

1

T57

1

T50

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T2

1

T16

1

T55

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T2

1

T16

1

T55

3

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T16

2

T68

3

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

84

1

T2

3

T16

2

T57

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T2

1

T38

1

T198

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T2

1

T16

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T16

1

T57

2

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T16

1

T50

2

T198

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T57

1

T68

2

T50

3

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T2

1

T16

3

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T2

1

T16

1

T55

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T16

1

T50

1

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T55

1

T57

1

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T55

1

T68

1

T50

1