Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119598

1

T6

106

T7

262

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141901	1			T6	3		T7	261		T8	3
values[0x0]	67091	1			T6	210		T7	253		T8	2
values[0x1]	67151	1			T6	213		T7	280		T19	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149215

1

T6

139

T7

329

T8

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	953	1			T6	2		T7	6		T1	4
valid_sources[0x01]	905	1			T6	3		T7	4		T1	4
valid_sources[0x02]	889	1			T7	3		T1	4		T64	2
valid_sources[0x03]	823	1			T6	4		T7	3		T1	5
valid_sources[0x04]	965	1			T6	1		T7	2		T1	6
valid_sources[0x05]	712	1			T6	1		T7	3		T1	5
valid_sources[0x06]	825	1			T7	9		T1	3		T4	1
valid_sources[0x07]	873	1			T6	2		T7	3		T1	5
valid_sources[0x08]	755	1			T6	2		T7	6		T1	2
valid_sources[0x09]	1333	1			T7	4		T1	3		T3	2
valid_sources[0x0a]	991	1			T6	1		T7	1		T1	9
valid_sources[0x0b]	903	1			T6	4		T7	4		T1	6
valid_sources[0x0c]	953	1			T7	1		T1	4		T4	1
valid_sources[0x0d]	792	1			T6	2		T7	4		T19	1
valid_sources[0x0e]	1026	1			T6	2		T7	5		T20	6
valid_sources[0x0f]	2067	1			T6	1		T7	1		T1	3
valid_sources[0x10]	832	1			T7	4		T64	3		T50	3
valid_sources[0x11]	1692	1			T7	10		T19	1		T1	3
valid_sources[0x12]	1465	1			T7	1		T1	1		T4	2
valid_sources[0x13]	1007	1			T6	3		T7	2		T1	4
valid_sources[0x14]	1019	1			T6	1		T7	6		T1	4
valid_sources[0x15]	864	1			T7	1		T57	1		T50	10
valid_sources[0x16]	1861	1			T7	2		T1	2		T48	1
valid_sources[0x17]	1950	1			T6	1		T7	4		T1	8
valid_sources[0x18]	1184	1			T7	2		T1	1		T33	4
valid_sources[0x19]	890	1			T6	2		T7	2		T1	8
valid_sources[0x1a]	825	1			T6	6		T7	2		T1	4
valid_sources[0x1b]	895	1			T6	1		T7	3		T1	4
valid_sources[0x1c]	1016	1			T7	8		T1	3		T11	24
valid_sources[0x1d]	1025	1			T6	3		T7	2		T1	3
valid_sources[0x1e]	1081	1			T7	1		T1	6		T15	1
valid_sources[0x1f]	791	1			T6	5		T7	3		T1	1
valid_sources[0x20]	901	1			T6	2		T7	7		T1	1
valid_sources[0x21]	2979	1			T1	2		T15	1		T50	3
valid_sources[0x22]	2156	1			T7	4		T1	2		T57	2
valid_sources[0x23]	2950	1			T6	4		T7	5		T1	1
valid_sources[0x24]	942	1			T6	2		T7	4		T1	2
valid_sources[0x25]	925	1			T6	3		T7	2		T1	2
valid_sources[0x26]	1118	1			T7	2		T19	1		T21	10
valid_sources[0x27]	816	1			T6	6		T7	4		T11	1
valid_sources[0x28]	893	1			T6	8		T7	5		T1	2
valid_sources[0x29]	911	1			T6	3		T7	2		T1	4
valid_sources[0x2a]	1439	1			T7	1		T1	2		T50	6
valid_sources[0x2b]	935	1			T7	4		T1	5		T50	3
valid_sources[0x2c]	1011	1			T6	4		T7	9		T1	7
valid_sources[0x2d]	910	1			T7	7		T1	5		T5	2
valid_sources[0x2e]	1674	1			T7	1		T1	6		T4	1
valid_sources[0x2f]	939	1			T6	1		T7	2		T1	3
valid_sources[0x30]	793	1			T7	4		T1	4		T56	1
valid_sources[0x31]	1322	1			T7	4		T1	2		T4	1
valid_sources[0x32]	1075	1			T6	2		T7	1		T1	1
valid_sources[0x33]	805	1			T6	4		T7	3		T1	2
valid_sources[0x34]	923	1			T6	3		T7	3		T1	3
valid_sources[0x35]	985	1			T6	4		T7	5		T1	1
valid_sources[0x36]	894	1			T6	3		T7	4		T19	3
valid_sources[0x37]	1894	1			T6	7		T7	4		T1	2
valid_sources[0x38]	1469	1			T6	3		T7	3		T1	7
valid_sources[0x39]	1155	1			T6	5		T7	4		T1	2
valid_sources[0x3a]	1152	1			T6	1		T7	4		T21	6
valid_sources[0x3b]	878	1			T6	3		T7	1		T57	1
valid_sources[0x3c]	853	1			T7	2		T20	8		T1	4
valid_sources[0x3d]	889	1			T7	4		T1	2		T56	1
valid_sources[0x3e]	891	1			T6	4		T7	3		T20	5
valid_sources[0x3f]	866	1			T6	5		T7	3		T1	4
valid_sources[0x40]	1139	1			T6	1		T7	6		T1	4
valid_sources[0x41]	1043	1			T6	2		T7	3		T1	3
valid_sources[0x42]	864	1			T6	1		T7	5		T1	2
valid_sources[0x43]	822	1			T7	1		T1	6		T17	2
valid_sources[0x44]	1598	1			T6	3		T7	6		T1	5
valid_sources[0x45]	1083	1			T7	2		T1	8		T57	2
valid_sources[0x46]	788	1			T7	2		T20	14		T1	3
valid_sources[0x47]	838	1			T7	12		T1	1		T4	1
valid_sources[0x48]	1275	1			T7	3		T1	2		T17	1
valid_sources[0x49]	1086	1			T6	4		T7	2		T20	5
valid_sources[0x4a]	841	1			T6	4		T7	1		T1	2
valid_sources[0x4b]	1595	1			T7	4		T1	1		T4	1
valid_sources[0x4c]	851	1			T6	1		T7	3		T20	6
valid_sources[0x4d]	971	1			T6	4		T7	1		T1	10
valid_sources[0x4e]	875	1			T7	4		T1	2		T57	1
valid_sources[0x4f]	967	1			T1	7		T50	6		T33	1
valid_sources[0x50]	1036	1			T7	2		T1	2		T15	4
valid_sources[0x51]	770	1			T6	3		T7	3		T1	5
valid_sources[0x52]	1180	1			T6	7		T7	2		T1	7
valid_sources[0x53]	1064	1			T7	4		T1	3		T50	4
valid_sources[0x54]	1051	1			T6	1		T1	2		T48	2
valid_sources[0x55]	2233	1			T6	1		T7	2		T1	4
valid_sources[0x56]	797	1			T6	4		T7	2		T1	3
valid_sources[0x57]	943	1			T6	2		T7	4		T57	1
valid_sources[0x58]	965	1			T6	4		T7	3		T1	1
valid_sources[0x59]	893	1			T6	2		T7	2		T1	7
valid_sources[0x5a]	1882	1			T6	9		T7	4		T1	6
valid_sources[0x5b]	1088	1			T6	1		T7	1		T1	3
valid_sources[0x5c]	922	1			T7	2		T1	3		T12	3
valid_sources[0x5d]	891	1			T6	7		T7	2		T1	3
valid_sources[0x5e]	804	1			T6	2		T7	2		T1	1
valid_sources[0x5f]	933	1			T6	3		T7	2		T1	2
valid_sources[0x60]	791	1			T7	8		T1	5		T56	1
valid_sources[0x61]	836	1			T6	4		T7	7		T1	5
valid_sources[0x62]	1016	1			T6	1		T7	1		T1	5
valid_sources[0x63]	2134	1			T7	4		T1	11		T2	1203
valid_sources[0x64]	1005	1			T6	1		T7	5		T1	7
valid_sources[0x65]	1969	1			T6	4		T7	3		T1	2
valid_sources[0x66]	1386	1			T7	3		T19	2		T1	2
valid_sources[0x67]	1382	1			T6	4		T7	3		T1	5
valid_sources[0x68]	811	1			T6	1		T7	5		T19	1
valid_sources[0x69]	1881	1			T6	5		T7	6		T19	1
valid_sources[0x6a]	738	1			T6	3		T7	1		T1	4
valid_sources[0x6b]	930	1			T7	4		T1	2		T64	1
valid_sources[0x6c]	881	1			T6	2		T7	8		T1	2
valid_sources[0x6d]	827	1			T6	2		T7	6		T1	6
valid_sources[0x6e]	1348	1			T6	1		T7	1		T56	6
valid_sources[0x6f]	1151	1			T6	2		T7	8		T1	1
valid_sources[0x70]	852	1			T6	3		T7	1		T1	1
valid_sources[0x71]	960	1			T6	2		T7	3		T1	3
valid_sources[0x72]	922	1			T1	6		T11	2		T50	3
valid_sources[0x73]	1048	1			T6	3		T7	4		T1	8
valid_sources[0x74]	801	1			T6	1		T7	1		T1	2
valid_sources[0x75]	1322	1			T6	3		T7	7		T1	2
valid_sources[0x76]	1093	1			T6	1		T7	7		T1	1
valid_sources[0x77]	761	1			T6	1		T7	1		T1	4
valid_sources[0x78]	2014	1			T6	3		T7	2		T1	3
valid_sources[0x79]	1063	1			T7	6		T1	7		T57	1
valid_sources[0x7a]	1817	1			T7	3		T1	2		T50	2
valid_sources[0x7b]	864	1			T6	2		T7	4		T19	1
valid_sources[0x7c]	1028	1			T1	3		T56	1		T50	5
valid_sources[0x7d]	809	1			T7	2		T1	1		T17	1
valid_sources[0x7e]	851	1			T6	2		T7	2		T1	3
valid_sources[0x7f]	923	1			T6	2		T7	2		T1	2
valid_sources[0x80]	954	1			T6	1		T7	2		T1	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63935

1

T6

3

T7

129

T8

1

values[0x0]

all_enables

biggest_size

32629

1

T6

75

T7

93

T19

3

values[0x1]

all_enables

biggest_size

23034

1

T6

28

T7

40

T19

2