Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1305081212	11120	0	0
auto_block_debounce_ctl_rd_A	1305081212	1576	0	0
auto_block_out_ctl_rd_A	1305081212	2342	0	0
com_det_ctl_0_rd_A	1305081212	3094	0	0
com_det_ctl_1_rd_A	1305081212	3221	0	0
com_det_ctl_2_rd_A	1305081212	3162	0	0
com_det_ctl_3_rd_A	1305081212	3222	0	0
com_out_ctl_0_rd_A	1305081212	3846	0	0
com_out_ctl_1_rd_A	1305081212	3848	0	0
com_out_ctl_2_rd_A	1305081212	3671	0	0
com_out_ctl_3_rd_A	1305081212	3814	0	0
com_pre_det_ctl_0_rd_A	1305081212	987	0	0
com_pre_det_ctl_1_rd_A	1305081212	1025	0	0
com_pre_det_ctl_2_rd_A	1305081212	1052	0	0
com_pre_det_ctl_3_rd_A	1305081212	1099	0	0
com_pre_sel_ctl_0_rd_A	1305081212	3842	0	0
com_pre_sel_ctl_1_rd_A	1305081212	3874	0	0
com_pre_sel_ctl_2_rd_A	1305081212	3785	0	0
com_pre_sel_ctl_3_rd_A	1305081212	3863	0	0
com_sel_ctl_0_rd_A	1305081212	4119	0	0
com_sel_ctl_1_rd_A	1305081212	3854	0	0
com_sel_ctl_2_rd_A	1305081212	3841	0	0
com_sel_ctl_3_rd_A	1305081212	3720	0	0
ec_rst_ctl_rd_A	1305081212	2175	0	0
intr_enable_rd_A	1305081212	1768	0	0
key_intr_ctl_rd_A	1305081212	3685	0	0
key_intr_debounce_ctl_rd_A	1305081212	1045	0	0
key_invert_ctl_rd_A	1305081212	5803	0	0
pin_allowed_ctl_rd_A	1305081212	5783	0	0
pin_out_ctl_rd_A	1305081212	4099	0	0
pin_out_value_rd_A	1305081212	4007	0	0
regwen_rd_A	1305081212	1308	0	0
ulp_ac_debounce_ctl_rd_A	1305081212	1142	0	0
ulp_ctl_rd_A	1305081212	1114	0	0
ulp_lid_debounce_ctl_rd_A	1305081212	977	0	0
ulp_pwrb_debounce_ctl_rd_A	1305081212	1220	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	11120	0	0
T25	0	13	0	0
T32	0	16	0	0
T34	823968	0	0	0
T38	798133	4	0	0
T40	0	19	0	0
T41	280642	12	0	0
T43	0	9	0	0
T52	328197	0	0	0
T53	190971	0	0	0
T58	0	7	0	0
T81	0	10	0	0
T124	0	7	0	0
T198	241247	0	0	0
T199	243233	0	0	0
T200	102006	0	0	0
T201	130852	0	0	0
T202	192986	0	0	0
T329	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1576	0	0
T12	56527	0	0	0
T13	975703	7	0	0
T32	0	43	0	0
T48	354433	7	0	0
T49	19953	0	0	0
T50	140443	0	0	0
T51	0	11	0	0
T53	0	13	0	0
T64	150179	0	0	0
T65	247714	0	0	0
T66	39652	0	0	0
T68	63109	0	0	0
T86	201191	0	0	0
T110	0	8	0	0
T124	0	15	0	0
T189	0	18	0	0
T191	0	3	0	0
T330	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	2342	0	0
T12	56527	0	0	0
T13	975703	0	0	0
T32	0	40	0	0
T48	354433	7	0	0
T49	19953	0	0	0
T50	140443	0	0	0
T51	0	14	0	0
T53	0	15	0	0
T64	150179	0	0	0
T65	247714	0	0	0
T66	39652	0	0	0
T68	63109	0	0	0
T86	201191	0	0	0
T110	0	3	0	0
T124	0	16	0	0
T140	0	13	0	0
T189	0	30	0	0
T191	0	9	0	0
T330	0	8	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3094	0	0
T5	81347	0	0	0
T9	317619	60	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	60	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	33	0	0
T33	0	67	0	0
T36	0	19	0	0
T48	0	57	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	77	0	0
T124	0	7	0	0
T277	0	40	0	0
T331	0	77	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3221	0	0
T5	81347	0	0	0
T9	317619	56	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	38	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	34	0	0
T33	0	55	0	0
T36	0	32	0	0
T48	0	64	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	53	0	0
T124	0	9	0	0
T277	0	24	0	0
T331	0	58	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3162	0	0
T5	81347	0	0	0
T9	317619	63	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	30	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	33	0	0
T33	0	57	0	0
T36	0	40	0	0
T48	0	77	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	45	0	0
T124	0	10	0	0
T277	0	33	0	0
T331	0	63	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3222	0	0
T5	81347	0	0	0
T9	317619	67	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	52	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	38	0	0
T33	0	75	0	0
T36	0	29	0	0
T48	0	56	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	63	0	0
T124	0	3	0	0
T277	0	47	0	0
T331	0	58	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3846	0	0
T5	81347	0	0	0
T9	317619	62	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	31	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	23	0	0
T33	0	62	0	0
T36	0	16	0	0
T48	0	74	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	49	0	0
T124	0	2	0	0
T277	0	27	0	0
T331	0	65	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3848	0	0
T5	81347	0	0	0
T9	317619	49	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	34	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	29	0	0
T33	0	68	0	0
T36	0	42	0	0
T48	0	72	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	70	0	0
T124	0	26	0	0
T277	0	40	0	0
T331	0	65	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3671	0	0
T5	81347	0	0	0
T9	317619	59	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	44	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	35	0	0
T33	0	82	0	0
T36	0	22	0	0
T48	0	67	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	59	0	0
T277	0	33	0	0
T331	0	75	0	0
T332	0	56	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3814	0	0
T5	81347	0	0	0
T9	317619	55	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	47	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	34	0	0
T33	0	55	0	0
T36	0	37	0	0
T48	0	53	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	62	0	0
T124	0	7	0	0
T277	0	31	0	0
T331	0	53	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	987	0	0
T32	454130	28	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	18	0	0
T121	0	31	0	0
T124	0	20	0	0
T127	0	4	0	0
T131	48898	0	0	0
T142	0	17	0	0
T164	0	12	0	0
T189	0	11	0	0
T242	0	10	0	0
T290	0	5	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1025	0	0
T32	454130	38	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	8	0	0
T121	0	31	0	0
T124	0	14	0	0
T127	0	14	0	0
T131	48898	0	0	0
T142	0	13	0	0
T164	0	5	0	0
T189	0	11	0	0
T242	0	9	0	0
T290	0	15	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1052	0	0
T32	454130	38	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	16	0	0
T121	0	27	0	0
T124	0	16	0	0
T127	0	7	0	0
T131	48898	0	0	0
T142	0	8	0	0
T164	0	15	0	0
T189	0	13	0	0
T242	0	24	0	0
T290	0	14	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1099	0	0
T32	454130	39	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	14	0	0
T121	0	24	0	0
T124	0	6	0	0
T127	0	22	0	0
T131	48898	0	0	0
T142	0	10	0	0
T164	0	11	0	0
T189	0	11	0	0
T242	0	17	0	0
T290	0	5	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3842	0	0
T5	81347	0	0	0
T9	317619	60	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	39	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	54	0	0
T33	0	70	0	0
T36	0	30	0	0
T48	0	47	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	69	0	0
T124	0	6	0	0
T277	0	42	0	0
T331	0	85	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3874	0	0
T5	81347	0	0	0
T9	317619	55	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	47	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	22	0	0
T33	0	85	0	0
T36	0	33	0	0
T48	0	62	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	65	0	0
T124	0	8	0	0
T277	0	37	0	0
T331	0	39	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3785	0	0
T5	81347	0	0	0
T9	317619	55	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	21	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	30	0	0
T33	0	79	0	0
T36	0	19	0	0
T48	0	75	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	60	0	0
T124	0	14	0	0
T277	0	29	0	0
T331	0	79	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3863	0	0
T5	81347	0	0	0
T9	317619	69	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	46	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	15	0	0
T33	0	66	0	0
T36	0	29	0	0
T48	0	79	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	89	0	0
T124	0	5	0	0
T277	0	25	0	0
T331	0	65	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	4119	0	0
T5	81347	0	0	0
T9	317619	51	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	57	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	28	0	0
T33	0	76	0	0
T36	0	37	0	0
T48	0	62	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	63	0	0
T124	0	1	0	0
T277	0	36	0	0
T331	0	86	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3854	0	0
T5	81347	0	0	0
T9	317619	31	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	33	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	20	0	0
T33	0	79	0	0
T36	0	39	0	0
T48	0	61	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	49	0	0
T124	0	3	0	0
T277	0	27	0	0
T331	0	77	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3841	0	0
T5	81347	0	0	0
T9	317619	58	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	30	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	24	0	0
T33	0	67	0	0
T36	0	35	0	0
T48	0	77	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	66	0	0
T124	0	24	0	0
T277	0	36	0	0
T331	0	72	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3720	0	0
T5	81347	0	0	0
T9	317619	66	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	51	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	35	0	0
T33	0	80	0	0
T36	0	16	0	0
T48	0	66	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	83	0	0
T124	0	5	0	0
T277	0	41	0	0
T331	0	88	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	2175	0	0
T5	81347	0	0	0
T9	317619	26	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T13	0	2	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	39	0	0
T33	0	11	0	0
T36	0	12	0	0
T48	0	2	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T89	0	27	0	0
T124	0	25	0	0
T134	0	7	0	0
T337	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1768	0	0
T32	454130	32	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T124	0	3	0	0
T127	0	14	0	0
T131	48898	0	0	0
T140	0	8	0	0
T142	0	30	0	0
T164	0	52	0	0
T189	0	45	0	0
T290	0	5	0	0
T322	0	5	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0
T338	0	3	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	3685	0	0
T3	55318	5	0	0
T4	66894	0	0	0
T5	81347	2	0	0
T9	317619	0	0	0
T10	331916	0	0	0
T16	65685	0	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	35	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T83	0	8	0	0
T138	0	7	0	0
T140	0	6	0	0
T149	0	3	0	0
T154	0	9	0	0
T170	0	4	0	0
T189	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1045	0	0
T32	454130	53	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	25	0	0
T121	0	35	0	0
T124	0	13	0	0
T127	0	6	0	0
T131	48898	0	0	0
T142	0	12	0	0
T164	0	14	0	0
T189	0	6	0	0
T242	0	14	0	0
T290	0	6	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	5803	0	0
T3	55318	0	0	0
T4	66894	0	0	0
T5	81347	0	0	0
T9	317619	0	0	0
T13	0	56	0	0
T15	234881	55	0	0
T16	65685	0	0	0
T17	42048	30	0	0
T18	21580	0	0	0
T32	0	30	0	0
T48	0	61	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T65	0	65	0	0
T66	0	74	0	0
T124	0	17	0	0
T331	0	143	0	0
T339	0	61	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	5783	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T12	56527	0	0	0
T32	0	19	0	0
T48	354433	0	0	0
T55	250957	57	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T68	63109	0	0	0
T86	201191	0	0	0
T124	0	8	0	0
T158	0	83	0	0
T164	0	13	0	0
T189	0	46	0	0
T198	0	72	0	0
T340	0	91	0	0
T341	0	32	0	0
T342	0	101	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	4099	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T12	56527	0	0	0
T32	0	27	0	0
T48	354433	0	0	0
T55	250957	56	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T68	63109	0	0	0
T86	201191	0	0	0
T124	0	10	0	0
T158	0	64	0	0
T164	0	8	0	0
T189	0	63	0	0
T198	0	74	0	0
T340	0	72	0	0
T341	0	37	0	0
T342	0	51	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	4007	0	0
T10	331916	0	0	0
T11	336970	0	0	0
T12	56527	0	0	0
T32	0	27	0	0
T48	354433	0	0	0
T55	250957	68	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T63	66538	0	0	0
T68	63109	0	0	0
T86	201191	0	0	0
T124	0	20	0	0
T158	0	83	0	0
T164	0	2	0	0
T189	0	25	0	0
T198	0	60	0	0
T340	0	57	0	0
T341	0	36	0	0
T342	0	87	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1308	0	0
T32	454130	29	0	0
T37	215584	0	0	0
T39	283053	0	0	0
T59	122494	0	0	0
T60	162860	0	0	0
T85	0	18	0	0
T121	0	31	0	0
T124	0	10	0	0
T127	0	20	0	0
T131	48898	0	0	0
T142	0	9	0	0
T164	0	9	0	0
T189	0	6	0	0
T242	0	20	0	0
T290	0	11	0	0
T333	50918	0	0	0
T334	128566	0	0	0
T335	485801	0	0	0
T336	206249	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1142	0	0
T4	66894	6	0	0
T5	81347	0	0	0
T9	317619	0	0	0
T10	331916	0	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	41	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T61	0	14	0	0
T63	66538	0	0	0
T103	0	3	0	0
T124	0	18	0	0
T125	0	11	0	0
T127	0	21	0	0
T157	0	5	0	0
T164	0	11	0	0
T189	0	22	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1114	0	0
T4	66894	8	0	0
T5	81347	0	0	0
T9	317619	0	0	0
T10	331916	0	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	43	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T61	0	3	0	0
T63	66538	0	0	0
T103	0	1	0	0
T124	0	3	0	0
T125	0	4	0	0
T157	0	7	0	0
T164	0	13	0	0
T189	0	30	0	0
T343	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	977	0	0
T4	66894	4	0	0
T5	81347	0	0	0
T9	317619	0	0	0
T10	331916	0	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	36	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T61	0	10	0	0
T63	66538	0	0	0
T103	0	12	0	0
T124	0	7	0	0
T125	0	4	0	0
T157	0	4	0	0
T164	0	1	0	0
T189	0	4	0	0
T343	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305081212	1220	0	0
T4	66894	11	0	0
T5	81347	0	0	0
T9	317619	0	0	0
T10	331916	0	0	0
T17	42048	0	0	0
T18	21580	0	0	0
T32	0	15	0	0
T55	250957	0	0	0
T56	216905	0	0	0
T57	58462	0	0	0
T61	0	8	0	0
T63	66538	0	0	0
T103	0	4	0	0
T124	0	9	0	0
T125	0	9	0	0
T157	0	3	0	0
T164	0	7	0	0
T189	0	21	0	0
T343	0	6	0	0