Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1923

1

T1

13

T2

4

T15

18

auto[1]

653

1

T1

4

T15

18

T5

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1847

1

T1

4

T2

4

T15

27

auto[1]

729

1

T1

13

T15

9

T17

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T1

15

T2

4

T15

36

auto[1]

604

1

T1

2

T6

4

T10

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T1

16

T2

3

T15

18

auto[1]

641

1

T1

1

T2

1

T15

18

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2297

1

T1

17

T2

3

T15

36

auto[1]

279

1

T2

1

T17

1

T5

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2412

1

T1

17

T2

4

T15

36

auto[1]

164

1

T206

8

T96

5

T222

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2413

1

T1

17

T2

4

T15

36

auto[1]

163

1

T5

1

T63

5

T45

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2286

1

T1

17

T2

4

T15

36

auto[1]

290

1

T5

2

T10

3

T30

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2285

1

T1

17

T2

4

T15

18

auto[1]

291

1

T15

18

T5

2

T30

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T1

13

T2

3

T15

36

auto[1]

624

1

T1

4

T2

1

T17

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	834	1			T1	17		T6	5		T11	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	87	1			T2	1		T17	1		T5	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	106	1			T15	18		T103	1		T223	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	42	1			T30	3		T78	1		T96	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	100	1			T10	3		T45	4		T333	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	63	1			T30	5		T96	3		T324	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	29	1			T5	2		T314	10		T334	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	7	1			T223	1		T324	4		T335	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	52	1			T5	1		T126	1		T336	7
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T222	2		T334	5		T337	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T323	1		T338	3		T339	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T323	1		T340	4		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	29	1			T45	3		T341	2		T324	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T147	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T45	2		T341	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	45	1			T222	2		T223	2		T337	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	14	1			T206	3		T342	2		T147	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T336	6		T341	2		T338	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T206	3		T324	4		T327	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	10	1			T206	2		T96	3		T343	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T344	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	15	1			T314	8		T334	1		T130	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T334	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	9	1			T199	1		T345	2		T237	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T314	4		T343	1		T335	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T346	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T96	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

140

1

T11

11

T45

4

T323

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

68

1

T30

5

T234

11

T131

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

74

1

T1

3

T45

3

T29

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

129

1

T5

1

T206

3

T190

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T15

9

T239

2

T347

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T2

1

T47

1

T51

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T29

1

T277

4

T238

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

66

1

T206

3

T190

3

T314

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T238

6

T126

2

T130

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T10

3

T79

6

T313

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T1

1

T11

3

T96

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

75

1

T29

1

T47

1

T312

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T190

1

T82

1

T319

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T348

1

T320

2

T349

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T11

2

T222

2

T277

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

99

1

T1

12

T45

4

T96

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

85

1

T5

2

T45

2

T58

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

108

1

T17

1

T94

6

T225

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T243

1

T192

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T5

4

T10

6

T47

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

55

1

T15

9

T29

2

T336

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T225

2

T232

2

T323

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T6

1

T69

1

T70

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T223

1

T69

1

T291

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T6

3

T225

4

T79

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T29

5

T131

4

T84

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T6

1

T29

1

T350

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T1

1

T30

3

T78

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T103

1

T351

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T94

2

T47

1

T312

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T114

1

T352

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded