Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1227

1

T24

11

T59

10

T60

13

auto[1]

1185

1

T24

9

T59

10

T60

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T24

7

T59

6

T60

3

from_0to1

572

1

T24

6

T59

6

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1240

1

T24

9

T59

11

T60

11

auto[1]

1172

1

T24

11

T59

9

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1209

1

T24

10

T59

9

T60

11

auto[1]

1203

1

T24

10

T59

11

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

85

1

T59

1

T47

5

T50

2

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T24

3

T59

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T60

1

T47

3

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T24

1

T59

1

T33

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T24

1

T33

1

T172

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T59

2

T47

1

T51

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T24

2

T33

1

T47

2

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T24

1

T59

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T60

2

T51

1

T190

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T24

1

T59

2

T33

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T59

1

T33

1

T172

2

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T24

2

T172

2

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T24

1

T59

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T59

1

T60

1

T172

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T24

1

T59

1

T47

4

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T172

1

T47

3

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1198

1

T24

3

T59

15

T60

7

auto[1]

1214

1

T24

17

T59

5

T60

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T24

7

T59

4

T60

7

from_0to1

574

1

T24

6

T59

5

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T24

8

T59

8

T60

11

auto[1]

1206

1

T24

12

T59

12

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T24

11

T59

8

T60

12

auto[1]

1232

1

T24

9

T59

12

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T24

1

T59

2

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T59

1

T172

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T172

1

T47

2

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T24

1

T33

1

T172

1

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T60

2

T33

1

T47

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T59

1

T60

1

T47

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T59

3

T47

4

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T51

2

T360

2

T190

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T60

1

T33

1

T47

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T24

1

T60

1

T33

1

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T24

2

T60

1

T47

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T24

2

T59

1

T60

3

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T24

3

T172

2

T47

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T24

1

T60

1

T172

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T24

2

T59

1

T60

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T33

1

T47

2

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T24

9

T59

10

T60

7

auto[1]

1205

1

T24

11

T59

10

T60

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

592

1

T24

3

T59

5

T60

5

from_0to1

587

1

T24

4

T59

5

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1216

1

T24

9

T59

12

T60

15

auto[1]

1196

1

T24

11

T59

8

T60

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1188

1

T24

9

T59

11

T60

13

auto[1]

1224

1

T24

11

T59

9

T60

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T59

2

T33

1

T172

1

auto[0]

from_1to0

auto[0]

auto[1]

86

1

T24

2

T33

1

T51

2

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T60

2

T33

1

T172

1

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T47

4

T50

1

T51

2

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T59

2

T60

1

T172

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T59

1

T60

1

T172

1

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T24

1

T33

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T33

1

T172

2

T47

5

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T24

1

T59

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T60

2

T33

2

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T59

1

T172

1

T47

3

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T59

1

T172

2

T50

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T60

2

T33

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T24

2

T59

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T60

1

T33

1

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T24

1

T33

1

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T24

10

T59

12

T60

8

auto[1]

1242

1

T24

10

T59

8

T60

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

579

1

T24

4

T59

6

T60

5

from_0to1

586

1

T24

5

T59

6

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T24

8

T59

12

T60

9

auto[1]

1200

1

T24

12

T59

8

T60

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T24

11

T59

11

T60

10

auto[1]

1206

1

T24

9

T59

9

T60

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T24

1

T172

1

T47

3

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T59

2

T33

2

T172

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T24

1

T59

1

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T24

1

T59

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

83

1

T24

2

T60

2

T47

4

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T59

1

T172

1

T190

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T24

1

T59

2

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T59

1

T172

1

T47

5

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T59

2

T172

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T33

1

T47

2

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T24

1

T60

2

T172

1

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T60

2

T172

1

T47

7

auto[1]

from_0to1

auto[0]

auto[0]

85

1

T59

1

T60

2

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T47

2

T51

1

T190

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T172

1

T50

2

T51

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T24

2

T59

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1230

1

T24

12

T59

11

T60

7

auto[1]

1182

1

T24

8

T59

9

T60

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

584

1

T24

5

T59

5

T60

4

from_0to1

578

1

T24

6

T59

4

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1221

1

T24

11

T59

11

T60

11

auto[1]

1191

1

T24

9

T59

9

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1244

1

T24

9

T59

10

T60

6

auto[1]

1168

1

T24

11

T59

10

T60

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T24

2

T172

1

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T33

2

T47

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T24

3

T59

1

T33

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T60

1

T47

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T59

1

T172

1

T47

2

auto[0]

from_0to1

auto[0]

auto[1]

88

1

T59

1

T60

1

T172

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T47

2

T50

1

T51

2

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T59

1

T60

1

T33

2

auto[1]

from_1to0

auto[0]

auto[0]

96

1

T172

1

T47

2

T50

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T59

2

T60

2

T33

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T33

1

T47

2

T50

3

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T59

2

T60

1

T172

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T33

1

T47

3

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T24

4

T59

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T33

1

T47

3

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T24

2

T33

1

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1214

1

T24

7

T59

10

T60

12

auto[1]

1198

1

T24

13

T59

10

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

576

1

T24

4

T59

4

T60

5

from_0to1

580

1

T24

3

T59

5

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1219

1

T24

12

T59

13

T60

11

auto[1]

1193

1

T24

8

T59

7

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T24

12

T59

10

T60

12

auto[1]

1205

1

T24

8

T59

10

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T24

1

T59

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T59

1

T60

1

T33

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T60

1

T33

2

T47

4

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T24

1

T47

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T172

1

T47

2

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

89

1

T59

3

T60

1

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T60

1

T47

2

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T33

2

T50

4

T51

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T59

1

T47

3

T51

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T24

1

T60

1

T172

2

auto[1]

from_1to0

auto[1]

auto[0]

83

1

T24

1

T59

1

T172

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T60

1

T33

1

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T24

1

T59

2

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T24

2

T33

1

T47

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T172

1

T47

2

T51

3

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T60

1

T47

4

T50

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T24

9

T59

14

T60

4

auto[1]

1232

1

T24

11

T59

6

T60

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

575

1

T24

4

T59

5

T60

7

from_0to1

574

1

T24

4

T59

4

T60

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1214

1

T24

9

T59

9

T60

8

auto[1]

1198

1

T24

11

T59

11

T60

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T24

3

T59

8

T60

9

auto[1]

1206

1

T24

17

T59

12

T60

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T24

1

T59

1

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T59

1

T60

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T24

1

T60

2

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T24

1

T59

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T172

1

T47

2

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T24

1

T59

1

T172

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T59

1

T47

1

T51

3

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T59

1

T47

1

T50

2

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T59

1

T60

1

T47

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T59

1

T47

5

T51

5

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T60

1

T33

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T24

1

T60

1

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T60

1

T33

2

T172

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T24

2

T60

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

91

1

T60

1

T33

1

T47

3

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T24

1

T59

1

T60

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1219

1

T24

13

T59

13

T60

10

auto[1]

1193

1

T24

7

T59

7

T60

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

578

1

T24

4

T59

5

T60

5

from_0to1

575

1

T24

4

T59

5

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T24

9

T59

8

T60

12

auto[1]

1212

1

T24

11

T59

12

T60

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T24

9

T59

9

T60

8

auto[1]

1245

1

T24

11

T59

11

T60

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T24

1

T60

1

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T24

1

T59

2

T33

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T60

1

T33

2

T172

3

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T24

1

T59

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T24

1

T59

1

T33

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T60

1

T172

1

T47

4

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T24

1

T33

1

T172

1

auto[0]

from_0to1

auto[1]

auto[1]

88

1

T59

2

T33

1

T47

3

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T59

1

T47

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T60

1

T33

3

T47

3

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T59

1

T33

1

T172

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T24

1

T60

1

T172

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T60

2

T172

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T24

1

T59

1

T60

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T24

1

T33

2

T172

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T59

1

T33

1

T172

2