Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125676

1

T1

550

T2

280

T4

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	148837	1			T1	830		T2	215		T4	2
values[0x0]	69569	1			T1	146		T2	304		T4	25
values[0x1]	70460	1			T1	172		T2	328		T4	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156676

1

T1

660

T2

352

T4

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1078	1			T2	19		T5	7		T37	3
valid_sources[0x01]	1386	1			T15	1		T17	12		T5	1
valid_sources[0x02]	3526	1			T15	1		T17	3		T5	1
valid_sources[0x03]	1016	1			T13	8		T15	5		T17	7
valid_sources[0x04]	960	1			T15	3		T37	1		T11	5
valid_sources[0x05]	848	1			T2	6		T15	5		T5	7
valid_sources[0x06]	1503	1			T15	2		T17	24		T5	1
valid_sources[0x07]	980	1			T2	17		T15	12		T17	10
valid_sources[0x08]	848	1			T15	6		T17	1		T5	1
valid_sources[0x09]	1278	1			T2	18		T4	2		T15	3
valid_sources[0x0a]	1060	1			T15	4		T37	1		T6	8
valid_sources[0x0b]	1006	1			T14	44		T15	2		T17	4
valid_sources[0x0c]	1015	1			T15	2		T5	2		T37	1
valid_sources[0x0d]	935	1			T2	4		T15	7		T17	12
valid_sources[0x0e]	1096	1			T2	1		T5	2		T37	1
valid_sources[0x0f]	973	1			T2	3		T15	8		T37	2
valid_sources[0x10]	798	1			T4	3		T15	2		T17	23
valid_sources[0x11]	2467	1			T2	5		T15	3		T17	4
valid_sources[0x12]	1340	1			T15	2		T5	3		T37	5
valid_sources[0x13]	1922	1			T15	13		T17	7		T5	1
valid_sources[0x14]	850	1			T17	1		T5	1		T37	1
valid_sources[0x15]	902	1			T2	14		T17	1		T5	2
valid_sources[0x16]	1696	1			T2	1		T15	5		T5	1
valid_sources[0x17]	1001	1			T2	16		T15	2		T6	1
valid_sources[0x18]	845	1			T15	4		T37	4		T6	1
valid_sources[0x19]	1005	1			T15	6		T17	2		T5	7
valid_sources[0x1a]	1116	1			T2	16		T15	8		T5	8
valid_sources[0x1b]	1881	1			T15	1		T11	2		T30	12
valid_sources[0x1c]	910	1			T5	5		T37	1		T6	1
valid_sources[0x1d]	1031	1			T15	9		T17	9		T5	3
valid_sources[0x1e]	872	1			T15	4		T5	3		T37	1
valid_sources[0x1f]	1067	1			T15	6		T5	3		T37	3
valid_sources[0x20]	733	1			T15	3		T37	1		T91	2
valid_sources[0x21]	974	1			T17	8		T37	2		T11	1
valid_sources[0x22]	852	1			T15	1		T17	7		T5	1
valid_sources[0x23]	1237	1			T13	7		T15	1		T5	3
valid_sources[0x24]	910	1			T13	3		T15	1		T17	11
valid_sources[0x25]	943	1			T2	2		T4	3		T13	10
valid_sources[0x26]	918	1			T15	5		T17	4		T5	3
valid_sources[0x27]	893	1			T15	4		T37	1		T8	22
valid_sources[0x28]	1008	1			T4	5		T15	3		T5	3
valid_sources[0x29]	996	1			T2	1		T15	10		T5	2
valid_sources[0x2a]	1154	1			T15	6		T5	5		T37	1
valid_sources[0x2b]	1072	1			T2	4		T15	3		T17	9
valid_sources[0x2c]	1793	1			T5	3		T37	4		T6	2
valid_sources[0x2d]	1044	1			T15	2		T17	3		T5	3
valid_sources[0x2e]	911	1			T4	1		T15	4		T17	11
valid_sources[0x2f]	855	1			T15	3		T17	7		T5	11
valid_sources[0x30]	1640	1			T15	3		T17	3		T37	1
valid_sources[0x31]	1830	1			T17	18		T5	1		T37	1
valid_sources[0x32]	958	1			T5	5		T37	2		T11	2
valid_sources[0x33]	1163	1			T2	12		T15	12		T5	4
valid_sources[0x34]	878	1			T2	8		T15	5		T5	1
valid_sources[0x35]	1067	1			T1	67		T15	4		T5	12
valid_sources[0x36]	909	1			T15	5		T17	19		T37	3
valid_sources[0x37]	1329	1			T15	4		T5	6		T37	2
valid_sources[0x38]	858	1			T15	2		T5	1		T37	3
valid_sources[0x39]	1109	1			T15	5		T5	5		T37	2
valid_sources[0x3a]	1118	1			T15	6		T5	9		T37	3
valid_sources[0x3b]	950	1			T1	1		T15	8		T37	1
valid_sources[0x3c]	979	1			T15	1		T5	4		T37	1
valid_sources[0x3d]	1344	1			T15	4		T5	1		T36	2
valid_sources[0x3e]	1868	1			T15	5		T17	9		T5	4
valid_sources[0x3f]	925	1			T1	29		T2	45		T15	1
valid_sources[0x40]	1162	1			T15	9		T17	2		T5	6
valid_sources[0x41]	907	1			T15	1		T37	2		T91	1
valid_sources[0x42]	890	1			T1	20		T15	5		T37	4
valid_sources[0x43]	816	1			T15	6		T17	3		T5	5
valid_sources[0x44]	2420	1			T2	21		T15	4		T17	11
valid_sources[0x45]	871	1			T1	1		T17	1		T37	1
valid_sources[0x46]	1137	1			T13	2		T15	2		T46	1
valid_sources[0x47]	1087	1			T15	13		T6	5		T11	2
valid_sources[0x48]	774	1			T2	8		T15	2		T5	6
valid_sources[0x49]	1557	1			T15	2		T5	11		T37	3
valid_sources[0x4a]	1778	1			T2	5		T5	13		T37	2
valid_sources[0x4b]	840	1			T15	2		T17	1		T6	7
valid_sources[0x4c]	984	1			T2	36		T5	6		T37	5
valid_sources[0x4d]	1148	1			T2	5		T4	1		T15	4
valid_sources[0x4e]	1489	1			T1	20		T15	5		T17	12
valid_sources[0x4f]	854	1			T15	7		T5	3		T37	3
valid_sources[0x50]	883	1			T15	4		T17	1		T37	3
valid_sources[0x51]	1950	1			T2	10		T15	3		T35	1
valid_sources[0x52]	1066	1			T15	5		T17	12		T37	1
valid_sources[0x53]	1041	1			T2	20		T15	9		T17	2
valid_sources[0x54]	741	1			T2	21		T15	7		T17	8
valid_sources[0x55]	910	1			T15	3		T17	8		T37	2
valid_sources[0x56]	1135	1			T15	4		T17	4		T46	2
valid_sources[0x57]	1204	1			T15	7		T5	3		T37	1
valid_sources[0x58]	1043	1			T15	2		T5	4		T37	2
valid_sources[0x59]	945	1			T15	2		T5	4		T37	4
valid_sources[0x5a]	1166	1			T4	1		T15	8		T17	4
valid_sources[0x5b]	1918	1			T2	30		T13	8		T15	5
valid_sources[0x5c]	1011	1			T15	6		T5	2		T37	1
valid_sources[0x5d]	1549	1			T15	1		T5	2		T6	1
valid_sources[0x5e]	1236	1			T15	6		T5	2		T37	3
valid_sources[0x5f]	961	1			T2	11		T13	1		T17	1
valid_sources[0x60]	2220	1			T15	2		T5	2		T37	1
valid_sources[0x61]	1045	1			T1	3		T15	1		T5	11
valid_sources[0x62]	2031	1			T2	6		T15	1		T17	5
valid_sources[0x63]	1329	1			T15	13		T17	2		T5	11
valid_sources[0x64]	921	1			T15	4		T5	1		T36	2
valid_sources[0x65]	1388	1			T13	2		T15	4		T5	4
valid_sources[0x66]	702	1			T2	17		T4	1		T15	2
valid_sources[0x67]	781	1			T15	1		T5	2		T36	1
valid_sources[0x68]	1334	1			T5	2		T37	1		T11	6
valid_sources[0x69]	1281	1			T1	255		T15	6		T17	5
valid_sources[0x6a]	1051	1			T35	6		T5	1		T6	1
valid_sources[0x6b]	1010	1			T1	20		T2	1		T15	4
valid_sources[0x6c]	1061	1			T15	4		T3	28		T17	2
valid_sources[0x6d]	937	1			T15	5		T17	28		T37	1
valid_sources[0x6e]	895	1			T15	2		T17	1		T5	2
valid_sources[0x6f]	1022	1			T2	7		T15	2		T5	4
valid_sources[0x70]	893	1			T4	1		T15	2		T17	3
valid_sources[0x71]	997	1			T2	7		T15	3		T5	14
valid_sources[0x72]	1724	1			T15	1		T5	8		T37	2
valid_sources[0x73]	1152	1			T13	1		T5	9		T37	2
valid_sources[0x74]	1646	1			T15	14		T5	16		T37	1
valid_sources[0x75]	768	1			T15	7		T17	7		T5	7
valid_sources[0x76]	1100	1			T15	5		T5	8		T37	3
valid_sources[0x77]	1105	1			T2	7		T4	6		T15	3
valid_sources[0x78]	821	1			T15	1		T17	1		T37	2
valid_sources[0x79]	905	1			T15	3		T5	9		T37	2
valid_sources[0x7a]	1537	1			T15	5		T5	1		T37	2
valid_sources[0x7b]	884	1			T1	2		T2	5		T15	2
valid_sources[0x7c]	1256	1			T15	6		T37	1		T6	2
valid_sources[0x7d]	1002	1			T2	26		T15	5		T5	2
valid_sources[0x7e]	1059	1			T4	5		T15	6		T17	2
valid_sources[0x7f]	1760	1			T2	13		T15	10		T5	4
valid_sources[0x80]	1170	1			T15	3		T5	5		T37	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67327

1

T1

434

T2

107

T4

2

values[0x0]

all_enables

biggest_size

34071

1

T1

62

T2

103

T4

6

values[0x1]

all_enables

biggest_size

24278

1

T1

54

T2

70

T4

11