Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T26,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T26,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T26,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T35
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T26,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T35
0	1	Covered	T26,T68,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T35
0	1	Covered	T1,T26,T35
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T26,T35
1	-	Covered	T1,T26,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T35
DetectSt	168	Covered	T1,T26,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T26,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T26,T35
DebounceSt->IdleSt	163	Covered	T26,T35,T42
DetectSt->IdleSt	186	Covered	T26,T68,T80
DetectSt->StableSt	191	Covered	T1,T26,T35
IdleSt->DebounceSt	148	Covered	T1,T26,T35
StableSt->IdleSt	206	Covered	T1,T26,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T35
0	1	Covered	T1,T26,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T26,T35
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T26,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T35,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T35
DetectSt	-	-	-	-	1	-	-	Covered	T26,T68,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T26,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T26,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T26,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	284	0	0
CntIncr_A	9556404	242321	0	0
CntNoWrap_A	9556404	8886418	0	0
DetectStDropOut_A	9556404	6	0	0
DetectedOut_A	9556404	878	0	0
DetectedPulseOut_A	9556404	123	0	0
DisabledIdleSt_A	9556404	8637612	0	0
DisabledNoDetection_A	9556404	8639970	0	0
EnterDebounceSt_A	9556404	160	0	0
EnterDetectSt_A	9556404	129	0	0
EnterStableSt_A	9556404	123	0	0
PulseIsPulse_A	9556404	123	0	0
StayInStableSt	9556404	755	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	7202	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	284	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T26	0	5	0	0
T35	0	3	0	0
T36	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	0	1	0	0
T47	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	242321	0	0
T1	21977	60	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	40	0	0
T26	0	139	0	0
T35	0	118	0	0
T36	0	112	0	0
T40	0	42	0	0
T41	0	44	0	0
T42	0	161	0	0
T43	0	8	0	0
T47	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886418	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6	0	0
T5	19188	0	0	0
T6	15542	0	0	0
T7	718	0	0	0
T26	656	1	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T38	434	0	0	0
T46	103706	0	0	0
T68	0	1	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	409	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	878	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T26	0	4	0	0
T35	0	11	0	0
T36	0	22	0	0
T40	0	13	0	0
T41	0	8	0	0
T42	0	13	0	0
T47	0	2	0	0
T50	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	123	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8637612	0	0
T1	21977	13581	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8639970	0	0
T1	21977	13604	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	160	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	3	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	129	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	123	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	123	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	755	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T26	0	3	0	0
T35	0	10	0	0
T36	0	20	0	0
T40	0	12	0	0
T41	0	7	0	0
T42	0	11	0	0
T47	0	1	0	0
T50	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	7202	0	0
T1	21977	44	0	0
T2	9174	24	0	0
T3	160979	8	0	0
T4	521	7	0	0
T12	435	2	0	0
T13	523	5	0	0
T14	454	6	0	0
T15	24026	24	0	0
T16	719	3	0	0
T17	10947	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	122	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T47
0	1	Covered	T1,T51,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T47
0	1	Unreachable
1	0	Covered	T3,T24,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T24
DetectSt	168	Covered	T1,T3,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T24,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T24
DebounceSt->IdleSt	163	Covered	T43,T49,T51
DetectSt->IdleSt	186	Covered	T1,T51,T74
DetectSt->StableSt	191	Covered	T3,T24,T47
IdleSt->DebounceSt	148	Covered	T1,T3,T24
StableSt->IdleSt	206	Covered	T3,T24,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T24
0	1	Covered	T1,T3,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T51,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T1,T51,T74
DetectSt	-	-	-	-	0	1	-	Covered	T3,T24,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T24,T47
StableSt	-	-	-	-	-	-	0	Covered	T3,T24,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	166	0	0
CntIncr_A	9556404	307850	0	0
CntNoWrap_A	9556404	8886536	0	0
DetectStDropOut_A	9556404	9	0	0
DetectedOut_A	9556404	847498	0	0
DetectedPulseOut_A	9556404	49	0	0
DisabledIdleSt_A	9556404	6602145	0	0
DisabledNoDetection_A	9556404	6604559	0	0
EnterDebounceSt_A	9556404	110	0	0
EnterDetectSt_A	9556404	58	0	0
EnterStableSt_A	9556404	49	0	0
PulseIsPulse_A	9556404	49	0	0
StayInStableSt	9556404	847449	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	7202	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_sticky_sva.StableStDropOut_A	9556404	373018	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	166	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	2	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T43	0	1	0	0
T47	0	2	0	0
T49	0	12	0	0
T50	0	2	0	0
T51	0	11	0	0
T64	0	6	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	307850	0	0
T1	21977	22	0	0
T2	9174	0	0	0
T3	160979	33	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	42	0	0
T43	0	83	0	0
T47	0	33	0	0
T49	0	960	0	0
T50	0	19	0	0
T51	0	75771	0	0
T64	0	188	0	0
T65	0	42755	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886536	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160576	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	9	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T51	0	4	0	0
T74	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	847498	0	0
T3	160979	152	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	265	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	92	0	0
T50	0	90	0	0
T51	0	127	0	0
T64	0	319	0	0
T65	0	204604	0	0
T70	0	199	0	0
T91	409	0	0	0
T97	0	601	0	0
T98	0	191	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	49	0	0
T3	160979	1	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T70	0	1	0	0
T91	409	0	0	0
T97	0	2	0	0
T98	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6602145	0	0
T1	21977	13594	0	0
T2	9174	8765	0	0
T3	160979	100343	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6604559	0	0
T1	21977	13618	0	0
T2	9174	8767	0	0
T3	160979	100344	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	110	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	1	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T49	0	12	0	0
T50	0	1	0	0
T51	0	6	0	0
T64	0	5	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	58	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	1	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	5	0	0
T64	0	1	0	0
T65	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	49	0	0
T3	160979	1	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T70	0	1	0	0
T91	409	0	0	0
T97	0	2	0	0
T98	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	49	0	0
T3	160979	1	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T70	0	1	0	0
T91	409	0	0	0
T97	0	2	0	0
T98	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	847449	0	0
T3	160979	151	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	264	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	91	0	0
T50	0	89	0	0
T51	0	126	0	0
T64	0	318	0	0
T65	0	204603	0	0
T70	0	198	0	0
T91	409	0	0	0
T97	0	599	0	0
T98	0	190	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	7202	0	0
T1	21977	44	0	0
T2	9174	24	0	0
T3	160979	8	0	0
T4	521	7	0	0
T12	435	2	0	0
T13	523	5	0	0
T14	454	6	0	0
T15	24026	24	0	0
T16	719	3	0	0
T17	10947	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	373018	0	0
T3	160979	60024	0	0
T5	19188	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	206	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T46	103706	0	0	0
T47	0	258	0	0
T50	0	783	0	0
T51	0	55	0	0
T64	0	227	0	0
T65	0	102	0	0
T70	0	55	0	0
T91	409	0	0	0
T97	0	229932	0	0
T98	0	168	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T49,T50
0	1	Covered	T71,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T49,T50
0	1	Unreachable
1	0	Covered	T1,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T24
DetectSt	168	Covered	T1,T49,T50
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T49,T50
DebounceSt->IdleSt	163	Covered	T3,T24,T43
DetectSt->IdleSt	186	Covered	T71,T72,T73
DetectSt->StableSt	191	Covered	T1,T49,T50
IdleSt->DebounceSt	148	Covered	T1,T3,T24
StableSt->IdleSt	206	Covered	T1,T49,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T24
0	1	Covered	T1,T3,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T49,T50
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T24,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T71,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T1,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	171	0	0
CntIncr_A	9556404	316686	0	0
CntNoWrap_A	9556404	8886531	0	0
DetectStDropOut_A	9556404	4	0	0
DetectedOut_A	9556404	21093	0	0
DetectedPulseOut_A	9556404	50	0	0
DisabledIdleSt_A	9556404	6602145	0	0
DisabledNoDetection_A	9556404	6604559	0	0
EnterDebounceSt_A	9556404	119	0	0
EnterDetectSt_A	9556404	54	0	0
EnterStableSt_A	9556404	50	0	0
PulseIsPulse_A	9556404	50	0	0
StayInStableSt	9556404	21043	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_sticky_sva.StableStDropOut_A	9556404	1496683	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	171	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	3	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	5	0	0
T43	0	1	0	0
T47	0	3	0	0
T49	0	6	0	0
T50	0	2	0	0
T51	0	4	0	0
T64	0	8	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	316686	0	0
T1	21977	52	0	0
T2	9174	0	0	0
T3	160979	60138	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	150	0	0
T43	0	81	0	0
T47	0	243	0	0
T49	0	141	0	0
T50	0	82	0	0
T51	0	64	0	0
T64	0	237	0	0
T65	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886531	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160575	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4	0	0
T71	11059	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T109	8628	0	0	0
T110	2215	0	0	0
T111	638	0	0	0
T112	409	0	0	0
T113	407	0	0	0
T114	31741	0	0	0
T115	471	0	0	0
T116	523	0	0	0
T117	752	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	21093	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	987	0	0
T50	0	712	0	0
T51	0	230	0	0
T64	0	154	0	0
T65	0	442	0	0
T70	0	156	0	0
T98	0	296	0	0
T99	0	14	0	0
T100	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	50	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T70	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6602145	0	0
T1	21977	13594	0	0
T2	9174	8765	0	0
T3	160979	100343	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6604559	0	0
T1	21977	13618	0	0
T2	9174	8767	0	0
T3	160979	100344	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	119	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	3	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	5	0	0
T43	0	2	0	0
T47	0	3	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	6	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	54	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T70	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	50	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T70	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	50	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T70	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	21043	0	0
T1	21977	3	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	984	0	0
T50	0	711	0	0
T51	0	228	0	0
T64	0	152	0	0
T65	0	441	0	0
T70	0	155	0	0
T98	0	295	0	0
T99	0	13	0	0
T100	0	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1496683	0	0
T1	21977	30	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	740	0	0
T50	0	82	0	0
T51	0	75759	0	0
T64	0	266	0	0
T65	0	246946	0	0
T70	0	113	0	0
T98	0	50	0	0
T99	0	137	0	0
T100	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T47,T49
0	1	Covered	T1,T3,T49
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T47,T49
0	1	Unreachable
1	0	Covered	T24,T47,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T24
DetectSt	168	Covered	T1,T3,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T24,T47,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T24
DebounceSt->IdleSt	163	Covered	T43,T50,T64
DetectSt->IdleSt	186	Covered	T1,T3,T49
DetectSt->StableSt	191	Covered	T24,T47,T49
IdleSt->DebounceSt	148	Covered	T1,T3,T24
StableSt->IdleSt	206	Covered	T24,T47,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T24
0	1	Covered	T1,T3,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T64,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T1,T3,T49
DetectSt	-	-	-	-	0	1	-	Covered	T24,T47,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T47,T49
StableSt	-	-	-	-	-	-	0	Covered	T24,T47,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	180	0	0
CntIncr_A	9556404	367579	0	0
CntNoWrap_A	9556404	8886522	0	0
DetectStDropOut_A	9556404	18	0	0
DetectedOut_A	9556404	475992	0	0
DetectedPulseOut_A	9556404	52	0	0
DisabledIdleSt_A	9556404	6602145	0	0
DisabledNoDetection_A	9556404	6604559	0	0
EnterDebounceSt_A	9556404	112	0	0
EnterDetectSt_A	9556404	70	0	0
EnterStableSt_A	9556404	52	0	0
PulseIsPulse_A	9556404	52	0	0
StayInStableSt	9556404	475940	0	0
gen_high_event_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_sticky_sva.StableStDropOut_A	9556404	1148222	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	180	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	6	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T43	0	1	0	0
T47	0	2	0	0
T49	0	16	0	0
T50	0	3	0	0
T51	0	4	0	0
T64	0	8	0	0
T65	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	367579	0	0
T1	21977	40	0	0
T2	9174	0	0	0
T3	160979	225	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	22	0	0
T43	0	83	0	0
T47	0	51	0	0
T49	0	688	0	0
T50	0	176	0	0
T51	0	40	0	0
T64	0	366	0	0
T65	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886522	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160572	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	18	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	3	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T49	0	6	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0
T121	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	475992	0	0
T24	15302	153	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	182	0	0
T49	0	352	0	0
T50	0	268	0	0
T51	0	175	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	290	0	0
T65	0	296	0	0
T97	0	628	0	0
T98	0	157	0	0
T99	0	66	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T24	15302	1	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6602145	0	0
T1	21977	13594	0	0
T2	9174	8765	0	0
T3	160979	100343	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6604559	0	0
T1	21977	13618	0	0
T2	9174	8767	0	0
T3	160979	100344	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	112	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	3	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T49	0	8	0	0
T50	0	2	0	0
T51	0	2	0	0
T64	0	6	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	70	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	3	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T47	0	1	0	0
T49	0	8	0	0
T50	0	1	0	0
T51	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T97	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T24	15302	1	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T24	15302	1	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	475940	0	0
T24	15302	152	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	181	0	0
T49	0	350	0	0
T50	0	267	0	0
T51	0	173	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	288	0	0
T65	0	295	0	0
T97	0	626	0	0
T98	0	156	0	0
T99	0	65	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1148222	0	0
T24	15302	346	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T47	0	160	0	0
T49	0	439	0	0
T50	0	353	0	0
T51	0	75866	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	195	0	0
T65	0	247131	0	0
T97	0	229951	0	0
T98	0	202	0	0
T99	0	48	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Covered	T122,T123
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Covered	T24,T31,T34
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T24
1	-	Covered	T24,T31,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T24
DetectSt	168	Covered	T1,T8,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T24
DebounceSt->IdleSt	163	Covered	T43,T124,T125
DetectSt->IdleSt	186	Covered	T122,T123
DetectSt->StableSt	191	Covered	T1,T8,T24
IdleSt->DebounceSt	148	Covered	T1,T8,T24
StableSt->IdleSt	206	Covered	T1,T24,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T24
0	1	Covered	T1,T8,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T122,T123
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T31,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	95	0	0
CntIncr_A	9556404	51973	0	0
CntNoWrap_A	9556404	8886607	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	82123	0	0
DetectedPulseOut_A	9556404	44	0	0
DisabledIdleSt_A	9556404	8533171	0	0
DisabledNoDetection_A	9556404	8535529	0	0
EnterDebounceSt_A	9556404	50	0	0
EnterDetectSt_A	9556404	46	0	0
EnterStableSt_A	9556404	44	0	0
PulseIsPulse_A	9556404	44	0	0
StayInStableSt	9556404	82057	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	95	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	6	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	4	0	0
T43	0	1	0	0
T124	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	51973	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	93	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	93	0	0
T29	0	252	0	0
T31	0	80	0	0
T32	0	19	0	0
T33	0	27	0	0
T34	0	116	0	0
T43	0	15	0	0
T124	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886607	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T80	49736	0	0	0
T122	1003	1	0	0
T123	0	1	0	0
T126	13924	0	0	0
T127	32594	0	0	0
T128	9989	0	0	0
T129	619	0	0	0
T130	6708	0	0	0
T131	19077	0	0	0
T132	482	0	0	0
T133	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	82123	0	0
T1	21977	42	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	326	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	41	0	0
T29	0	188	0	0
T31	0	32	0	0
T32	0	62	0	0
T33	0	39	0	0
T34	0	268	0	0
T64	0	181	0	0
T134	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	44	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8533171	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8535529	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	50	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T43	0	1	0	0
T124	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	46	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	44	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	44	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	82057	0	0
T1	21977	40	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	324	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	40	0	0
T29	0	183	0	0
T31	0	31	0	0
T32	0	60	0	0
T33	0	38	0	0
T34	0	265	0	0
T64	0	178	0	0
T134	0	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	21	0	0
T24	15302	1	0	0
T29	0	1	0	0
T31	1124	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T64	0	1	0	0
T86	0	2	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T128	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T136,T137
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T1,T24,T34
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T24
1	-	Covered	T1,T24,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T9,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T43,T138,T139
DetectSt->IdleSt	186	Covered	T136,T137
DetectSt->StableSt	191	Covered	T1,T9,T24
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T1,T24,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T138,T139,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T136,T137
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T24,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	134	0	0
CntIncr_A	9556404	95141	0	0
CntNoWrap_A	9556404	8886568	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	101900	0	0
DetectedPulseOut_A	9556404	62	0	0
DisabledIdleSt_A	9556404	8441705	0	0
DisabledNoDetection_A	9556404	8444068	0	0
EnterDebounceSt_A	9556404	70	0	0
EnterDetectSt_A	9556404	64	0	0
EnterStableSt_A	9556404	62	0	0
PulseIsPulse_A	9556404	62	0	0
StayInStableSt	9556404	101811	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	2704	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	134	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	6	0	0
T29	0	4	0	0
T32	0	2	0	0
T34	0	4	0	0
T43	0	1	0	0
T61	0	2	0	0
T64	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	95141	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	28	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	205	0	0
T29	0	190	0	0
T32	0	19	0	0
T34	0	116	0	0
T43	0	14	0	0
T61	0	99	0	0
T64	0	27	0	0
T140	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886568	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T136	686	1	0	0
T137	0	1	0	0
T141	523	0	0	0
T142	414	0	0	0
T143	5766	0	0	0
T144	506	0	0	0
T145	298913	0	0	0
T146	4820	0	0	0
T147	17279	0	0	0
T148	450	0	0	0
T149	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	101900	0	0
T1	21977	185	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	68	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	663	0	0
T29	0	266	0	0
T32	0	42	0	0
T34	0	8	0	0
T61	0	238	0	0
T64	0	236	0	0
T140	0	138	0	0
T150	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	62	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T140	0	1	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8441705	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8444068	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	70	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T43	0	1	0	0
T61	0	1	0	0
T64	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	64	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T140	0	1	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	62	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T140	0	1	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	62	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T140	0	1	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	101811	0	0
T1	21977	184	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	66	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	658	0	0
T29	0	264	0	0
T32	0	41	0	0
T34	0	6	0	0
T61	0	237	0	0
T64	0	235	0	0
T140	0	136	0	0
T150	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2704	0	0
T1	21977	27	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	5	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	435	2	0	0
T13	523	7	0	0
T14	454	6	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T25	0	5	0	0
T77	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	34	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0
T69	0	1	0	0
T138	0	1	0	0
T151	0	1	0	0