Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Covered	T69,T152,T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Covered	T33,T61,T32
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T24
1	-	Covered	T33,T61,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T24
DetectSt	168	Covered	T1,T8,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T24
DebounceSt->IdleSt	163	Covered	T43,T124,T154
DetectSt->IdleSt	186	Covered	T69,T152,T153
DetectSt->StableSt	191	Covered	T1,T8,T24
IdleSt->DebounceSt	148	Covered	T1,T8,T24
StableSt->IdleSt	206	Covered	T1,T33,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T24
0	1	Covered	T1,T8,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T69,T152,T153
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T61,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	115	0	0
CntIncr_A	9556404	3342	0	0
CntNoWrap_A	9556404	8886587	0	0
DetectStDropOut_A	9556404	4	0	0
DetectedOut_A	9556404	4683	0	0
DetectedPulseOut_A	9556404	52	0	0
DisabledIdleSt_A	9556404	8861646	0	0
DisabledNoDetection_A	9556404	8863999	0	0
EnterDebounceSt_A	9556404	59	0	0
EnterDetectSt_A	9556404	56	0	0
EnterStableSt_A	9556404	52	0	0
PulseIsPulse_A	9556404	52	0	0
StayInStableSt	9556404	4606	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	115	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T61	0	4	0	0
T124	0	1	0	0
T134	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3342	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	93	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	93	0	0
T32	0	60	0	0
T33	0	27	0	0
T43	0	14	0	0
T61	0	198	0	0
T124	0	86	0	0
T134	0	70	0	0
T155	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886587	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4	0	0
T69	21267	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	769	0	0	0
T158	892	0	0	0
T159	524	0	0	0
T160	425	0	0	0
T161	29672	0	0	0
T162	404	0	0	0
T163	1078	0	0	0
T164	509	0	0	0
T165	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4683	0	0
T1	21977	176	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	158	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	52	0	0
T32	0	262	0	0
T33	0	41	0	0
T61	0	270	0	0
T64	0	181	0	0
T134	0	223	0	0
T155	0	180	0	0
T166	0	143	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0
T155	0	1	0	0
T166	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8861646	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8863999	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	59	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	1	0	0
T61	0	2	0	0
T124	0	1	0	0
T134	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	56	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0
T155	0	1	0	0
T166	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0
T155	0	1	0	0
T166	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	52	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T64	0	2	0	0
T134	0	1	0	0
T155	0	1	0	0
T166	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4606	0	0
T1	21977	174	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	156	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	50	0	0
T32	0	261	0	0
T33	0	40	0	0
T61	0	268	0	0
T64	0	178	0	0
T134	0	221	0	0
T155	0	178	0	0
T166	0	140	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	26	0	0
T29	26777	0	0	0
T32	0	1	0	0
T33	2941	1	0	0
T43	6091	0	0	0
T61	1212	2	0	0
T64	0	1	0	0
T78	9596	0	0	0
T93	436	0	0	0
T94	18927	0	0	0
T128	0	1	0	0
T135	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	426	0	0	0
T171	716	0	0	0
T172	503	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T173,T174,T137
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T31
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T9
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T61,T43,T166
DetectSt->IdleSt	186	Covered	T173,T174,T137
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T8,T9
StableSt->IdleSt	206	Covered	T1,T8,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T166,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T173,T174,T137
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	177	0	0
CntIncr_A	9556404	5358	0	0
CntNoWrap_A	9556404	8886525	0	0
DetectStDropOut_A	9556404	3	0	0
DetectedOut_A	9556404	7382	0	0
DetectedPulseOut_A	9556404	83	0	0
DisabledIdleSt_A	9556404	8863164	0	0
DisabledNoDetection_A	9556404	8865522	0	0
EnterDebounceSt_A	9556404	92	0	0
EnterDetectSt_A	9556404	86	0	0
EnterStableSt_A	9556404	83	0	0
PulseIsPulse_A	9556404	83	0	0
StayInStableSt	9556404	7267	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	3059	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	50	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	177	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	6	0	0
T31	0	4	0	0
T32	0	4	0	0
T33	0	4	0	0
T43	0	1	0	0
T61	0	5	0	0
T124	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	5358	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	93	0	0
T9	0	28	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	285	0	0
T31	0	160	0	0
T32	0	38	0	0
T33	0	54	0	0
T43	0	14	0	0
T61	0	297	0	0
T124	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886525	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3	0	0
T136	686	0	0	0
T137	0	1	0	0
T141	523	0	0	0
T142	414	0	0	0
T143	5766	0	0	0
T144	506	0	0	0
T145	298913	0	0	0
T146	4820	0	0	0
T173	6915	1	0	0
T174	0	1	0	0
T175	12110	0	0	0
T176	678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	7382	0	0
T1	21977	50	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	356	0	0
T9	0	68	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	136	0	0
T31	0	201	0	0
T32	0	96	0	0
T33	0	90	0	0
T61	0	97	0	0
T124	0	152	0	0
T155	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	83	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T61	0	2	0	0
T124	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8863164	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8865522	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	92	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T61	0	3	0	0
T124	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	86	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T61	0	2	0	0
T124	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	83	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T61	0	2	0	0
T124	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	83	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T61	0	2	0	0
T124	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	7267	0	0
T1	21977	49	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	355	0	0
T9	0	66	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	132	0	0
T31	0	198	0	0
T32	0	94	0	0
T33	0	87	0	0
T61	0	94	0	0
T124	0	149	0	0
T155	0	13	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3059	0	0
T1	21977	36	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	5	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	9	0	0
T12	435	2	0	0
T13	523	5	0	0
T14	454	3	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T46	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	50	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T61	0	1	0	0
T124	0	1	0	0
T134	0	1	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T24
0	1	Covered	T1,T8,T24
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T24
1	-	Covered	T1,T8,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T24
DetectSt	168	Covered	T1,T8,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T24
DebounceSt->IdleSt	163	Covered	T24,T43,T124
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T8,T24
IdleSt->DebounceSt	148	Covered	T1,T8,T24
StableSt->IdleSt	206	Covered	T1,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T24
0	1	Covered	T1,T8,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T124,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T24
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	150	0	0
CntIncr_A	9556404	6025	0	0
CntNoWrap_A	9556404	8886552	0	0
DetectStDropOut_A	9556404	0	0	0
DetectedOut_A	9556404	6173	0	0
DetectedPulseOut_A	9556404	71	0	0
DisabledIdleSt_A	9556404	8769603	0	0
DisabledNoDetection_A	9556404	8771960	0	0
EnterDebounceSt_A	9556404	81	0	0
EnterDetectSt_A	9556404	71	0	0
EnterStableSt_A	9556404	71	0	0
PulseIsPulse_A	9556404	71	0	0
StayInStableSt	9556404	6074	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	150	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	6	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	5	0	0
T29	0	4	0	0
T32	0	4	0	0
T33	0	6	0	0
T34	0	6	0	0
T43	0	1	0	0
T61	0	2	0	0
T124	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6025	0	0
T1	21977	122	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	279	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	205	0	0
T29	0	124	0	0
T32	0	120	0	0
T33	0	90	0	0
T34	0	174	0	0
T43	0	14	0	0
T61	0	99	0	0
T124	0	258	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886552	0	0
T1	21977	13686	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6173	0	0
T1	21977	197	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	163	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	397	0	0
T29	0	47	0	0
T32	0	97	0	0
T33	0	67	0	0
T34	0	78	0	0
T61	0	223	0	0
T124	0	149	0	0
T177	0	329	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	71	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	3	0	0
T61	0	1	0	0
T124	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8769603	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8771960	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	81	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	3	0	0
T43	0	1	0	0
T61	0	1	0	0
T124	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	71	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	3	0	0
T61	0	1	0	0
T124	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	71	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	3	0	0
T61	0	1	0	0
T124	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	71	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T34	0	3	0	0
T61	0	1	0	0
T124	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6074	0	0
T1	21977	194	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	159	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	394	0	0
T29	0	44	0	0
T32	0	95	0	0
T33	0	63	0	0
T34	0	74	0	0
T61	0	221	0	0
T124	0	146	0	0
T177	0	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T8	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T64	0	2	0	0
T124	0	1	0	0
T134	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T24
0	1	Covered	T168,T178
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T24
0	1	Covered	T7,T8,T24
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T24
1	-	Covered	T7,T8,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T8
DetectSt	168	Covered	T7,T8,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T24
DebounceSt->IdleSt	163	Covered	T1,T43,T125
DetectSt->IdleSt	186	Covered	T168,T178
DetectSt->StableSt	191	Covered	T7,T8,T24
IdleSt->DebounceSt	148	Covered	T1,T7,T8
StableSt->IdleSt	206	Covered	T7,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T168,T178
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	75	0	0
CntIncr_A	9556404	2188	0	0
CntNoWrap_A	9556404	8886627	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	2749	0	0
DetectedPulseOut_A	9556404	34	0	0
DisabledIdleSt_A	9556404	8773493	0	0
DisabledNoDetection_A	9556404	8775855	0	0
EnterDebounceSt_A	9556404	39	0	0
EnterDetectSt_A	9556404	36	0	0
EnterStableSt_A	9556404	34	0	0
PulseIsPulse_A	9556404	34	0	0
StayInStableSt	9556404	2696	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	6730	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	75	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T8	0	4	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	6	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	0	4	0	0
T43	0	1	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2188	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	45	0	0
T8	0	186	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	152	0	0
T29	0	62	0	0
T31	0	80	0	0
T32	0	120	0	0
T34	0	116	0	0
T43	0	14	0	0
T70	0	49	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886627	0	0
T1	21977	13689	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T135	726	0	0	0
T168	1026	1	0	0
T178	0	1	0	0
T179	1985	0	0	0
T180	523	0	0	0
T181	721	0	0	0
T182	1345	0	0	0
T183	496	0	0	0
T184	1363	0	0	0
T185	522	0	0	0
T186	737	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2749	0	0
T7	718	118	0	0
T8	1110	69	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	154	0	0
T25	493	0	0	0
T29	0	106	0	0
T30	21074	0	0	0
T31	0	277	0	0
T32	0	88	0	0
T34	0	138	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	62	0	0
T77	422	0	0	0
T128	0	218	0	0
T167	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	34	0	0
T7	718	1	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	3	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	3	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8773493	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8775855	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	39	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	3	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T43	0	1	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	36	0	0
T7	718	1	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	3	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	3	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	34	0	0
T7	718	1	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	3	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	3	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	34	0	0
T7	718	1	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	3	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	3	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2696	0	0
T7	718	117	0	0
T8	1110	67	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	149	0	0
T25	493	0	0	0
T29	0	105	0	0
T30	21074	0	0	0
T31	0	275	0	0
T32	0	85	0	0
T34	0	136	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	60	0	0
T77	422	0	0	0
T128	0	213	0	0
T167	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6730	0	0
T1	21977	51	0	0
T2	9174	31	0	0
T3	160979	8	0	0
T4	521	5	0	0
T5	0	28	0	0
T12	435	4	0	0
T13	523	5	0	0
T14	454	4	0	0
T15	24026	35	0	0
T16	719	0	0	0
T17	10947	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	14	0	0
T7	718	1	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	1	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T77	422	0	0	0
T128	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T7,T31,T33
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T9
1	-	Covered	T7,T31,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T43,T166,T128
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T128,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T31,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	148	0	0
CntIncr_A	9556404	89091	0	0
CntNoWrap_A	9556404	8886554	0	0
DetectStDropOut_A	9556404	0	0	0
DetectedOut_A	9556404	211197	0	0
DetectedPulseOut_A	9556404	72	0	0
DisabledIdleSt_A	9556404	8473704	0	0
DisabledNoDetection_A	9556404	8476063	0	0
EnterDebounceSt_A	9556404	76	0	0
EnterDetectSt_A	9556404	72	0	0
EnterStableSt_A	9556404	72	0	0
PulseIsPulse_A	9556404	72	0	0
StayInStableSt	9556404	211088	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	148	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	4	0	0
T9	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T31	0	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T61	0	4	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	89091	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	90	0	0
T9	0	28	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	190	0	0
T31	0	160	0	0
T32	0	60	0	0
T33	0	27	0	0
T43	0	13	0	0
T61	0	198	0	0
T140	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886554	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	211197	0	0
T1	21977	42	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	78	0	0
T9	0	38	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	376	0	0
T31	0	199	0	0
T32	0	473	0	0
T33	0	5	0	0
T61	0	410	0	0
T140	0	138	0	0
T190	0	74	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T140	0	1	0	0
T190	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8473704	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8476063	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	76	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	1	0	0
T61	0	2	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T140	0	1	0	0
T190	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T140	0	1	0	0
T190	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T61	0	2	0	0
T140	0	1	0	0
T190	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	211088	0	0
T1	21977	40	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	75	0	0
T9	0	36	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	373	0	0
T31	0	196	0	0
T32	0	471	0	0
T33	0	4	0	0
T61	0	407	0	0
T140	0	136	0	0
T190	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	34	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T61	0	1	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	3	0	0
T138	0	1	0	0
T166	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T34,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T34,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T34,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T34,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T32
0	1	Covered	T122,T191,T192
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T32
0	1	Covered	T8,T34,T190
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T34,T32
1	-	Covered	T8,T34,T190

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T43
DetectSt	168	Covered	T8,T34,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T34,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T34,T32
DebounceSt->IdleSt	163	Covered	T43,T124,T70
DetectSt->IdleSt	186	Covered	T122,T191,T192
DetectSt->StableSt	191	Covered	T8,T34,T32
IdleSt->DebounceSt	148	Covered	T8,T34,T43
StableSt->IdleSt	206	Covered	T8,T34,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T43
0	1	Covered	T8,T34,T43
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T34,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T34,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T43
DetectSt	-	-	-	-	1	-	-	Covered	T122,T191,T192
DetectSt	-	-	-	-	0	1	-	Covered	T8,T34,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T34,T190
StableSt	-	-	-	-	-	-	0	Covered	T8,T34,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	99	0	0
CntIncr_A	9556404	44262	0	0
CntNoWrap_A	9556404	8886603	0	0
DetectStDropOut_A	9556404	3	0	0
DetectedOut_A	9556404	4441	0	0
DetectedPulseOut_A	9556404	45	0	0
DisabledIdleSt_A	9556404	8439665	0	0
DisabledNoDetection_A	9556404	8442019	0	0
EnterDebounceSt_A	9556404	51	0	0
EnterDetectSt_A	9556404	48	0	0
EnterStableSt_A	9556404	45	0	0
PulseIsPulse_A	9556404	45	0	0
StayInStableSt	9556404	4381	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	6492	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	99	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	2	0	0
T34	0	4	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	1	0	0
T62	5116	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T122	0	2	0	0
T124	0	1	0	0
T134	0	2	0	0
T166	0	4	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	44262	0	0
T8	1110	93	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	19	0	0
T34	0	116	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	14	0	0
T62	5116	0	0	0
T70	0	49	0	0
T77	422	0	0	0
T122	0	67	0	0
T124	0	86	0	0
T134	0	70	0	0
T166	0	44	0	0
T190	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886603	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3	0	0
T80	49736	0	0	0
T122	1003	1	0	0
T126	13924	0	0	0
T127	32594	0	0	0
T128	9989	0	0	0
T129	619	0	0	0
T130	6708	0	0	0
T131	19077	0	0	0
T132	482	0	0	0
T133	491	0	0	0
T191	0	1	0	0
T192	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4441	0	0
T8	1110	192	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	204	0	0
T34	0	33	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T128	0	126	0	0
T134	0	109	0	0
T135	0	81	0	0
T139	0	47	0	0
T166	0	144	0	0
T168	0	167	0	0
T190	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T128	0	3	0	0
T134	0	1	0	0
T135	0	2	0	0
T139	0	1	0	0
T166	0	2	0	0
T168	0	2	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8439665	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8442019	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	51	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	1	0	0
T62	5116	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T134	0	1	0	0
T166	0	2	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	48	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T122	0	1	0	0
T128	0	3	0	0
T134	0	1	0	0
T139	0	1	0	0
T166	0	2	0	0
T168	0	2	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T128	0	3	0	0
T134	0	1	0	0
T135	0	2	0	0
T139	0	1	0	0
T166	0	2	0	0
T168	0	2	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T128	0	3	0	0
T134	0	1	0	0
T135	0	2	0	0
T139	0	1	0	0
T166	0	2	0	0
T168	0	2	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4381	0	0
T8	1110	191	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	202	0	0
T34	0	31	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T128	0	121	0	0
T134	0	107	0	0
T135	0	78	0	0
T139	0	45	0	0
T166	0	141	0	0
T168	0	164	0	0
T190	0	58	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6492	0	0
T1	21977	51	0	0
T2	9174	24	0	0
T3	160979	0	0	0
T4	521	5	0	0
T5	0	33	0	0
T12	435	2	0	0
T13	523	3	0	0
T14	454	4	0	0
T15	24026	37	0	0
T16	719	0	0	0
T17	10947	31	0	0
T37	0	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	29	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T34	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T86	0	1	0	0
T123	0	1	0	0
T128	0	1	0	0
T135	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T190	0	1	0	0
T193	0	1	0	0