Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T7,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T24
0	1	Covered	T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T24
0	1	Covered	T7,T8,T24
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T24
1	-	Covered	T7,T8,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T24
DetectSt	168	Covered	T7,T8,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T24
DebounceSt->IdleSt	163	Covered	T8,T43,T124
DetectSt->IdleSt	186	Covered	T70
DetectSt->StableSt	191	Covered	T7,T8,T24
IdleSt->DebounceSt	148	Covered	T7,T8,T24
StableSt->IdleSt	206	Covered	T7,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T24
0	1	Covered	T7,T8,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T124,T128
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T70
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	127	0	0
CntIncr_A	9556404	96065	0	0
CntNoWrap_A	9556404	8886575	0	0
DetectStDropOut_A	9556404	1	0	0
DetectedOut_A	9556404	30050	0	0
DetectedPulseOut_A	9556404	58	0	0
DisabledIdleSt_A	9556404	8537293	0	0
DisabledNoDetection_A	9556404	8539661	0	0
EnterDebounceSt_A	9556404	68	0	0
EnterDetectSt_A	9556404	59	0	0
EnterStableSt_A	9556404	58	0	0
PulseIsPulse_A	9556404	58	0	0
StayInStableSt	9556404	29972	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	127	0	0
T7	718	4	0	0
T8	1110	3	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	4	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	8	0	0
T33	0	2	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	1	0	0
T77	422	0	0	0
T124	0	2	0	0
T140	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	96065	0	0
T7	718	90	0	0
T8	1110	186	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	112	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	158	0	0
T33	0	36	0	0
T34	0	58	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	15	0	0
T77	422	0	0	0
T124	0	172	0	0
T140	0	66	0	0
T155	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886575	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1	0	0
T70	19067	1	0	0
T100	566	0	0	0
T194	425	0	0	0
T195	4412	0	0	0
T196	4816	0	0	0
T197	636	0	0	0
T198	8402	0	0	0
T199	13132	0	0	0
T200	648	0	0	0
T201	515	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	30050	0	0
T7	718	132	0	0
T8	1110	25	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	147	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	358	0	0
T33	0	110	0	0
T34	0	189	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	60	0	0
T77	422	0	0	0
T134	0	55	0	0
T140	0	28	0	0
T155	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	58	0	0
T7	718	2	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	2	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8537293	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8539661	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	68	0	0
T7	718	2	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	2	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	1	0	0
T77	422	0	0	0
T124	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	59	0	0
T7	718	2	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	2	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	58	0	0
T7	718	2	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	2	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	58	0	0
T7	718	2	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	2	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	29972	0	0
T7	718	129	0	0
T8	1110	24	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	144	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	352	0	0
T33	0	108	0	0
T34	0	188	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	58	0	0
T77	422	0	0	0
T134	0	53	0	0
T140	0	27	0	0
T155	0	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	37	0	0
T7	718	1	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T24	0	1	0	0
T25	493	0	0	0
T30	21074	0	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T64	0	2	0	0
T70	0	1	0	0
T77	422	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T31,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T8,T31,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T31,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T24,T31
1	0	Covered	T1,T2,T4
1	1	Covered	T8,T31,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T33
0	1	Covered	T32
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T31,T33
0	1	Covered	T8,T31,T29
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T31,T33
1	-	Covered	T8,T31,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T31,T33
DetectSt	168	Covered	T8,T31,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T8,T31,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T31,T33
DebounceSt->IdleSt	163	Covered	T43,T29
DetectSt->IdleSt	186	Covered	T32
DetectSt->StableSt	191	Covered	T8,T31,T33
IdleSt->DebounceSt	148	Covered	T8,T31,T33
StableSt->IdleSt	206	Covered	T8,T31,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T31,T33
0	1	Covered	T8,T31,T33
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T31,T33
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T31,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T31,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T29
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T31,T33
DetectSt	-	-	-	-	1	-	-	Covered	T32
DetectSt	-	-	-	-	0	1	-	Covered	T8,T31,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T31,T29
StableSt	-	-	-	-	-	-	0	Covered	T8,T31,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	86	0	0
CntIncr_A	9556404	2531	0	0
CntNoWrap_A	9556404	8886616	0	0
DetectStDropOut_A	9556404	1	0	0
DetectedOut_A	9556404	2552	0	0
DetectedPulseOut_A	9556404	41	0	0
DisabledIdleSt_A	9556404	8867262	0	0
DisabledNoDetection_A	9556404	8869623	0	0
EnterDebounceSt_A	9556404	44	0	0
EnterDetectSt_A	9556404	42	0	0
EnterStableSt_A	9556404	41	0	0
PulseIsPulse_A	9556404	41	0	0
StayInStableSt	9556404	2490	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	6450	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	86	0	0
T8	1110	4	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	3	0	0
T30	21074	0	0	0
T31	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	1	0	0
T61	0	2	0	0
T62	5116	0	0	0
T64	0	4	0	0
T77	422	0	0	0
T138	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2531	0	0
T8	1110	186	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	190	0	0
T30	21074	0	0	0
T31	0	160	0	0
T32	0	79	0	0
T33	0	27	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	14	0	0
T61	0	99	0	0
T62	5116	0	0	0
T64	0	54	0	0
T77	422	0	0	0
T138	0	72	0	0
T177	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886616	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1	0	0
T32	2518	1	0	0
T55	494	0	0	0
T75	4466	0	0	0
T124	1057	0	0	0
T202	539	0	0	0
T203	720	0	0	0
T204	677	0	0	0
T205	8401	0	0	0
T206	11063	0	0	0
T207	794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2552	0	0
T8	1110	82	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	51	0	0
T30	21074	0	0	0
T31	0	201	0	0
T32	0	264	0	0
T33	0	38	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	39	0	0
T62	5116	0	0	0
T64	0	162	0	0
T77	422	0	0	0
T138	0	23	0	0
T151	0	42	0	0
T177	0	31	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	41	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	1	0	0
T62	5116	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T138	0	1	0	0
T151	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8867262	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8869623	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	44	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T43	0	1	0	0
T61	0	1	0	0
T62	5116	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T138	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	1	0	0
T62	5116	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T138	0	1	0	0
T151	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	41	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	1	0	0
T62	5116	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T138	0	1	0	0
T151	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	41	0	0
T8	1110	2	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	1	0	0
T62	5116	0	0	0
T64	0	2	0	0
T77	422	0	0	0
T138	0	1	0	0
T151	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2490	0	0
T8	1110	79	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	50	0	0
T30	21074	0	0	0
T31	0	198	0	0
T32	0	263	0	0
T33	0	36	0	0
T40	656	0	0	0
T41	752	0	0	0
T61	0	37	0	0
T62	5116	0	0	0
T64	0	159	0	0
T77	422	0	0	0
T138	0	22	0	0
T151	0	41	0	0
T177	0	30	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6450	0	0
T1	21977	46	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	6	0	0
T5	0	29	0	0
T12	435	2	0	0
T13	523	2	0	0
T14	454	5	0	0
T15	24026	30	0	0
T16	719	0	0	0
T17	10947	27	0	0
T37	0	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	19	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T40	656	0	0	0
T41	752	0	0	0
T62	5116	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T77	422	0	0	0
T122	0	1	0	0
T138	0	1	0	0
T151	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T174,T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T7,T8,T61
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T7,T8,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T8
DetectSt	168	Covered	T1,T7,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T8
DebounceSt->IdleSt	163	Covered	T61,T43,T190
DetectSt->IdleSt	186	Covered	T174,T208
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T7,T8
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T190,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T174,T208
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T61
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	146	0	0
CntIncr_A	9556404	4604	0	0
CntNoWrap_A	9556404	8886556	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	5920	0	0
DetectedPulseOut_A	9556404	66	0	0
DisabledIdleSt_A	9556404	8865239	0	0
DisabledNoDetection_A	9556404	8867596	0	0
EnterDebounceSt_A	9556404	78	0	0
EnterDetectSt_A	9556404	68	0	0
EnterStableSt_A	9556404	66	0	0
PulseIsPulse_A	9556404	66	0	0
StayInStableSt	9556404	5830	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	146	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	4	0	0
T29	0	6	0	0
T33	0	2	0	0
T43	0	1	0	0
T61	0	5	0	0
T140	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4604	0	0
T1	21977	61	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	45	0	0
T8	0	93	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	59	0	0
T29	0	219	0	0
T33	0	27	0	0
T43	0	15	0	0
T61	0	297	0	0
T140	0	66	0	0
T177	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886556	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T73	922	0	0	0
T174	9720	1	0	0
T208	0	1	0	0
T209	8944	0	0	0
T210	513	0	0	0
T211	743	0	0	0
T212	33150	0	0	0
T213	402	0	0	0
T214	552577	0	0	0
T215	496	0	0	0
T216	63058	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	5920	0	0
T1	21977	288	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	178	0	0
T8	0	219	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	89	0	0
T29	0	89	0	0
T33	0	39	0	0
T61	0	282	0	0
T134	0	233	0	0
T140	0	27	0	0
T177	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	66	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	3	0	0
T33	0	1	0	0
T61	0	2	0	0
T134	0	2	0	0
T140	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8865239	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8867596	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	78	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	3	0	0
T33	0	1	0	0
T43	0	1	0	0
T61	0	3	0	0
T140	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	68	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	3	0	0
T33	0	1	0	0
T61	0	2	0	0
T134	0	2	0	0
T140	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	66	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	3	0	0
T33	0	1	0	0
T61	0	2	0	0
T134	0	2	0	0
T140	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	66	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	3	0	0
T33	0	1	0	0
T61	0	2	0	0
T134	0	2	0	0
T140	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	5830	0	0
T1	21977	286	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T7	0	177	0	0
T8	0	218	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	85	0	0
T29	0	85	0	0
T33	0	37	0	0
T61	0	279	0	0
T134	0	231	0	0
T140	0	26	0	0
T177	0	146	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	41	0	0
T7	718	1	0	0
T8	1110	1	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T39	7116	0	0	0
T40	656	0	0	0
T61	0	1	0	0
T77	422	0	0	0
T134	0	2	0	0
T138	0	2	0	0
T140	0	1	0	0
T166	0	1	0	0
T177	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T24,T43,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T24,T43,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T24,T29,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T24,T43,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T29,T32
0	1	Covered	T69,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T29,T124
0	1	Covered	T24,T29,T32
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T29,T124
1	-	Covered	T24,T29,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T43,T29
DetectSt	168	Covered	T24,T29,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T24,T29,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T29,T32
DebounceSt->IdleSt	163	Covered	T43,T90
DetectSt->IdleSt	186	Covered	T69,T152
DetectSt->StableSt	191	Covered	T24,T29,T32
IdleSt->DebounceSt	148	Covered	T24,T43,T29
StableSt->IdleSt	206	Covered	T24,T29,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T43,T29
0	1	Covered	T24,T43,T29
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T29,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T43,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T29,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T43,T29
DetectSt	-	-	-	-	1	-	-	Covered	T69,T152
DetectSt	-	-	-	-	0	1	-	Covered	T24,T29,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T29,T32
StableSt	-	-	-	-	-	-	0	Covered	T24,T29,T124
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	95	0	0
CntIncr_A	9556404	10435	0	0
CntNoWrap_A	9556404	8886607	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	4354	0	0
DetectedPulseOut_A	9556404	45	0	0
DisabledIdleSt_A	9556404	8739733	0	0
DisabledNoDetection_A	9556404	8742095	0	0
EnterDebounceSt_A	9556404	49	0	0
EnterDetectSt_A	9556404	47	0	0
EnterStableSt_A	9556404	45	0	0
PulseIsPulse_A	9556404	45	0	0
StayInStableSt	9556404	4282	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	6397	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	95	0	0
T24	15302	2	0	0
T29	0	4	0	0
T31	1124	0	0	0
T32	0	2	0	0
T43	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T69	0	2	0	0
T70	0	2	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T124	0	2	0	0
T138	0	4	0	0
T155	0	4	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	10435	0	0
T24	15302	93	0	0
T29	0	157	0	0
T31	1124	0	0	0
T32	0	19	0	0
T43	0	15	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T69	0	65	0	0
T70	0	71	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T124	0	86	0	0
T138	0	144	0	0
T155	0	70	0	0
T177	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886607	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T69	21267	1	0	0
T152	0	1	0	0
T157	769	0	0	0
T158	892	0	0	0
T159	524	0	0	0
T160	425	0	0	0
T161	29672	0	0	0
T162	404	0	0	0
T163	1078	0	0	0
T164	509	0	0	0
T165	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4354	0	0
T24	15302	369	0	0
T29	0	460	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T70	0	44	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	292	0	0
T124	0	439	0	0
T128	0	42	0	0
T138	0	112	0	0
T155	0	84	0	0
T177	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T24	15302	1	0	0
T29	0	2	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T70	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T128	0	1	0	0
T138	0	2	0	0
T155	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8739733	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8742095	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	49	0	0
T24	15302	1	0	0
T29	0	2	0	0
T31	1124	0	0	0
T32	0	1	0	0
T43	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T124	0	1	0	0
T138	0	2	0	0
T155	0	2	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	47	0	0
T24	15302	1	0	0
T29	0	2	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T138	0	2	0	0
T155	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T24	15302	1	0	0
T29	0	2	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T70	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T128	0	1	0	0
T138	0	2	0	0
T155	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45	0	0
T24	15302	1	0	0
T29	0	2	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T70	0	1	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T128	0	1	0	0
T138	0	2	0	0
T155	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	4282	0	0
T24	15302	368	0	0
T29	0	457	0	0
T31	1124	0	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T70	0	42	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T122	0	290	0	0
T124	0	437	0	0
T128	0	40	0	0
T138	0	109	0	0
T155	0	81	0	0
T177	0	37	0	0
T217	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	6397	0	0
T1	21977	55	0	0
T2	9174	26	0	0
T3	160979	0	0	0
T4	521	3	0	0
T5	0	31	0	0
T12	435	1	0	0
T13	523	5	0	0
T14	454	8	0	0
T15	24026	29	0	0
T16	719	0	0	0
T17	10947	26	0	0
T37	0	35	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	17	0	0
T24	15302	1	0	0
T29	0	1	0	0
T31	1124	0	0	0
T32	0	1	0	0
T45	14777	0	0	0
T52	499	0	0	0
T63	6830	0	0	0
T101	440	0	0	0
T102	452	0	0	0
T103	9315	0	0	0
T104	425	0	0	0
T105	701	0	0	0
T106	0	1	0	0
T138	0	1	0	0
T155	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T31
0	1	Covered	T9,T218
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T31
0	1	Covered	T1,T24,T31
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T24,T31
1	-	Covered	T1,T24,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T24,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T43,T124,T151
DetectSt->IdleSt	186	Covered	T9,T218
DetectSt->StableSt	191	Covered	T1,T24,T31
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T1,T24,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T9,T218
DetectSt	-	-	-	-	0	1	-	Covered	T1,T24,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T24,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T24,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	169	0	0
CntIncr_A	9556404	54268	0	0
CntNoWrap_A	9556404	8886533	0	0
DetectStDropOut_A	9556404	2	0	0
DetectedOut_A	9556404	23528	0	0
DetectedPulseOut_A	9556404	81	0	0
DisabledIdleSt_A	9556404	8531508	0	0
DisabledNoDetection_A	9556404	8533865	0	0
EnterDebounceSt_A	9556404	86	0	0
EnterDetectSt_A	9556404	83	0	0
EnterStableSt_A	9556404	81	0	0
PulseIsPulse_A	9556404	81	0	0
StayInStableSt	9556404	23418	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	51	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	169	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	4	0	0
T29	0	4	0	0
T31	0	4	0	0
T32	0	8	0	0
T33	0	2	0	0
T34	0	4	0	0
T43	0	1	0	0
T61	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	54268	0	0
T1	21977	122	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	28	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	133	0	0
T29	0	190	0	0
T31	0	160	0	0
T32	0	158	0	0
T33	0	36	0	0
T34	0	116	0	0
T43	0	14	0	0
T61	0	198	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886533	0	0
T1	21977	13686	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T30	21074	0	0	0
T40	656	0	0	0
T41	752	0	0	0
T42	681	0	0	0
T62	5116	0	0	0
T77	422	0	0	0
T218	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	23528	0	0
T1	21977	83	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	555	0	0
T29	0	118	0	0
T31	0	333	0	0
T32	0	204	0	0
T33	0	110	0	0
T34	0	203	0	0
T61	0	82	0	0
T124	0	163	0	0
T177	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	81	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T61	0	2	0	0
T124	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8531508	0	0
T1	21977	13335	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8533865	0	0
T1	21977	13358	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	86	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T43	0	1	0	0
T61	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	83	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T9	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T61	0	2	0	0
T124	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	81	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T61	0	2	0	0
T124	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	81	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	1	0	0
T34	0	2	0	0
T61	0	2	0	0
T124	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	23418	0	0
T1	21977	80	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	552	0	0
T29	0	116	0	0
T31	0	330	0	0
T32	0	200	0	0
T33	0	108	0	0
T34	0	200	0	0
T61	0	79	0	0
T124	0	162	0	0
T177	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	51	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T61	0	1	0	0
T124	0	1	0	0
T140	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T9,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T7,T9,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T9,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T31
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T9,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T31
0	1	Covered	T7,T31,T34
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T31
1	-	Covered	T7,T31,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T31
DetectSt	168	Covered	T7,T9,T31
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T9,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T31
DebounceSt->IdleSt	163	Covered	T43,T64,T70
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T9,T31
IdleSt->DebounceSt	148	Covered	T7,T9,T31
StableSt->IdleSt	206	Covered	T7,T31,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T31
0	1	Covered	T7,T9,T31
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T31
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T70,T153
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T31,T34
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	89	0	0
CntIncr_A	9556404	2487	0	0
CntNoWrap_A	9556404	8886613	0	0
DetectStDropOut_A	9556404	0	0	0
DetectedOut_A	9556404	3135	0	0
DetectedPulseOut_A	9556404	42	0	0
DisabledIdleSt_A	9556404	8866217	0	0
DisabledNoDetection_A	9556404	8868575	0	0
EnterDebounceSt_A	9556404	47	0	0
EnterDetectSt_A	9556404	42	0	0
EnterStableSt_A	9556404	42	0	0
PulseIsPulse_A	9556404	42	0	0
StayInStableSt	9556404	3072	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9556404	7202	0	0
gen_low_level_sva.LowLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	89	0	0
T7	718	2	0	0
T8	1110	0	0	0
T9	505	2	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	4	0	0
T30	21074	0	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	0	2	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	1	0	0
T64	0	1	0	0
T77	422	0	0	0
T155	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2487	0	0
T7	718	45	0	0
T8	1110	0	0	0
T9	505	28	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	190	0	0
T30	21074	0	0	0
T31	0	80	0	0
T32	0	38	0	0
T34	0	58	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	14	0	0
T64	0	97	0	0
T77	422	0	0	0
T155	0	35	0	0
T166	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8886613	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3135	0	0
T7	718	32	0	0
T8	1110	0	0	0
T9	505	39	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	232	0	0
T30	21074	0	0	0
T31	0	33	0	0
T32	0	163	0	0
T34	0	131	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	170	0	0
T77	422	0	0	0
T151	0	271	0	0
T155	0	43	0	0
T166	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	2	0	0
T77	422	0	0	0
T151	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8866217	0	0
T1	21977	13690	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8868575	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	47	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T43	0	1	0	0
T64	0	1	0	0
T77	422	0	0	0
T155	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	2	0	0
T77	422	0	0	0
T151	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	2	0	0
T77	422	0	0	0
T151	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	42	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	1	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	2	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	2	0	0
T77	422	0	0	0
T151	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3072	0	0
T7	718	31	0	0
T8	1110	0	0	0
T9	505	37	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	229	0	0
T30	21074	0	0	0
T31	0	32	0	0
T32	0	160	0	0
T34	0	130	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	167	0	0
T77	422	0	0	0
T122	0	38	0	0
T151	0	269	0	0
T155	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	7202	0	0
T1	21977	44	0	0
T2	9174	24	0	0
T3	160979	8	0	0
T4	521	7	0	0
T12	435	2	0	0
T13	523	5	0	0
T14	454	6	0	0
T15	24026	24	0	0
T16	719	3	0	0
T17	10947	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	20	0	0
T7	718	1	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	22062	0	0	0
T11	63031	0	0	0
T25	493	0	0	0
T29	0	1	0	0
T30	21074	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T39	7116	0	0	0
T40	656	0	0	0
T70	0	1	0	0
T77	422	0	0	0
T128	0	2	0	0
T155	0	1	0	0
T166	0	1	0	0
T219	0	1	0	0