Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T17
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T17
1	0	Covered	T2,T15,T17
1	1	Covered	T2,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T17,T37,T62
1	0	Covered	T2,T15,T17

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T39,T10
0	1	Covered	T5,T39,T10
1	0	Covered	T2,T17,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T17,T5
1	-	Covered	T5,T39,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T17
DetectSt	168	Covered	T2,T15,T17
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T17,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T17
DebounceSt->IdleSt	163	Covered	T39,T43,T75
DetectSt->IdleSt	186	Covered	T2,T15,T17
DetectSt->StableSt	191	Covered	T2,T17,T5
IdleSt->DebounceSt	148	Covered	T2,T15,T17
StableSt->IdleSt	206	Covered	T2,T17,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T2,T15,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T43,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	0	1	-	Covered	T2,T17,T5
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T2,T17,T5
StableSt	-	-	-	-	-	-	0	Covered	T5,T39,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	2883	0	0
CntIncr_A	9556404	108098	0	0
CntNoWrap_A	9556404	8883819	0	0
DetectStDropOut_A	9556404	358	0	0
DetectedOut_A	9556404	70262	0	0
DetectedPulseOut_A	9556404	834	0	0
DisabledIdleSt_A	9556404	8432077	0	0
DisabledNoDetection_A	9556404	8434288	0	0
EnterDebounceSt_A	9556404	1468	0	0
EnterDetectSt_A	9556404	1416	0	0
EnterStableSt_A	9556404	834	0	0
PulseIsPulse_A	9556404	834	0	0
StayInStableSt	9556404	69317	0	0
gen_high_event_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	711	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	2883	0	0
T2	9174	58	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	48	0	0
T10	0	54	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	16	0	0
T16	719	0	0	0
T17	10947	46	0	0
T26	656	0	0	0
T30	0	22	0	0
T37	0	46	0	0
T39	0	13	0	0
T62	0	10	0	0
T63	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	108098	0	0
T2	9174	1878	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	888	0	0
T10	0	2025	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	1179	0	0
T16	719	0	0	0
T17	10947	2110	0	0
T26	656	0	0	0
T30	0	957	0	0
T37	0	1309	0	0
T39	0	1677	0	0
T62	0	245	0	0
T63	0	1485	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8883819	0	0
T1	21977	13690	0	0
T2	9174	8707	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23562	0	0
T16	719	318	0	0
T17	10947	10492	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	358	0	0
T5	19188	0	0	0
T6	15542	0	0	0
T17	10947	4	0	0
T26	656	0	0	0
T35	735	0	0	0
T36	14900	0	0	0
T37	5470	23	0	0
T38	434	0	0	0
T43	0	1	0	0
T46	103706	0	0	0
T62	0	5	0	0
T75	0	5	0	0
T78	0	18	0	0
T91	409	0	0	0
T196	0	27	0	0
T220	0	12	0	0
T221	0	23	0	0
T222	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	70262	0	0
T2	9174	2	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1941	0	0
T10	0	1679	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	5	0	0
T26	656	0	0	0
T30	0	2269	0	0
T39	0	7	0	0
T45	0	123	0	0
T63	0	1347	0	0
T78	0	3	0	0
T103	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	834	0	0
T2	9174	2	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	5	0	0
T26	656	0	0	0
T30	0	11	0	0
T39	0	3	0	0
T45	0	5	0	0
T63	0	27	0	0
T78	0	3	0	0
T103	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8432077	0	0
T1	21977	13690	0	0
T2	9174	5352	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	16002	0	0
T16	719	318	0	0
T17	10947	5777	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8434288	0	0
T1	21977	13714	0	0
T2	9174	5353	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	16008	0	0
T16	719	319	0	0
T17	10947	5778	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1468	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	8	0	0
T16	719	0	0	0
T17	10947	23	0	0
T26	656	0	0	0
T30	0	11	0	0
T37	0	23	0	0
T39	0	10	0	0
T62	0	5	0	0
T63	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1416	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	8	0	0
T16	719	0	0	0
T17	10947	23	0	0
T26	656	0	0	0
T30	0	11	0	0
T37	0	23	0	0
T39	0	3	0	0
T62	0	5	0	0
T63	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	834	0	0
T2	9174	2	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	5	0	0
T26	656	0	0	0
T30	0	11	0	0
T39	0	3	0	0
T45	0	5	0	0
T63	0	27	0	0
T78	0	3	0	0
T103	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	834	0	0
T2	9174	2	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	5	0	0
T26	656	0	0	0
T30	0	11	0	0
T39	0	3	0	0
T45	0	5	0	0
T63	0	27	0	0
T78	0	3	0	0
T103	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	69317	0	0
T5	19188	1916	0	0
T6	15542	0	0	0
T7	718	0	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	0	1651	0	0
T30	0	2255	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T38	434	0	0	0
T39	7116	4	0	0
T43	0	329	0	0
T45	0	117	0	0
T63	0	1320	0	0
T91	409	0	0	0
T95	0	82	0	0
T96	0	1294	0	0
T103	0	41	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	711	0	0
T5	19188	23	0	0
T6	15542	0	0	0
T7	718	0	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	0	26	0	0
T30	0	8	0	0
T36	14900	0	0	0
T37	5470	0	0	0
T38	434	0	0	0
T39	7116	3	0	0
T43	0	5	0	0
T45	0	4	0	0
T63	0	27	0	0
T91	409	0	0	0
T96	0	11	0	0
T103	0	21	0	0
T223	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T5,T38

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T5,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T58,T79,T70
1	0	Covered	T43,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T6,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T6
1	-	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T38
DetectSt	168	Covered	T1,T5,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T5,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T6
DebounceSt->IdleSt	163	Covered	T1,T38,T10
DetectSt->IdleSt	186	Covered	T58,T43,T79
DetectSt->StableSt	191	Covered	T1,T5,T6
IdleSt->DebounceSt	148	Covered	T1,T5,T38
StableSt->IdleSt	206	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T38
0	1	Covered	T1,T5,T38
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T38,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T38
DetectSt	-	-	-	-	1	-	-	Covered	T58,T43,T79
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	1098	0	0
CntIncr_A	9556404	54270	0	0
CntNoWrap_A	9556404	8885604	0	0
DetectStDropOut_A	9556404	85	0	0
DetectedOut_A	9556404	17480	0	0
DetectedPulseOut_A	9556404	420	0	0
DisabledIdleSt_A	9556404	8504482	0	0
DisabledNoDetection_A	9556404	8506136	0	0
EnterDebounceSt_A	9556404	591	0	0
EnterDetectSt_A	9556404	509	0	0
EnterStableSt_A	9556404	420	0	0
PulseIsPulse_A	9556404	420	0	0
StayInStableSt	9556404	17033	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	390	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1098	0	0
T1	21977	9	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	2	0	0
T6	0	2	0	0
T10	0	5	0	0
T11	0	23	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T30	0	6	0	0
T38	0	1	0	0
T45	0	2	0	0
T76	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	54270	0	0
T1	21977	205	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	60	0	0
T6	0	116	0	0
T10	0	194	0	0
T11	0	1381	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	40	0	0
T30	0	180	0	0
T38	0	20	0	0
T45	0	29	0	0
T76	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8885604	0	0
T1	21977	13681	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	85	0	0
T33	2941	0	0	0
T34	920	0	0	0
T43	6091	0	0	0
T58	3996	1	0	0
T59	502	0	0	0
T60	507	0	0	0
T61	1212	0	0	0
T70	0	2	0	0
T78	9596	0	0	0
T79	0	9	0	0
T81	0	5	0	0
T82	0	8	0	0
T83	0	1	0	0
T84	0	3	0	0
T85	0	6	0	0
T86	0	4	0	0
T87	0	6	0	0
T92	439	0	0	0
T93	436	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	17480	0	0
T1	21977	62	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	271	0	0
T6	0	57	0	0
T10	0	107	0	0
T11	0	752	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	5	0	0
T30	0	236	0	0
T43	0	109	0	0
T45	0	61	0	0
T94	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	420	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T10	0	2	0	0
T11	0	11	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T94	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8504482	0	0
T1	21977	9015	0	0
T2	9174	8763	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10533	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8506136	0	0
T1	21977	9032	0	0
T2	9174	8765	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10535	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	591	0	0
T1	21977	5	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T11	0	12	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T24	0	2	0	0
T30	0	3	0	0
T38	0	1	0	0
T45	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	509	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T10	0	2	0	0
T11	0	11	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T43	0	3	0	0
T45	0	1	0	0
T58	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	420	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T10	0	2	0	0
T11	0	11	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T94	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	420	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T10	0	2	0	0
T11	0	11	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T94	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	17033	0	0
T1	21977	58	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	269	0	0
T6	0	56	0	0
T10	0	105	0	0
T11	0	741	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T30	0	230	0	0
T43	0	108	0	0
T45	0	59	0	0
T94	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	390	0	0
T1	21977	4	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T6	0	1	0	0
T10	0	2	0	0
T11	0	11	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	1	0	0
T47	0	4	0	0
T51	0	3	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T17
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T17
1	0	Covered	T2,T15,T17
1	1	Covered	T2,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T37,T39,T30
1	0	Covered	T30,T43,T220

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
1	0	Covered	T43,T224

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T17
1	-	Covered	T2,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T17
DetectSt	168	Covered	T2,T15,T17
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T17
DebounceSt->IdleSt	163	Covered	T39,T43,T75
DetectSt->IdleSt	186	Covered	T37,T39,T30
DetectSt->StableSt	191	Covered	T2,T15,T17
IdleSt->DebounceSt	148	Covered	T2,T15,T17
StableSt->IdleSt	206	Covered	T2,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T2,T15,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T43,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T37,T39,T30
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	3292	0	0
CntIncr_A	9556404	116098	0	0
CntNoWrap_A	9556404	8883410	0	0
DetectStDropOut_A	9556404	442	0	0
DetectedOut_A	9556404	88645	0	0
DetectedPulseOut_A	9556404	1025	0	0
DisabledIdleSt_A	9556404	8420048	0	0
DisabledNoDetection_A	9556404	8422239	0	0
EnterDebounceSt_A	9556404	1672	0	0
EnterDetectSt_A	9556404	1621	0	0
EnterStableSt_A	9556404	1025	0	0
PulseIsPulse_A	9556404	1025	0	0
StayInStableSt	9556404	87489	0	0
gen_high_event_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	892	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3292	0	0
T2	9174	58	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	54	0	0
T10	0	54	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	18	0	0
T26	656	0	0	0
T30	0	62	0	0
T37	0	70	0	0
T39	0	26	0	0
T62	0	44	0	0
T63	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	116098	0	0
T2	9174	1595	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1917	0	0
T10	0	1620	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	960	0	0
T16	719	0	0	0
T17	10947	675	0	0
T26	656	0	0	0
T30	0	3824	0	0
T37	0	1997	0	0
T39	0	3092	0	0
T62	0	1094	0	0
T63	0	924	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8883410	0	0
T1	21977	13690	0	0
T2	9174	8707	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23554	0	0
T16	719	318	0	0
T17	10947	10520	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	442	0	0
T6	15542	0	0	0
T7	718	0	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	22062	0	0	0
T30	0	17	0	0
T37	5470	35	0	0
T38	434	0	0	0
T39	7116	8	0	0
T40	656	0	0	0
T43	0	1	0	0
T62	0	22	0	0
T78	0	6	0	0
T91	409	0	0	0
T130	0	2	0	0
T196	0	7	0	0
T220	0	5	0	0
T221	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	88645	0	0
T2	9174	1010	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3815	0	0
T10	0	2925	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	833	0	0
T16	719	0	0	0
T17	10947	165	0	0
T26	656	0	0	0
T43	0	360	0	0
T45	0	979	0	0
T63	0	1593	0	0
T103	0	1093	0	0
T206	0	307	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1025	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T43	0	5	0	0
T45	0	15	0	0
T63	0	22	0	0
T103	0	27	0	0
T206	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8420048	0	0
T1	21977	13690	0	0
T2	9174	4588	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	15964	0	0
T16	719	318	0	0
T17	10947	5752	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8422239	0	0
T1	21977	13714	0	0
T2	9174	4588	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	15970	0	0
T16	719	319	0	0
T17	10947	5753	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1672	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T30	0	31	0	0
T37	0	35	0	0
T39	0	18	0	0
T62	0	22	0	0
T63	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1621	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T30	0	31	0	0
T37	0	35	0	0
T39	0	8	0	0
T62	0	22	0	0
T63	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1025	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T43	0	5	0	0
T45	0	15	0	0
T63	0	22	0	0
T103	0	27	0	0
T206	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1025	0	0
T2	9174	29	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	27	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T43	0	5	0	0
T45	0	15	0	0
T63	0	22	0	0
T103	0	27	0	0
T206	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	87489	0	0
T2	9174	980	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3785	0	0
T10	0	2892	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	821	0	0
T16	719	0	0	0
T17	10947	156	0	0
T26	656	0	0	0
T43	0	355	0	0
T45	0	962	0	0
T63	0	1571	0	0
T103	0	1065	0	0
T206	0	296	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	892	0	0
T2	9174	28	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	24	0	0
T10	0	21	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	9	0	0
T26	656	0	0	0
T43	0	4	0	0
T45	0	13	0	0
T63	0	22	0	0
T103	0	26	0	0
T206	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T47,T66,T225
1	0	Covered	T43,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T5
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T2,T5,T6
DetectSt->IdleSt	186	Covered	T43,T47,T66
DetectSt->StableSt	191	Covered	T1,T2,T5
IdleSt->DebounceSt	148	Covered	T1,T2,T5
StableSt->IdleSt	206	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T5,T6
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	1	-	-	Covered	T43,T47,T66
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	910	0	0
CntIncr_A	9556404	49482	0	0
CntNoWrap_A	9556404	8885792	0	0
DetectStDropOut_A	9556404	73	0	0
DetectedOut_A	9556404	18442	0	0
DetectedPulseOut_A	9556404	350	0	0
DisabledIdleSt_A	9556404	8493306	0	0
DisabledNoDetection_A	9556404	8495024	0	0
EnterDebounceSt_A	9556404	484	0	0
EnterDetectSt_A	9556404	428	0	0
EnterStableSt_A	9556404	350	0	0
PulseIsPulse_A	9556404	350	0	0
StayInStableSt	9556404	18056	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	314	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	910	0	0
T1	21977	6	0	0
T2	9174	3	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	7	0	0
T6	0	7	0	0
T10	0	12	0	0
T11	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	8	0	0
T43	0	8	0	0
T63	0	8	0	0
T103	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	49482	0	0
T1	21977	264	0	0
T2	9174	94	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	251	0	0
T6	0	555	0	0
T10	0	498	0	0
T11	0	134	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	646	0	0
T43	0	175	0	0
T63	0	224	0	0
T103	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8885792	0	0
T1	21977	13684	0	0
T2	9174	8762	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23578	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	73	0	0
T32	2518	0	0	0
T47	26538	3	0	0
T48	85535	0	0	0
T54	492	0	0	0
T55	494	0	0	0
T66	0	7	0	0
T75	4466	0	0	0
T85	0	2	0	0
T86	0	1	0	0
T124	1057	0	0	0
T127	0	3	0	0
T202	539	0	0	0
T203	720	0	0	0
T225	0	1	0	0
T226	0	5	0	0
T227	0	3	0	0
T228	0	10	0	0
T229	0	3	0	0
T230	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	18442	0	0
T1	21977	222	0	0
T2	9174	41	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	768	0	0
T6	0	13	0	0
T10	0	301	0	0
T11	0	52	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	45	0	0
T43	0	109	0	0
T63	0	357	0	0
T103	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	350	0	0
T1	21977	3	0	0
T2	9174	1	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	1	0	0
T63	0	4	0	0
T103	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8493306	0	0
T1	21977	9269	0	0
T2	9174	7756	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	22745	0	0
T16	719	318	0	0
T17	10947	10373	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8495024	0	0
T1	21977	9290	0	0
T2	9174	7757	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	22752	0	0
T16	719	319	0	0
T17	10947	10375	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	484	0	0
T1	21977	3	0	0
T2	9174	2	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	4	0	0
T6	0	4	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	5	0	0
T63	0	4	0	0
T103	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	428	0	0
T1	21977	3	0	0
T2	9174	1	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	3	0	0
T63	0	4	0	0
T103	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	350	0	0
T1	21977	3	0	0
T2	9174	1	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	1	0	0
T63	0	4	0	0
T103	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	350	0	0
T1	21977	3	0	0
T2	9174	1	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	3	0	0
T6	0	3	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	1	0	0
T63	0	4	0	0
T103	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	18056	0	0
T1	21977	219	0	0
T2	9174	40	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	763	0	0
T6	0	10	0	0
T10	0	295	0	0
T11	0	51	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	41	0	0
T43	0	108	0	0
T63	0	353	0	0
T103	0	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	314	0	0
T1	21977	3	0	0
T2	9174	1	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	3	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	4	0	0
T43	0	1	0	0
T63	0	4	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T17
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T17
1	0	Covered	T2,T15,T17
1	1	Covered	T2,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T37,T39,T62
1	0	Covered	T63,T103,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
1	0	Covered	T30,T231

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T17
1	-	Covered	T2,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T17
DetectSt	168	Covered	T2,T15,T17
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T17
DebounceSt->IdleSt	163	Covered	T39,T43,T75
DetectSt->IdleSt	186	Covered	T37,T39,T62
DetectSt->StableSt	191	Covered	T2,T15,T17
IdleSt->DebounceSt	148	Covered	T2,T15,T17
StableSt->IdleSt	206	Covered	T2,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T2,T15,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T43,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T37,T39,T62
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	3133	0	0
CntIncr_A	9556404	110705	0	0
CntNoWrap_A	9556404	8883569	0	0
DetectStDropOut_A	9556404	449	0	0
DetectedOut_A	9556404	84870	0	0
DetectedPulseOut_A	9556404	942	0	0
DisabledIdleSt_A	9556404	8422304	0	0
DisabledNoDetection_A	9556404	8424512	0	0
EnterDebounceSt_A	9556404	1585	0	0
EnterDetectSt_A	9556404	1548	0	0
EnterStableSt_A	9556404	942	0	0
PulseIsPulse_A	9556404	942	0	0
StayInStableSt	9556404	83814	0	0
gen_high_event_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	796	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3133	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	22	0	0
T10	0	10	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	48	0	0
T16	719	0	0	0
T17	10947	42	0	0
T26	656	0	0	0
T30	0	22	0	0
T37	0	30	0	0
T39	0	13	0	0
T62	0	54	0	0
T63	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	110705	0	0
T2	9174	228	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	583	0	0
T10	0	420	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	1800	0	0
T16	719	0	0	0
T17	10947	1197	0	0
T26	656	0	0	0
T30	0	539	0	0
T37	0	846	0	0
T39	0	1544	0	0
T62	0	1348	0	0
T63	0	1409	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8883569	0	0
T1	21977	13690	0	0
T2	9174	8757	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23530	0	0
T16	719	318	0	0
T17	10947	10496	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	449	0	0
T6	15542	0	0	0
T7	718	0	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	22062	0	0	0
T37	5470	15	0	0
T38	434	0	0	0
T39	7116	4	0	0
T40	656	0	0	0
T43	0	1	0	0
T62	0	27	0	0
T63	0	9	0	0
T75	0	1	0	0
T91	409	0	0	0
T196	0	10	0	0
T221	0	15	0	0
T232	0	5	0	0
T233	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	84870	0	0
T2	9174	38	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	928	0	0
T10	0	84	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3599	0	0
T16	719	0	0	0
T17	10947	2425	0	0
T26	656	0	0	0
T30	0	825	0	0
T43	0	341	0	0
T45	0	1030	0	0
T78	0	1586	0	0
T206	0	409	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	942	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	11	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	21	0	0
T26	656	0	0	0
T30	0	11	0	0
T43	0	5	0	0
T45	0	27	0	0
T78	0	13	0	0
T206	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8422304	0	0
T1	21977	13690	0	0
T2	9174	5334	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	14135	0	0
T16	719	318	0	0
T17	10947	4059	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8424512	0	0
T1	21977	13714	0	0
T2	9174	5335	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	14135	0	0
T16	719	319	0	0
T17	10947	4059	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1585	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	11	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	21	0	0
T26	656	0	0	0
T30	0	11	0	0
T37	0	15	0	0
T39	0	9	0	0
T62	0	27	0	0
T63	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1548	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	11	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	21	0	0
T26	656	0	0	0
T30	0	11	0	0
T37	0	15	0	0
T39	0	4	0	0
T62	0	27	0	0
T63	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	942	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	11	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	21	0	0
T26	656	0	0	0
T30	0	11	0	0
T43	0	5	0	0
T45	0	27	0	0
T78	0	13	0	0
T206	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	942	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	11	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	21	0	0
T26	656	0	0	0
T30	0	11	0	0
T43	0	5	0	0
T45	0	27	0	0
T78	0	13	0	0
T206	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	83814	0	0
T2	9174	34	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	916	0	0
T10	0	79	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3569	0	0
T16	719	0	0	0
T17	10947	2403	0	0
T26	656	0	0	0
T30	0	814	0	0
T43	0	336	0	0
T45	0	1000	0	0
T78	0	1572	0	0
T206	0	399	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	796	0	0
T2	9174	4	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	10	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	18	0	0
T16	719	0	0	0
T17	10947	20	0	0
T26	656	0	0	0
T43	0	5	0	0
T45	0	24	0	0
T78	0	12	0	0
T206	0	6	0	0
T220	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T17
0	1	Covered	T47,T79,T234
1	0	Covered	T43,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T17
0	1	Covered	T1,T5,T6
1	0	Covered	T43,T67,T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T17
1	-	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T17
DetectSt	168	Covered	T1,T15,T17
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T17
DebounceSt->IdleSt	163	Covered	T1,T43,T47
DetectSt->IdleSt	186	Covered	T43,T47,T79
DetectSt->StableSt	191	Covered	T1,T15,T17
IdleSt->DebounceSt	148	Covered	T1,T15,T17
StableSt->IdleSt	206	Covered	T1,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T17
0	1	Covered	T1,T15,T17
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T47,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T43,T47,T79
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	901	0	0
CntIncr_A	9556404	45811	0	0
CntNoWrap_A	9556404	8885801	0	0
DetectStDropOut_A	9556404	105	0	0
DetectedOut_A	9556404	15881	0	0
DetectedPulseOut_A	9556404	316	0	0
DisabledIdleSt_A	9556404	8504500	0	0
DisabledNoDetection_A	9556404	8506242	0	0
EnterDebounceSt_A	9556404	477	0	0
EnterDetectSt_A	9556404	425	0	0
EnterStableSt_A	9556404	316	0	0
PulseIsPulse_A	9556404	316	0	0
StayInStableSt	9556404	15534	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	282	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	901	0	0
T1	21977	27	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	2	0	0
T6	0	2	0	0
T11	0	2	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	2	0	0
T29	0	14	0	0
T43	0	8	0	0
T45	0	6	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	45811	0	0
T1	21977	1281	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	72	0	0
T6	0	91	0	0
T11	0	173	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	255	0	0
T16	719	0	0	0
T17	10947	92	0	0
T29	0	676	0	0
T43	0	161	0	0
T45	0	111	0	0
T78	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8885801	0	0
T1	21977	13663	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23572	0	0
T16	719	318	0	0
T17	10947	10536	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	105	0	0
T32	2518	0	0	0
T47	26538	5	0	0
T48	85535	0	0	0
T54	492	0	0	0
T55	494	0	0	0
T75	4466	0	0	0
T79	0	10	0	0
T82	0	4	0	0
T86	0	3	0	0
T87	0	10	0	0
T124	1057	0	0	0
T127	0	5	0	0
T202	539	0	0	0
T203	720	0	0	0
T229	0	6	0	0
T230	526	0	0	0
T234	0	3	0	0
T235	0	5	0	0
T236	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	15881	0	0
T1	21977	901	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	260	0	0
T6	0	82	0	0
T11	0	13	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	73	0	0
T16	719	0	0	0
T17	10947	54	0	0
T29	0	522	0	0
T43	0	110	0	0
T45	0	159	0	0
T78	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	316	0	0
T1	21977	12	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3	0	0
T16	719	0	0	0
T17	10947	1	0	0
T29	0	7	0	0
T43	0	1	0	0
T45	0	3	0	0
T78	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8504500	0	0
T1	21977	9269	0	0
T2	9174	8727	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	19985	0	0
T16	719	318	0	0
T17	10947	8114	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8506242	0	0
T1	21977	9290	0	0
T2	9174	8729	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	19986	0	0
T16	719	319	0	0
T17	10947	8115	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	477	0	0
T1	21977	15	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3	0	0
T16	719	0	0	0
T17	10947	1	0	0
T29	0	7	0	0
T43	0	5	0	0
T45	0	3	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	425	0	0
T1	21977	12	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3	0	0
T16	719	0	0	0
T17	10947	1	0	0
T29	0	7	0	0
T43	0	3	0	0
T45	0	3	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	316	0	0
T1	21977	12	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3	0	0
T16	719	0	0	0
T17	10947	1	0	0
T29	0	7	0	0
T43	0	1	0	0
T45	0	3	0	0
T78	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	316	0	0
T1	21977	12	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3	0	0
T16	719	0	0	0
T17	10947	1	0	0
T29	0	7	0	0
T43	0	1	0	0
T45	0	3	0	0
T78	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	15534	0	0
T1	21977	889	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	259	0	0
T6	0	81	0	0
T11	0	12	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	67	0	0
T16	719	0	0	0
T17	10947	52	0	0
T29	0	515	0	0
T43	0	109	0	0
T45	0	153	0	0
T78	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	282	0	0
T1	21977	12	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T11	0	1	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	7	0	0
T47	0	2	0	0
T51	0	2	0	0
T94	0	6	0	0
T96	0	1	0	0
T206	0	1	0	0