Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T17
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T17
1	0	Covered	T2,T15,T17
1	1	Covered	T2,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T37,T39,T62
1	0	Covered	T5,T63,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
1	0	Covered	T237

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T17
1	-	Covered	T2,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T17
DetectSt	168	Covered	T2,T15,T17
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T17
DebounceSt->IdleSt	163	Covered	T39,T43,T75
DetectSt->IdleSt	186	Covered	T5,T37,T39
DetectSt->StableSt	191	Covered	T2,T15,T17
IdleSt->DebounceSt	148	Covered	T2,T15,T17
StableSt->IdleSt	206	Covered	T2,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T17
0	1	Covered	T2,T15,T17
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T2,T15,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T43,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T5,T37,T39
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T2,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	3036	0	0
CntIncr_A	9556404	106206	0	0
CntNoWrap_A	9556404	8883666	0	0
DetectStDropOut_A	9556404	385	0	0
DetectedOut_A	9556404	73404	0	0
DetectedPulseOut_A	9556404	852	0	0
DisabledIdleSt_A	9556404	8431379	0	0
DisabledNoDetection_A	9556404	8433587	0	0
EnterDebounceSt_A	9556404	1545	0	0
EnterDetectSt_A	9556404	1493	0	0
EnterStableSt_A	9556404	852	0	0
PulseIsPulse_A	9556404	852	0	0
StayInStableSt	9556404	72438	0	0
gen_high_event_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	737	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	3036	0	0
T2	9174	16	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	54	0	0
T10	0	10	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	48	0	0
T16	719	0	0	0
T17	10947	24	0	0
T26	656	0	0	0
T30	0	28	0	0
T37	0	46	0	0
T39	0	16	0	0
T62	0	30	0	0
T63	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	106206	0	0
T2	9174	328	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	1994	0	0
T10	0	385	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	2208	0	0
T16	719	0	0	0
T17	10947	696	0	0
T26	656	0	0	0
T30	0	1218	0	0
T37	0	1317	0	0
T39	0	1982	0	0
T62	0	743	0	0
T63	0	1409	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8883666	0	0
T1	21977	13690	0	0
T2	9174	8749	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23530	0	0
T16	719	318	0	0
T17	10947	10514	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	385	0	0
T6	15542	0	0	0
T7	718	0	0	0
T8	1110	0	0	0
T9	505	0	0	0
T10	22062	0	0	0
T37	5470	23	0	0
T38	434	0	0	0
T39	7116	5	0	0
T40	656	0	0	0
T43	0	1	0	0
T62	0	15	0	0
T63	0	9	0	0
T75	0	9	0	0
T78	0	3	0	0
T91	409	0	0	0
T220	0	12	0	0
T221	0	4	0	0
T222	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	73404	0	0
T2	9174	752	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	118	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3191	0	0
T16	719	0	0	0
T17	10947	427	0	0
T26	656	0	0	0
T30	0	1975	0	0
T43	0	312	0	0
T45	0	1341	0	0
T96	0	1229	0	0
T103	0	245	0	0
T206	0	1091	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	852	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	14	0	0
T43	0	5	0	0
T45	0	29	0	0
T96	0	13	0	0
T103	0	16	0	0
T206	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8431379	0	0
T1	21977	13690	0	0
T2	9174	4779	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	14135	0	0
T16	719	318	0	0
T17	10947	5737	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8433587	0	0
T1	21977	13714	0	0
T2	9174	4780	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	14135	0	0
T16	719	319	0	0
T17	10947	5738	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1545	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	14	0	0
T37	0	23	0	0
T39	0	12	0	0
T62	0	15	0	0
T63	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	1493	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T5	0	27	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	14	0	0
T37	0	23	0	0
T39	0	5	0	0
T62	0	15	0	0
T63	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	852	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	14	0	0
T43	0	5	0	0
T45	0	29	0	0
T96	0	13	0	0
T103	0	16	0	0
T206	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	852	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	24	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	14	0	0
T43	0	5	0	0
T45	0	29	0	0
T96	0	13	0	0
T103	0	16	0	0
T206	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72438	0	0
T2	9174	744	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	113	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	3161	0	0
T16	719	0	0	0
T17	10947	415	0	0
T26	656	0	0	0
T30	0	1956	0	0
T43	0	307	0	0
T45	0	1309	0	0
T96	0	1214	0	0
T103	0	229	0	0
T206	0	1075	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	737	0	0
T2	9174	8	0	0
T3	160979	0	0	0
T4	521	0	0	0
T10	0	5	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	18	0	0
T16	719	0	0	0
T17	10947	12	0	0
T26	656	0	0	0
T30	0	9	0	0
T43	0	5	0	0
T45	0	26	0	0
T96	0	11	0	0
T103	0	16	0	0
T206	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T15,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T15,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T15,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T15,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T11
0	1	Covered	T238,T127,T239
1	0	Covered	T43,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T11
0	1	Covered	T1,T11,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T11
1	-	Covered	T1,T11,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T11
DetectSt	168	Covered	T1,T15,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T15,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T11
DebounceSt->IdleSt	163	Covered	T11,T43,T47
DetectSt->IdleSt	186	Covered	T43,T238,T127
DetectSt->StableSt	191	Covered	T1,T15,T11
IdleSt->DebounceSt	148	Covered	T1,T15,T11
StableSt->IdleSt	206	Covered	T1,T15,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T15,T11
0	1	Covered	T1,T15,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T43,T44
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T96,T79
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T11
DetectSt	-	-	-	-	1	-	-	Covered	T43,T238,T127
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9556404	757	0	0
CntIncr_A	9556404	37102	0	0
CntNoWrap_A	9556404	8885945	0	0
DetectStDropOut_A	9556404	72	0	0
DetectedOut_A	9556404	12805	0	0
DetectedPulseOut_A	9556404	278	0	0
DisabledIdleSt_A	9556404	8527651	0	0
DisabledNoDetection_A	9556404	8529412	0	0
EnterDebounceSt_A	9556404	405	0	0
EnterDetectSt_A	9556404	353	0	0
EnterStableSt_A	9556404	278	0	0
PulseIsPulse_A	9556404	278	0	0
StayInStableSt	9556404	12503	0	0
gen_high_level_sva.HighLevelEvent_A	9556404	8889118	0	0
gen_not_sticky_sva.StableStDropOut_A	9556404	251	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	757	0	0
T1	21977	2	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	7	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	12	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	6	0	0
T30	0	4	0	0
T43	0	8	0	0
T45	0	2	0	0
T47	0	4	0	0
T58	0	2	0	0
T94	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	37102	0	0
T1	21977	141	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	464	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	498	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	396	0	0
T30	0	180	0	0
T43	0	131	0	0
T45	0	35	0	0
T47	0	341	0	0
T58	0	70	0	0
T94	0	190	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8885945	0	0
T1	21977	13688	0	0
T2	9174	8765	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	23566	0	0
T16	719	318	0	0
T17	10947	10538	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	72	0	0
T44	0	1	0	0
T69	21267	0	0	0
T87	0	6	0	0
T127	0	9	0	0
T151	2135	0	0	0
T157	769	0	0	0
T158	892	0	0	0
T159	524	0	0	0
T160	425	0	0	0
T161	29672	0	0	0
T162	404	0	0	0
T163	1078	0	0	0
T226	0	2	0	0
T238	27352	9	0	0
T239	0	3	0	0
T240	0	7	0	0
T241	0	3	0	0
T242	0	2	0	0
T243	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	12805	0	0
T1	21977	21	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	175	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	159	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	111	0	0
T30	0	99	0	0
T43	0	110	0	0
T45	0	57	0	0
T47	0	76	0	0
T58	0	6	0	0
T94	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	278	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T58	0	1	0	0
T94	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8527651	0	0
T1	21977	9269	0	0
T2	9174	8013	0	0
T3	160979	160578	0	0
T4	521	120	0	0
T12	435	34	0	0
T13	523	122	0	0
T14	454	53	0	0
T15	24026	20393	0	0
T16	719	318	0	0
T17	10947	10111	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8529412	0	0
T1	21977	9290	0	0
T2	9174	8015	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	20394	0	0
T16	719	319	0	0
T17	10947	10113	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	405	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	4	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T43	0	5	0	0
T45	0	1	0	0
T47	0	3	0	0
T58	0	1	0	0
T94	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	353	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T43	0	3	0	0
T45	0	1	0	0
T47	0	2	0	0
T58	0	1	0	0
T94	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	278	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T58	0	1	0	0
T94	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	278	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	6	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T58	0	1	0	0
T94	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	12503	0	0
T1	21977	20	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	172	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	147	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	108	0	0
T30	0	97	0	0
T43	0	109	0	0
T45	0	56	0	0
T47	0	74	0	0
T58	0	4	0	0
T94	0	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	8889118	0	0
T1	21977	13714	0	0
T2	9174	8767	0	0
T3	160979	160579	0	0
T4	521	121	0	0
T12	435	35	0	0
T13	523	123	0	0
T14	454	54	0	0
T15	24026	23585	0	0
T16	719	319	0	0
T17	10947	10540	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9556404	251	0	0
T1	21977	1	0	0
T2	9174	0	0	0
T3	160979	0	0	0
T4	521	0	0	0
T11	0	3	0	0
T12	435	0	0	0
T13	523	0	0	0
T14	454	0	0	0
T15	24026	0	0	0
T16	719	0	0	0
T17	10947	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T94	0	2	0	0
T96	0	1	0	0
T190	0	1	0	0
T206	0	2	0	0