Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1067111485	11531	0	0
auto_block_debounce_ctl_rd_A	1067111485	2315	0	0
auto_block_out_ctl_rd_A	1067111485	3191	0	0
com_det_ctl_0_rd_A	1067111485	4611	0	0
com_det_ctl_1_rd_A	1067111485	4610	0	0
com_det_ctl_2_rd_A	1067111485	4770	0	0
com_det_ctl_3_rd_A	1067111485	4741	0	0
com_out_ctl_0_rd_A	1067111485	5090	0	0
com_out_ctl_1_rd_A	1067111485	5282	0	0
com_out_ctl_2_rd_A	1067111485	5258	0	0
com_out_ctl_3_rd_A	1067111485	5349	0	0
com_pre_det_ctl_0_rd_A	1067111485	1748	0	0
com_pre_det_ctl_1_rd_A	1067111485	1974	0	0
com_pre_det_ctl_2_rd_A	1067111485	1993	0	0
com_pre_det_ctl_3_rd_A	1067111485	1831	0	0
com_pre_sel_ctl_0_rd_A	1067111485	5466	0	0
com_pre_sel_ctl_1_rd_A	1067111485	5456	0	0
com_pre_sel_ctl_2_rd_A	1067111485	5676	0	0
com_pre_sel_ctl_3_rd_A	1067111485	5423	0	0
com_sel_ctl_0_rd_A	1067111485	5568	0	0
com_sel_ctl_1_rd_A	1067111485	5183	0	0
com_sel_ctl_2_rd_A	1067111485	5856	0	0
com_sel_ctl_3_rd_A	1067111485	5686	0	0
ec_rst_ctl_rd_A	1067111485	3033	0	0
intr_enable_rd_A	1067111485	2829	0	0
key_intr_ctl_rd_A	1067111485	4849	0	0
key_intr_debounce_ctl_rd_A	1067111485	1800	0	0
key_invert_ctl_rd_A	1067111485	6556	0	0
pin_allowed_ctl_rd_A	1067111485	8206	0	0
pin_out_ctl_rd_A	1067111485	5721	0	0
pin_out_value_rd_A	1067111485	5658	0	0
regwen_rd_A	1067111485	2623	0	0
ulp_ac_debounce_ctl_rd_A	1067111485	1928	0	0
ulp_ctl_rd_A	1067111485	2069	0	0
ulp_lid_debounce_ctl_rd_A	1067111485	2025	0	0
ulp_pwrb_debounce_ctl_rd_A	1067111485	2099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	11531	0	0
T1	531792	16	0	0
T2	206410	0	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T24	0	14	0	0
T29	0	15	0	0
T47	0	16	0	0
T50	0	8	0	0
T51	0	6	0	0
T58	0	6	0	0
T64	0	11	0	0
T98	0	11	0	0
T190	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2315	0	0
T64	0	6	0	0
T68	777122	12	0	0
T96	655267	0	0	0
T109	0	27	0	0
T111	0	1	0	0
T134	78535	0	0	0
T190	120978	0	0	0
T222	589250	0	0	0
T267	78460	13	0	0
T268	0	17	0	0
T269	0	7	0	0
T270	0	35	0	0
T271	0	41	0	0
T272	0	3	0	0
T273	131262	0	0	0
T274	246847	0	0	0
T275	169714	0	0	0
T276	55620	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	3191	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	7	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	16	0	0
T68	0	4	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	23	0	0
T111	0	5	0	0
T267	0	11	0	0
T268	0	10	0	0
T269	0	16	0	0
T270	0	44	0	0
T271	0	29	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	4611	0	0
T2	206410	59	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	65	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	73	0	0
T58	0	18	0	0
T64	0	17	0	0
T78	0	32	0	0
T94	0	62	0	0
T103	0	27	0	0
T220	0	20	0	0
T277	0	42	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	4610	0	0
T2	206410	54	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	72	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	55	0	0
T58	0	25	0	0
T64	0	25	0	0
T78	0	40	0	0
T94	0	53	0	0
T103	0	40	0	0
T220	0	42	0	0
T277	0	40	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	4770	0	0
T2	206410	49	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	70	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	56	0	0
T58	0	6	0	0
T64	0	17	0	0
T78	0	27	0	0
T94	0	51	0	0
T103	0	41	0	0
T220	0	26	0	0
T277	0	30	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	4741	0	0
T2	206410	42	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	75	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	78	0	0
T58	0	15	0	0
T64	0	9	0	0
T78	0	47	0	0
T94	0	81	0	0
T103	0	39	0	0
T220	0	28	0	0
T277	0	22	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5090	0	0
T2	206410	44	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	72	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	60	0	0
T58	0	17	0	0
T64	0	19	0	0
T78	0	50	0	0
T94	0	85	0	0
T103	0	39	0	0
T220	0	46	0	0
T277	0	56	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5282	0	0
T2	206410	27	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	50	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	65	0	0
T58	0	14	0	0
T64	0	33	0	0
T78	0	25	0	0
T94	0	78	0	0
T103	0	33	0	0
T220	0	28	0	0
T277	0	52	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5258	0	0
T2	206410	36	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	74	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	60	0	0
T58	0	21	0	0
T64	0	26	0	0
T78	0	49	0	0
T94	0	74	0	0
T103	0	27	0	0
T220	0	27	0	0
T277	0	54	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5349	0	0
T2	206410	34	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	43	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	69	0	0
T58	0	17	0	0
T64	0	14	0	0
T78	0	26	0	0
T94	0	69	0	0
T103	0	38	0	0
T220	0	29	0	0
T277	0	41	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1748	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	5	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	15	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	30	0	0
T120	0	12	0	0
T173	0	21	0	0
T174	0	11	0	0
T226	0	10	0	0
T270	0	23	0	0
T271	0	41	0	0
T278	0	2	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1974	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	9	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	23	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	24	0	0
T120	0	3	0	0
T173	0	19	0	0
T174	0	21	0	0
T226	0	3	0	0
T270	0	28	0	0
T271	0	24	0	0
T278	0	7	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1993	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	18	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	23	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	17	0	0
T120	0	17	0	0
T173	0	25	0	0
T174	0	13	0	0
T178	0	12	0	0
T226	0	7	0	0
T270	0	34	0	0
T271	0	34	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1831	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	16	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	16	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	24	0	0
T120	0	6	0	0
T125	0	4	0	0
T173	0	16	0	0
T174	0	13	0	0
T226	0	11	0	0
T270	0	38	0	0
T271	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5466	0	0
T2	206410	35	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	81	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	88	0	0
T58	0	12	0	0
T64	0	17	0	0
T78	0	29	0	0
T94	0	66	0	0
T103	0	24	0	0
T220	0	53	0	0
T277	0	25	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5456	0	0
T2	206410	31	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	94	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	75	0	0
T58	0	21	0	0
T64	0	18	0	0
T78	0	35	0	0
T94	0	65	0	0
T103	0	19	0	0
T220	0	7	0	0
T277	0	52	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5676	0	0
T2	206410	43	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	95	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	58	0	0
T58	0	19	0	0
T64	0	18	0	0
T78	0	32	0	0
T94	0	72	0	0
T103	0	32	0	0
T220	0	22	0	0
T277	0	63	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5423	0	0
T2	206410	33	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	66	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	71	0	0
T58	0	15	0	0
T64	0	26	0	0
T78	0	41	0	0
T94	0	60	0	0
T103	0	43	0	0
T220	0	24	0	0
T277	0	55	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5568	0	0
T2	206410	29	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	80	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	67	0	0
T58	0	17	0	0
T64	0	12	0	0
T78	0	27	0	0
T94	0	74	0	0
T103	0	38	0	0
T220	0	12	0	0
T277	0	34	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5183	0	0
T2	206410	28	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	53	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	56	0	0
T58	0	18	0	0
T64	0	19	0	0
T78	0	40	0	0
T94	0	40	0	0
T103	0	32	0	0
T220	0	57	0	0
T277	0	38	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5856	0	0
T2	206410	43	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	86	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	84	0	0
T58	0	15	0	0
T64	0	12	0	0
T78	0	58	0	0
T94	0	61	0	0
T103	0	37	0	0
T220	0	20	0	0
T277	0	50	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5686	0	0
T2	206410	25	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	85	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T45	0	70	0	0
T58	0	13	0	0
T64	0	16	0	0
T78	0	54	0	0
T94	0	82	0	0
T103	0	43	0	0
T220	0	37	0	0
T277	0	40	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	3033	0	0
T2	206410	10	0	0
T3	218574	0	0	0
T4	253364	0	0	0
T6	0	14	0	0
T12	23916	0	0	0
T13	125575	0	0	0
T14	25026	0	0	0
T15	300340	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T37	0	1	0	0
T45	0	23	0	0
T58	0	25	0	0
T78	0	2	0	0
T94	0	27	0	0
T103	0	6	0	0
T202	0	2	0	0
T203	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2829	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	17	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	40	0	0
T72	0	27	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	38	0	0
T226	0	9	0	0
T270	0	30	0	0
T271	0	24	0	0
T278	0	30	0	0
T279	0	20	0	0
T280	0	33	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	4849	0	0
T9	252862	5	0	0
T10	540541	0	0	0
T11	149695	0	0	0
T25	56836	0	0	0
T30	100110	0	0	0
T40	193711	0	0	0
T41	331247	0	0	0
T42	85176	0	0	0
T58	0	16	0	0
T62	253283	0	0	0
T64	0	21	0	0
T77	204680	0	0	0
T122	0	2	0	0
T139	0	4	0	0
T151	0	6	0	0
T167	0	1	0	0
T197	0	3	0	0
T270	0	35	0	0
T271	0	27	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1800	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	2	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	30	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	50	0	0
T120	0	9	0	0
T173	0	19	0	0
T174	0	26	0	0
T178	0	12	0	0
T226	0	4	0	0
T270	0	34	0	0
T271	0	24	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	6556	0	0
T34	460228	0	0	0
T52	59951	59	0	0
T53	236396	54	0	0
T54	0	69	0	0
T56	0	35	0	0
T57	261443	0	0	0
T58	439622	18	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T64	0	204	0	0
T76	108798	0	0	0
T92	22004	0	0	0
T105	332867	0	0	0
T274	0	62	0	0
T281	0	140	0	0
T282	0	54	0	0
T283	0	30	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	8206	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	20	0	0
T59	246181	0	0	0
T60	55844	83	0	0
T61	199458	0	0	0
T64	0	80	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T172	0	68	0	0
T201	0	19	0	0
T270	0	190	0	0
T277	0	53	0	0
T284	0	97	0	0
T285	0	58	0	0
T286	0	150	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5721	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	2	0	0
T59	246181	0	0	0
T60	55844	86	0	0
T61	199458	0	0	0
T64	0	87	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T172	0	64	0	0
T201	0	45	0	0
T270	0	178	0	0
T277	0	28	0	0
T284	0	72	0	0
T285	0	68	0	0
T286	0	143	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	5658	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	2	0	0
T59	246181	0	0	0
T60	55844	61	0	0
T61	199458	0	0	0
T64	0	48	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T172	0	65	0	0
T201	0	61	0	0
T270	0	160	0	0
T277	0	22	0	0
T284	0	86	0	0
T285	0	69	0	0
T286	0	147	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2623	0	0
T33	706382	0	0	0
T34	460228	0	0	0
T43	151214	0	0	0
T58	439622	15	0	0
T59	246181	0	0	0
T60	55844	0	0	0
T61	199458	0	0	0
T64	0	23	0	0
T78	235126	0	0	0
T92	22004	0	0	0
T93	21826	0	0	0
T109	0	25	0	0
T173	0	9	0	0
T174	0	7	0	0
T178	0	14	0	0
T226	0	9	0	0
T270	0	47	0	0
T271	0	29	0	0
T278	0	9	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	1928	0	0
T3	218574	8	0	0
T5	844295	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T35	91889	0	0	0
T36	260767	0	0	0
T37	683761	0	0	0
T46	243703	0	0	0
T58	0	19	0	0
T64	0	29	0	0
T72	0	3	0	0
T91	49154	0	0	0
T109	0	37	0	0
T270	0	51	0	0
T271	0	28	0	0
T287	0	2	0	0
T288	0	1	0	0
T289	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2069	0	0
T3	218574	7	0	0
T5	844295	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T35	91889	0	0	0
T36	260767	0	0	0
T37	683761	0	0	0
T46	243703	0	0	0
T58	0	14	0	0
T64	0	55	0	0
T72	0	4	0	0
T91	49154	0	0	0
T109	0	39	0	0
T270	0	49	0	0
T271	0	32	0	0
T287	0	5	0	0
T288	0	3	0	0
T289	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2025	0	0
T3	218574	9	0	0
T5	844295	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T35	91889	0	0	0
T36	260767	0	0	0
T37	683761	0	0	0
T46	243703	0	0	0
T58	0	10	0	0
T64	0	54	0	0
T72	0	3	0	0
T91	49154	0	0	0
T109	0	24	0	0
T270	0	36	0	0
T271	0	34	0	0
T278	0	1	0	0
T287	0	3	0	0
T290	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067111485	2099	0	0
T3	218574	7	0	0
T5	844295	0	0	0
T16	345735	0	0	0
T17	268234	0	0	0
T26	78723	0	0	0
T35	91889	0	0	0
T36	260767	0	0	0
T37	683761	0	0	0
T46	243703	0	0	0
T58	0	22	0	0
T64	0	29	0	0
T72	0	4	0	0
T91	49154	0	0	0
T109	0	31	0	0
T270	0	44	0	0
T271	0	31	0	0
T278	0	3	0	0
T287	0	7	0	0
T288	0	5	0	0