Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.28 99.44 96.83 100.00 98.72 98.89 99.81 94.27


Total tests in report: 913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
56.84 56.84 75.61 75.61 64.59 64.59 90.53 90.53 11.54 11.54 76.89 76.89 64.55 64.55 14.20 14.20 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.271961734
76.06 19.22 90.17 14.55 83.34 18.76 95.55 5.02 53.21 41.67 91.20 14.31 85.36 20.81 33.60 19.40 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2772671072
81.48 5.42 92.82 2.65 86.98 3.64 95.78 0.23 60.26 7.05 93.57 2.37 91.04 5.68 49.89 16.30 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3605736738
85.39 3.91 95.89 3.08 89.89 2.91 96.58 0.80 68.59 8.33 95.60 2.03 94.80 3.76 56.36 6.47 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2830839166
88.32 2.93 96.31 0.41 90.19 0.30 96.58 0.00 72.44 3.85 95.97 0.37 95.86 1.06 70.87 14.51 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.29971400
90.40 2.09 97.35 1.04 91.76 1.57 96.58 0.00 83.33 10.90 97.08 1.11 95.86 0.00 70.87 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3867765728
91.65 1.24 97.37 0.02 92.90 1.14 97.26 0.68 83.33 0.00 97.12 0.04 95.86 0.00 77.71 6.83 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3597664916
92.51 0.86 97.85 0.49 93.38 0.48 97.26 0.00 86.54 3.21 97.60 0.48 97.11 1.25 77.81 0.11 /workspace/coverage/default/2.sysrst_ctrl_stress_all.2407685994
93.18 0.67 98.00 0.15 93.53 0.15 97.26 0.00 88.46 1.92 97.71 0.11 97.30 0.19 79.97 2.16 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3433506140
93.73 0.55 98.32 0.32 94.01 0.48 97.60 0.34 90.38 1.92 97.89 0.18 97.59 0.29 80.28 0.32 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2755434141
94.24 0.52 98.45 0.13 94.24 0.23 97.60 0.00 90.38 0.00 97.89 0.00 97.59 0.00 83.54 3.26 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.138148257
94.59 0.34 98.54 0.09 94.39 0.15 97.72 0.11 91.67 1.28 97.97 0.07 97.59 0.00 84.23 0.68 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1159371325
94.87 0.28 98.54 0.00 94.41 0.03 99.32 1.60 91.67 0.00 97.97 0.00 97.69 0.10 84.49 0.26 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1082001749
95.14 0.27 98.54 0.00 94.46 0.05 99.32 0.00 91.67 0.00 97.97 0.00 97.69 0.00 86.33 1.84 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3505872427
95.32 0.18 98.60 0.06 94.51 0.05 99.32 0.00 92.31 0.64 98.00 0.04 97.78 0.10 86.70 0.37 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2727065411
95.48 0.16 98.68 0.07 94.57 0.05 99.32 0.00 92.95 0.64 98.11 0.11 97.88 0.10 86.86 0.16 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2215820441
95.63 0.16 98.71 0.04 95.30 0.73 99.32 0.00 92.95 0.00 98.11 0.00 97.88 0.00 87.17 0.32 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2920093884
95.78 0.15 98.79 0.07 95.32 0.03 99.32 0.00 93.59 0.64 98.23 0.11 97.98 0.10 87.28 0.11 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3312319667
95.93 0.14 98.79 0.00 95.32 0.00 99.32 0.00 93.59 0.00 98.23 0.00 97.98 0.00 88.28 1.00 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2449474077
96.07 0.14 98.81 0.02 95.35 0.03 99.32 0.00 93.59 0.00 98.23 0.00 98.07 0.10 89.12 0.84 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3267466502
96.20 0.14 98.86 0.06 95.37 0.03 99.32 0.00 94.23 0.64 98.30 0.07 98.17 0.10 89.17 0.05 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1547859070
96.33 0.13 98.90 0.04 95.40 0.03 99.77 0.46 94.23 0.00 98.30 0.00 98.36 0.19 89.38 0.21 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1160320750
96.47 0.13 98.92 0.02 95.50 0.10 99.77 0.00 94.23 0.00 98.37 0.07 99.04 0.67 89.43 0.05 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3777959875
96.59 0.13 98.97 0.06 95.53 0.03 99.77 0.00 94.87 0.64 98.45 0.07 99.13 0.10 89.43 0.00 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.757761035
96.72 0.13 99.03 0.06 95.55 0.03 99.77 0.00 95.51 0.64 98.52 0.07 99.23 0.10 89.43 0.00 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.468645747
96.84 0.12 99.07 0.04 95.58 0.03 99.77 0.00 96.15 0.64 98.56 0.04 99.33 0.10 89.43 0.00 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1905592369
96.96 0.12 99.10 0.04 95.60 0.03 99.77 0.00 96.79 0.64 98.60 0.04 99.42 0.10 89.43 0.00 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2875967798
97.08 0.12 99.14 0.04 95.63 0.03 99.77 0.00 97.44 0.64 98.63 0.04 99.52 0.10 89.43 0.00 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.380770833
97.20 0.12 99.18 0.04 95.65 0.03 99.77 0.00 98.08 0.64 98.67 0.04 99.61 0.10 89.43 0.00 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3028045983
97.32 0.12 99.22 0.04 95.68 0.03 99.77 0.00 98.72 0.64 98.71 0.04 99.71 0.10 89.43 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1729494308
97.42 0.10 99.22 0.00 95.68 0.00 99.77 0.00 98.72 0.00 98.71 0.00 99.71 0.00 90.12 0.68 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3656139617
97.49 0.08 99.25 0.04 95.75 0.08 99.77 0.00 98.72 0.00 98.71 0.00 99.71 0.00 90.54 0.42 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1446400126
97.57 0.07 99.25 0.00 96.21 0.46 99.77 0.00 98.72 0.00 98.71 0.00 99.71 0.00 90.59 0.05 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3391525765
97.63 0.07 99.25 0.00 96.21 0.00 99.77 0.00 98.72 0.00 98.71 0.00 99.71 0.00 91.06 0.47 /workspace/coverage/default/3.sysrst_ctrl_stress_all.3879351176
97.69 0.06 99.25 0.00 96.21 0.00 99.77 0.00 98.72 0.00 98.71 0.00 99.71 0.00 91.48 0.42 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.994976676
97.75 0.05 99.33 0.07 96.28 0.08 100.00 0.23 98.72 0.00 98.71 0.00 99.71 0.00 91.48 0.00 /workspace/coverage/default/26.sysrst_ctrl_alert_test.2632710495
97.80 0.05 99.37 0.04 96.54 0.25 100.00 0.00 98.72 0.00 98.78 0.07 99.71 0.00 91.48 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3670933173
97.84 0.04 99.37 0.00 96.54 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 91.75 0.26 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.4014422827
97.87 0.04 99.37 0.00 96.54 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.01 0.26 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1588562637
97.90 0.03 99.37 0.00 96.59 0.05 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.17 0.16 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2315045699
97.93 0.03 99.38 0.02 96.61 0.03 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.32 0.16 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4275399660
97.96 0.02 99.38 0.00 96.61 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.48 0.16 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2206727993
97.98 0.02 99.38 0.00 96.61 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.64 0.16 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.1420636928
98.00 0.02 99.38 0.00 96.61 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.80 0.16 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1936233240
98.02 0.02 99.38 0.00 96.76 0.15 100.00 0.00 98.72 0.00 98.78 0.00 99.71 0.00 92.80 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1591866884
98.04 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.10 92.85 0.05 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.727772591
98.06 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 92.95 0.11 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1374747007
98.07 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 93.06 0.11 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.4233698452
98.09 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 93.17 0.11 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3251524869
98.10 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 93.27 0.11 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2389447582
98.12 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 93.38 0.11 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1952742856
98.13 0.02 99.38 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.78 0.00 99.81 0.00 93.48 0.11 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3978287612
98.14 0.01 99.40 0.02 96.76 0.00 100.00 0.00 98.72 0.00 98.82 0.04 99.81 0.00 93.48 0.00 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3167709183
98.15 0.01 99.42 0.02 96.76 0.00 100.00 0.00 98.72 0.00 98.85 0.04 99.81 0.00 93.48 0.00 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.566460809
98.16 0.01 99.44 0.02 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.04 99.81 0.00 93.48 0.00 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2213453779
98.16 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.53 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1272402814
98.17 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.59 0.05 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3315705485
98.18 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.64 0.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.1584667943
98.19 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.69 0.05 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1192359929
98.19 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.74 0.05 /workspace/coverage/default/18.sysrst_ctrl_stress_all.500884498
98.20 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.80 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2311287118
98.21 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.85 0.05 /workspace/coverage/default/24.sysrst_ctrl_stress_all.1659101056
98.22 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.90 0.05 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3558024222
98.22 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 93.95 0.05 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3832818399
98.23 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.01 0.05 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.522324520
98.24 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.06 0.05 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.32470331
98.25 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.11 0.05 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.300579055
98.25 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.16 0.05 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3034915751
98.26 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.22 0.05 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3786995353
98.27 0.01 99.44 0.00 96.76 0.00 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.27 0.05 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1570034337
98.27 0.01 99.44 0.00 96.79 0.03 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.27 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3603547638
98.28 0.01 99.44 0.00 96.81 0.03 100.00 0.00 98.72 0.00 98.89 0.00 99.81 0.00 94.27 0.00 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3552643169

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3544483828
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.893319811
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3349876815
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1040214881
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2672470873
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4175815446
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1054977298
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3654159132
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.417137902
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.145240500
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3506546928
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2756327244
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3860628506
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.899194898
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.731130268
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2204371509
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1274097932
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3606141249
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2320368284
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.206455883
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2042701363
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3750350035
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.728477101
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3251912031
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2088562459
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3126839218
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.260136362
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2342207978
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1207331913
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3928771192
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2703643329
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.42303257
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1161168681
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.4013540903
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1370699536
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2912105736
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1274979695
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3716725852
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2018541922
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3116897813
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1165503239
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.927901832
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.519487741
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3650199615
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.93274975
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1190318239
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2727209262
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3121147855
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1240239618
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2587336528
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.357604090
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.176263587
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2262536428
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2501838502
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1364075142
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.743390546
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1809376589
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1695703850
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3158074087
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2879331351
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2916693819
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2644040876
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2331810433
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1958747971
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3402963822
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.130065923
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2110050413
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3959633062
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.775301525
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.19319188
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3575860620
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4207300505
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/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.4222830347
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2288788268
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3925076971
/workspace/coverage/default/41.sysrst_ctrl_smoke.2823463466
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2304228832
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1494433270
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3328084235
/workspace/coverage/default/42.sysrst_ctrl_alert_test.682325783
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2141733012
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2231472576
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.876765253
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2092325461
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3547020346
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4130226837
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3313451858
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.489168081
/workspace/coverage/default/42.sysrst_ctrl_smoke.2388146922
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1866695870
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.156272756
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.865887726
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3719293341
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3879347430
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3715133473
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3753876549
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.588774982
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3985089748
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4026432947
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2635029668
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3340055313
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1453170366
/workspace/coverage/default/43.sysrst_ctrl_smoke.3500190844
/workspace/coverage/default/43.sysrst_ctrl_stress_all.925104254
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3311765106
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.208747680
/workspace/coverage/default/44.sysrst_ctrl_alert_test.4013123916
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2976697169
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2795774203
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2186511432
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3173871952
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1248238838
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1541074477
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.413335926
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1310527417
/workspace/coverage/default/44.sysrst_ctrl_smoke.22410377
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1671455449
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3944726197
/workspace/coverage/default/45.sysrst_ctrl_alert_test.4174911667
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1830106692
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.4270608738
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3472569712
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3393299842
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3521573583
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.837981425
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2830122203
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2379092645
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2591015725
/workspace/coverage/default/45.sysrst_ctrl_smoke.357689807
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4011187402
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1227263665
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.4027608973
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.879576695
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.215647555
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2491628149
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.776858941
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1833438634
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1450366497
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3057195824
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.917656516
/workspace/coverage/default/46.sysrst_ctrl_smoke.2568091114
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2319492255
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.680925144
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1731633702
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1257991099
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1727487365
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.141346997
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3420927785
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.723735188
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1579347535
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3424735484
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3149476014
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.373821671
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4217756615
/workspace/coverage/default/47.sysrst_ctrl_smoke.3286963592
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1528797550
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.592386054
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.579876458
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3487100029
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3105304763
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.577425987
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.184551208
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1676566534
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.844232600
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3542055846
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.512595362
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.723551922
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3978307348
/workspace/coverage/default/48.sysrst_ctrl_smoke.1191494676
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3142238199
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2743579232
/workspace/coverage/default/49.sysrst_ctrl_alert_test.4286404878
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1260649917
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3528112904
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2559638396
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2960641268
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2025697648
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2664146206
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3055977867
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2818916797
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3337093189
/workspace/coverage/default/49.sysrst_ctrl_smoke.4154616816
/workspace/coverage/default/49.sysrst_ctrl_stress_all.191407159
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3550356128
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1499727776
/workspace/coverage/default/5.sysrst_ctrl_alert_test.346251342
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.444077059
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.1009220965
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2638855432
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2572346994
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3572826059
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2339258626
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1888947041
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1954117067
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3392338922
/workspace/coverage/default/5.sysrst_ctrl_smoke.2864951657
/workspace/coverage/default/5.sysrst_ctrl_stress_all.925117653
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.284662578
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1077129204
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1734436047
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1054041615
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2052153193
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.188852663
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3366985564
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1771480916
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4153577747
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4290409520
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3190978264
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.4092590732
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1697889022
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1333643149
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.227780152
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.4092198580
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4212164694
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2044759220
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2568781622
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1810885263
/workspace/coverage/default/6.sysrst_ctrl_smoke.4196496237
/workspace/coverage/default/6.sysrst_ctrl_stress_all.900493475
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3386743690
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.291323994
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1683327485
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1930467092
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1892743515
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1912520401
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.659160620
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3457653547
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.822336555
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3618478912
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1533790121
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.951358636
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.966869141
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1737354132
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3740118793
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3779756217
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1358498504
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4060875151
/workspace/coverage/default/7.sysrst_ctrl_smoke.2325188656
/workspace/coverage/default/7.sysrst_ctrl_stress_all.749661633
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.839582872
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2837251729
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3619318815
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.184880498
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1946650569
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.4284225768
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3999563772
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3689865497
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.952025803
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3925162237
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1776475353
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2424655526
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3942995155
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2389674054
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3236337217
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4083769568
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2007461526
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.151805228
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3953237725
/workspace/coverage/default/8.sysrst_ctrl_smoke.1813495298
/workspace/coverage/default/8.sysrst_ctrl_stress_all.645767647
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2737820785
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3063519509
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2070357352
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.121744536
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1649378170
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1028882689
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2378667483
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1668279623
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2766802885
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1764503632
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.466226721
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1148545798
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2580525025
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.700723428
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3114914886
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2550430998
/workspace/coverage/default/9.sysrst_ctrl_smoke.1528843607
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2461535094
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.864137110
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1687274622
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3262123147
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2821473671
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.169567976
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.356003603
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2901200009
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1626957008



Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1016964035 Jun 21 05:07:23 PM PDT 24 Jun 21 05:10:42 PM PDT 24 97353953397 ps
T4 /workspace/coverage/default/26.sysrst_ctrl_alert_test.2632710495 Jun 21 05:07:40 PM PDT 24 Jun 21 05:07:44 PM PDT 24 2068438797 ps
T5 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.271961734 Jun 21 05:08:36 PM PDT 24 Jun 21 05:08:54 PM PDT 24 35887500078 ps
T13 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2498165747 Jun 21 05:07:24 PM PDT 24 Jun 21 05:07:33 PM PDT 24 2529452105 ps
T2 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3502752273 Jun 21 05:07:20 PM PDT 24 Jun 21 05:12:33 PM PDT 24 118220178309 ps
T3 /workspace/coverage/default/19.sysrst_ctrl_stress_all.4217705180 Jun 21 05:07:26 PM PDT 24 Jun 21 05:07:42 PM PDT 24 7395858311 ps
T6 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.875672190 Jun 21 05:07:43 PM PDT 24 Jun 21 05:07:46 PM PDT 24 5526253771 ps
T14 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2333647060 Jun 21 05:07:18 PM PDT 24 Jun 21 05:07:32 PM PDT 24 2469490131 ps
T15 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2505080508 Jun 21 05:08:03 PM PDT 24 Jun 21 05:08:13 PM PDT 24 3222991741 ps
T7 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4275399660 Jun 21 05:08:36 PM PDT 24 Jun 21 05:10:07 PM PDT 24 68587987123 ps
T51 /workspace/coverage/default/19.sysrst_ctrl_smoke.1255941792 Jun 21 05:07:22 PM PDT 24 Jun 21 05:07:35 PM PDT 24 2111849729 ps
T61 /workspace/coverage/default/17.sysrst_ctrl_alert_test.3415537219 Jun 21 05:07:24 PM PDT 24 Jun 21 05:07:33 PM PDT 24 2026988322 ps
T8 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2755434141 Jun 21 05:08:01 PM PDT 24 Jun 21 05:08:10 PM PDT 24 7638836762 ps
T9 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4011187402 Jun 21 05:08:23 PM PDT 24 Jun 21 05:08:34 PM PDT 24 6520399982 ps
T62 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.413335926 Jun 21 05:08:21 PM PDT 24 Jun 21 05:08:29 PM PDT 24 2226599445 ps
T63 /workspace/coverage/default/13.sysrst_ctrl_smoke.2890440506 Jun 21 05:07:14 PM PDT 24 Jun 21 05:07:22 PM PDT 24 2131864049 ps
T55 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2960641268 Jun 21 05:08:39 PM PDT 24 Jun 21 05:08:49 PM PDT 24 2789526004 ps
T10 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.3479682781 Jun 21 05:07:11 PM PDT 24 Jun 21 05:07:17 PM PDT 24 3138881563 ps
T57 /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2565993984 Jun 21 05:07:17 PM PDT 24 Jun 21 05:07:26 PM PDT 24 3162493159 ps
T26 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1159371325 Jun 21 05:08:42 PM PDT 24 Jun 21 05:09:24 PM PDT 24 61473510530 ps
T43 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3999563772 Jun 21 05:08:44 PM PDT 24 Jun 21 05:09:01 PM PDT 24 23596505900 ps
T22 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1160320750 Jun 21 05:07:29 PM PDT 24 Jun 21 05:07:36 PM PDT 24 2569990194 ps
T56 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3082335294 Jun 21 05:08:08 PM PDT 24 Jun 21 05:08:18 PM PDT 24 2763535886 ps
T24 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2245328867 Jun 21 05:08:15 PM PDT 24 Jun 21 05:08:28 PM PDT 24 3848318073 ps
T25 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.268431604 Jun 21 05:07:18 PM PDT 24 Jun 21 05:07:34 PM PDT 24 3768910056 ps
T52 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2334518911 Jun 21 05:08:13 PM PDT 24 Jun 21 05:08:19 PM PDT 24 2079361463 ps
T53 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.37278885 Jun 21 05:08:00 PM PDT 24 Jun 21 05:08:03 PM PDT 24 2050440988 ps
T42 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3925162237 Jun 21 05:08:47 PM PDT 24 Jun 21 05:10:18 PM PDT 24 36221398889 ps
T20 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1851135301 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:20 PM PDT 24 2482388153 ps
T11 /workspace/coverage/default/5.sysrst_ctrl_stress_all.925117653 Jun 21 05:06:57 PM PDT 24 Jun 21 05:07:06 PM PDT 24 10733599893 ps
T12 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2830839166 Jun 21 05:08:42 PM PDT 24 Jun 21 05:14:21 PM PDT 24 141154859485 ps
T44 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3753876549 Jun 21 05:08:23 PM PDT 24 Jun 21 05:08:45 PM PDT 24 26356474051 ps
T30 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3426459259 Jun 21 05:08:06 PM PDT 24 Jun 21 05:09:22 PM PDT 24 107788257373 ps
T274 /workspace/coverage/default/38.sysrst_ctrl_alert_test.1026405720 Jun 21 05:08:13 PM PDT 24 Jun 21 05:08:18 PM PDT 24 2021862258 ps
T298 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.587877615 Jun 21 05:07:58 PM PDT 24 Jun 21 05:08:01 PM PDT 24 2730707966 ps
T23 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.4140498709 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:14 PM PDT 24 3161786320 ps
T45 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2638855432 Jun 21 05:06:56 PM PDT 24 Jun 21 05:07:50 PM PDT 24 20080070679 ps
T200 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2375047796 Jun 21 05:08:08 PM PDT 24 Jun 21 05:08:13 PM PDT 24 3849030873 ps
T68 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2184213387 Jun 21 05:07:15 PM PDT 24 Jun 21 05:07:23 PM PDT 24 2535104131 ps
T69 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1318856777 Jun 21 05:07:40 PM PDT 24 Jun 21 05:07:45 PM PDT 24 2638993692 ps
T34 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2772671072 Jun 21 05:07:41 PM PDT 24 Jun 21 05:09:41 PM PDT 24 487959965684 ps
T31 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.2570344771 Jun 21 05:07:48 PM PDT 24 Jun 21 05:08:28 PM PDT 24 147183072410 ps
T151 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.289378108 Jun 21 05:07:51 PM PDT 24 Jun 21 05:07:56 PM PDT 24 2262826753 ps
T89 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3267466502 Jun 21 05:08:17 PM PDT 24 Jun 21 05:15:39 PM PDT 24 180509596734 ps
T152 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3393299842 Jun 21 05:08:20 PM PDT 24 Jun 21 05:08:37 PM PDT 24 4058666363 ps
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T21 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2469949764 Jun 21 05:07:06 PM PDT 24 Jun 21 05:07:10 PM PDT 24 2471322816 ps
T70 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1179155668 Jun 21 05:07:56 PM PDT 24 Jun 21 05:08:00 PM PDT 24 2633842984 ps
T64 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1541074477 Jun 21 05:08:21 PM PDT 24 Jun 21 05:08:28 PM PDT 24 2502121098 ps
T29 /workspace/coverage/default/3.sysrst_ctrl_stress_all.3879351176 Jun 21 05:06:42 PM PDT 24 Jun 21 05:07:02 PM PDT 24 105929369587 ps
T241 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2070357352 Jun 21 05:08:41 PM PDT 24 Jun 21 05:15:48 PM PDT 24 235160939141 ps
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T65 /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3755561288 Jun 21 05:07:49 PM PDT 24 Jun 21 05:07:54 PM PDT 24 2461172665 ps
T395 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3732440988 Jun 21 05:07:32 PM PDT 24 Jun 21 05:07:39 PM PDT 24 2786818689 ps
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T58 /workspace/coverage/default/32.sysrst_ctrl_stress_all.1920494239 Jun 21 05:08:00 PM PDT 24 Jun 21 05:08:55 PM PDT 24 1117668655939 ps
T397 /workspace/coverage/default/36.sysrst_ctrl_smoke.2586540740 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:11 PM PDT 24 2133137953 ps
T32 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2901200009 Jun 21 05:08:52 PM PDT 24 Jun 21 05:13:43 PM PDT 24 124711428175 ps
T71 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3925076971 Jun 21 05:08:18 PM PDT 24 Jun 21 05:08:25 PM PDT 24 2524291556 ps
T398 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1228013248 Jun 21 05:08:05 PM PDT 24 Jun 21 05:08:15 PM PDT 24 2608470866 ps
T35 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3605736738 Jun 21 05:08:17 PM PDT 24 Jun 21 05:11:41 PM PDT 24 84630136548 ps
T185 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1647722711 Jun 21 05:08:18 PM PDT 24 Jun 21 05:08:25 PM PDT 24 2622482907 ps
T46 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3732777077 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:16 PM PDT 24 3237942997 ps
T59 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1955499121 Jun 21 05:07:17 PM PDT 24 Jun 21 05:07:31 PM PDT 24 4556821394 ps
T186 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4151709585 Jun 21 05:06:38 PM PDT 24 Jun 21 05:06:45 PM PDT 24 2227738673 ps
T66 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3580179697 Jun 21 05:06:39 PM PDT 24 Jun 21 05:06:43 PM PDT 24 2485388757 ps
T187 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.161007382 Jun 21 05:07:15 PM PDT 24 Jun 21 05:07:22 PM PDT 24 2137720913 ps
T188 /workspace/coverage/default/29.sysrst_ctrl_alert_test.3229255542 Jun 21 05:07:48 PM PDT 24 Jun 21 05:07:55 PM PDT 24 2010562958 ps
T189 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.2390924534 Jun 21 05:07:17 PM PDT 24 Jun 21 05:07:26 PM PDT 24 2538466881 ps
T190 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.887486197 Jun 21 05:08:05 PM PDT 24 Jun 21 05:08:10 PM PDT 24 2103471519 ps
T399 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.756677662 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:13 PM PDT 24 2348423640 ps
T400 /workspace/coverage/default/9.sysrst_ctrl_smoke.1528843607 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:14 PM PDT 24 2138665496 ps
T80 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3552643169 Jun 21 05:07:40 PM PDT 24 Jun 21 05:08:52 PM PDT 24 33892411100 ps
T117 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.138148257 Jun 21 05:08:53 PM PDT 24 Jun 21 05:14:02 PM PDT 24 115369746343 ps
T401 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3493466617 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:14 PM PDT 24 2617592664 ps
T60 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.626359709 Jun 21 05:07:23 PM PDT 24 Jun 21 05:07:34 PM PDT 24 6448528548 ps
T118 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.994976676 Jun 21 05:08:37 PM PDT 24 Jun 21 05:09:14 PM PDT 24 143483782451 ps
T402 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4026432947 Jun 21 05:08:20 PM PDT 24 Jun 21 05:08:27 PM PDT 24 2704886481 ps
T36 /workspace/coverage/default/4.sysrst_ctrl_stress_all.1755309937 Jun 21 05:06:57 PM PDT 24 Jun 21 05:07:27 PM PDT 24 11546791612 ps
T178 /workspace/coverage/default/16.sysrst_ctrl_smoke.1044460278 Jun 21 05:07:19 PM PDT 24 Jun 21 05:07:32 PM PDT 24 2108221599 ps
T179 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1446400126 Jun 21 05:07:58 PM PDT 24 Jun 21 05:13:32 PM PDT 24 139092924764 ps
T180 /workspace/coverage/default/49.sysrst_ctrl_smoke.4154616816 Jun 21 05:08:32 PM PDT 24 Jun 21 05:08:37 PM PDT 24 2114052535 ps
T181 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.837981425 Jun 21 05:08:24 PM PDT 24 Jun 21 05:08:31 PM PDT 24 2628124384 ps
T182 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.315486550 Jun 21 05:07:22 PM PDT 24 Jun 21 05:07:37 PM PDT 24 2613079360 ps
T77 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1218514601 Jun 21 05:07:17 PM PDT 24 Jun 21 05:09:09 PM PDT 24 57478915375 ps
T38 /workspace/coverage/default/2.sysrst_ctrl_stress_all.2407685994 Jun 21 05:06:42 PM PDT 24 Jun 21 05:06:57 PM PDT 24 16021970634 ps
T39 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.782470210 Jun 21 05:06:36 PM PDT 24 Jun 21 05:07:22 PM PDT 24 35545538407 ps
T33 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3505872427 Jun 21 05:08:20 PM PDT 24 Jun 21 05:11:46 PM PDT 24 83510265953 ps
T41 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.468645747 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:16 PM PDT 24 3299953464 ps
T106 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3268261754 Jun 21 05:07:19 PM PDT 24 Jun 21 05:07:31 PM PDT 24 2515627550 ps
T67 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3457753863 Jun 21 05:07:20 PM PDT 24 Jun 21 05:07:29 PM PDT 24 2548344656 ps
T78 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3433506140 Jun 21 05:07:31 PM PDT 24 Jun 21 05:07:47 PM PDT 24 65290696850 ps
T91 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.121744536 Jun 21 05:08:47 PM PDT 24 Jun 21 05:09:12 PM PDT 24 32235113067 ps
T107 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.169567976 Jun 21 05:08:44 PM PDT 24 Jun 21 05:08:59 PM PDT 24 55083440353 ps
T158 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2389447582 Jun 21 05:06:43 PM PDT 24 Jun 21 05:06:55 PM PDT 24 39547599699 ps
T227 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3876800734 Jun 21 05:08:14 PM PDT 24 Jun 21 05:09:29 PM PDT 24 51179522731 ps
T228 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3190748017 Jun 21 05:07:19 PM PDT 24 Jun 21 05:07:29 PM PDT 24 2454631451 ps
T229 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2844173686 Jun 21 05:07:22 PM PDT 24 Jun 21 05:07:35 PM PDT 24 4315178319 ps
T253 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.577425987 Jun 21 05:08:27 PM PDT 24 Jun 21 05:09:27 PM PDT 24 41681956266 ps
T257 /workspace/coverage/default/42.sysrst_ctrl_smoke.2388146922 Jun 21 05:08:13 PM PDT 24 Jun 21 05:08:29 PM PDT 24 2110942661 ps
T47 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1374747007 Jun 21 05:06:28 PM PDT 24 Jun 21 05:06:35 PM PDT 24 3688747988 ps
T300 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.4172905101 Jun 21 05:08:04 PM PDT 24 Jun 21 05:08:07 PM PDT 24 2481305217 ps
T48 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2014933919 Jun 21 05:06:34 PM PDT 24 Jun 21 05:06:38 PM PDT 24 3585210339 ps
T403 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3300861556 Jun 21 05:08:07 PM PDT 24 Jun 21 05:08:16 PM PDT 24 2612502584 ps
T301 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3652863831 Jun 21 05:06:43 PM PDT 24 Jun 21 05:06:47 PM PDT 24 2497910721 ps
T302 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1600787971 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:25 PM PDT 24 2510878120 ps
T49 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2766802885 Jun 21 05:07:08 PM PDT 24 Jun 21 05:07:14 PM PDT 24 3318028270 ps
T250 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1054041615 Jun 21 05:08:49 PM PDT 24 Jun 21 05:12:05 PM PDT 24 83484221819 ps
T50 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4130165810 Jun 21 05:07:26 PM PDT 24 Jun 21 05:08:19 PM PDT 24 76152762583 ps
T404 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3049697856 Jun 21 05:06:36 PM PDT 24 Jun 21 05:06:41 PM PDT 24 2329839759 ps
T304 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1687274622 Jun 21 05:07:09 PM PDT 24 Jun 21 05:07:14 PM PDT 24 4950837797 ps
T336 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.877503898 Jun 21 05:07:32 PM PDT 24 Jun 21 05:10:09 PM PDT 24 131492118353 ps
T305 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3951771255 Jun 21 05:07:41 PM PDT 24 Jun 21 05:07:45 PM PDT 24 3634176098 ps
T72 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3342439643 Jun 21 05:07:18 PM PDT 24 Jun 21 05:07:33 PM PDT 24 2592192069 ps
T259 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2033403359 Jun 21 05:08:17 PM PDT 24 Jun 21 05:10:11 PM PDT 24 43327809203 ps
T405 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2007461526 Jun 21 05:07:10 PM PDT 24 Jun 21 05:07:15 PM PDT 24 2495773842 ps
T406 /workspace/coverage/default/0.sysrst_ctrl_smoke.1819683919 Jun 21 05:06:32 PM PDT 24 Jun 21 05:06:38 PM PDT 24 2118031342 ps
T407 /workspace/coverage/default/19.sysrst_ctrl_alert_test.3063060310 Jun 21 05:07:25 PM PDT 24 Jun 21 05:07:37 PM PDT 24 2012960911 ps
T408 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3955851965 Jun 21 05:07:33 PM PDT 24 Jun 21 05:07:41 PM PDT 24 2520693283 ps
T409 /workspace/coverage/default/30.sysrst_ctrl_alert_test.2318701709 Jun 21 05:07:57 PM PDT 24 Jun 21 05:08:04 PM PDT 24 2014613674 ps
T410 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1676566534 Jun 21 05:08:31 PM PDT 24 Jun 21 05:08:37 PM PDT 24 5424808627 ps
T37 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1737354132 Jun 21 05:06:57 PM PDT 24 Jun 21 05:07:01 PM PDT 24 3601767956 ps
T174 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2102255048 Jun 21 05:07:58 PM PDT 24 Jun 21 05:08:05 PM PDT 24 2941825665 ps
T391 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4276337871 Jun 21 05:06:44 PM PDT 24 Jun 21 05:06:49 PM PDT 24 3935119328 ps
T292 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3689865497 Jun 21 05:08:38 PM PDT 24 Jun 21 05:13:13 PM PDT 24 100426366352 ps
T411 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.307780185 Jun 21 05:07:41 PM PDT 24 Jun 21 05:07:51 PM PDT 24 2450108131 ps
T242 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1588562637 Jun 21 05:08:41 PM PDT 24 Jun 21 05:09:50 PM PDT 24 51016672400 ps
T412 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2820799708 Jun 21 05:07:38 PM PDT 24 Jun 21 05:07:42 PM PDT 24 2151945023 ps
T413 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.470901880 Jun 21 05:08:13 PM PDT 24 Jun 21 05:08:31 PM PDT 24 2126568393 ps
T414 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2633337332 Jun 21 05:07:50 PM PDT 24 Jun 21 05:07:58 PM PDT 24 4731930308 ps
T266 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1082001749 Jun 21 05:06:55 PM PDT 24 Jun 21 05:07:11 PM PDT 24 22069951700 ps
T282 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2802859155 Jun 21 05:07:26 PM PDT 24 Jun 21 05:07:33 PM PDT 24 2580676764 ps
T283 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3243378747 Jun 21 05:07:10 PM PDT 24 Jun 21 05:07:15 PM PDT 24 2553692617 ps
T284 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1946112699 Jun 21 05:06:29 PM PDT 24 Jun 21 05:06:38 PM PDT 24 2062208126 ps
T73 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1058912873 Jun 21 05:07:32 PM PDT 24 Jun 21 05:08:13 PM PDT 24 259309004931 ps
T92 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3589959562 Jun 21 05:08:01 PM PDT 24 Jun 21 05:08:19 PM PDT 24 26602395029 ps
T90 /workspace/coverage/default/12.sysrst_ctrl_stress_all.637402504 Jun 21 05:07:17 PM PDT 24 Jun 21 05:07:53 PM PDT 24 12011450495 ps
T285 /workspace/coverage/default/46.sysrst_ctrl_alert_test.1227263665 Jun 21 05:08:35 PM PDT 24 Jun 21 05:08:38 PM PDT 24 2038034678 ps
T286 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3905063319 Jun 21 05:07:49 PM PDT 24 Jun 21 05:07:53 PM PDT 24 3287910090 ps
T157 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1465474268 Jun 21 05:06:43 PM PDT 24 Jun 21 05:07:52 PM PDT 24 28298640647 ps
T415 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.864151097 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:25 PM PDT 24 2466043230 ps
T416 /workspace/coverage/default/37.sysrst_ctrl_stress_all.1359951033 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:24 PM PDT 24 12921445484 ps
T93 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2727065411 Jun 21 05:07:16 PM PDT 24 Jun 21 05:08:15 PM PDT 24 79344973490 ps
T94 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.32470331 Jun 21 05:08:37 PM PDT 24 Jun 21 05:13:08 PM PDT 24 110633321816 ps
T417 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.723735188 Jun 21 05:08:31 PM PDT 24 Jun 21 05:08:43 PM PDT 24 3343606683 ps
T136 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.4107042760 Jun 21 05:07:19 PM PDT 24 Jun 21 05:07:30 PM PDT 24 2908659686 ps
T306 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.319597107 Jun 21 05:07:50 PM PDT 24 Jun 21 05:07:57 PM PDT 24 2542568112 ps
T40 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1905592369 Jun 21 05:07:11 PM PDT 24 Jun 21 05:07:24 PM PDT 24 4010036993 ps
T133 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.525317219 Jun 21 05:07:15 PM PDT 24 Jun 21 05:09:28 PM PDT 24 52088187094 ps
T201 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2278485174 Jun 21 05:07:14 PM PDT 24 Jun 21 05:07:21 PM PDT 24 4385286196 ps
T202 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.723551922 Jun 21 05:08:34 PM PDT 24 Jun 21 05:08:38 PM PDT 24 2164933347 ps
T203 /workspace/coverage/default/30.sysrst_ctrl_smoke.4018191266 Jun 21 05:07:50 PM PDT 24 Jun 21 05:07:55 PM PDT 24 2117173797 ps
T204 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3386168915 Jun 21 05:07:58 PM PDT 24 Jun 21 05:08:02 PM PDT 24 2531679830 ps
T205 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1450272127 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:16 PM PDT 24 2472439217 ps
T206 /workspace/coverage/default/47.sysrst_ctrl_stress_all.1528797550 Jun 21 05:08:37 PM PDT 24 Jun 21 05:08:48 PM PDT 24 6737988779 ps
T84 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3034915751 Jun 21 05:08:38 PM PDT 24 Jun 21 05:09:33 PM PDT 24 72687265422 ps
T207 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3151442768 Jun 21 05:07:38 PM PDT 24 Jun 21 05:07:42 PM PDT 24 2523180925 ps
T418 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2228046443 Jun 21 05:07:41 PM PDT 24 Jun 21 05:07:46 PM PDT 24 2624234643 ps
T288 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1102334874 Jun 21 05:07:22 PM PDT 24 Jun 21 05:07:33 PM PDT 24 3697277098 ps
T419 /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3302388057 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:11 PM PDT 24 2628361108 ps
T420 /workspace/coverage/default/14.sysrst_ctrl_smoke.1308693891 Jun 21 05:07:16 PM PDT 24 Jun 21 05:07:24 PM PDT 24 2128568458 ps
T289 /workspace/coverage/default/40.sysrst_ctrl_stress_all.1501232789 Jun 21 05:08:18 PM PDT 24 Jun 21 05:08:43 PM PDT 24 15319591386 ps
T95 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3472569712 Jun 21 05:08:34 PM PDT 24 Jun 21 05:08:55 PM PDT 24 27860935734 ps
T421 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3630136162 Jun 21 05:07:32 PM PDT 24 Jun 21 05:07:38 PM PDT 24 2231608146 ps
T422 /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.840027912 Jun 21 05:07:20 PM PDT 24 Jun 21 05:07:29 PM PDT 24 2638746118 ps
T423 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3879347430 Jun 21 05:08:22 PM PDT 24 Jun 21 05:08:37 PM PDT 24 3564490183 ps
T424 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1468701485 Jun 21 05:07:41 PM PDT 24 Jun 21 05:07:44 PM PDT 24 2288785471 ps
T425 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2166788162 Jun 21 05:07:29 PM PDT 24 Jun 21 05:07:37 PM PDT 24 3574042919 ps
T426 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.816518652 Jun 21 05:07:26 PM PDT 24 Jun 21 05:07:40 PM PDT 24 2609647600 ps
T74 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3614994908 Jun 21 05:08:12 PM PDT 24 Jun 21 05:08:50 PM PDT 24 142228398739 ps
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T427 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2751734248 Jun 21 05:08:05 PM PDT 24 Jun 21 05:08:11 PM PDT 24 2480377254 ps
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T429 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4217756615 Jun 21 05:08:29 PM PDT 24 Jun 21 05:08:34 PM PDT 24 2543807125 ps
T341 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3554844893 Jun 21 05:06:31 PM PDT 24 Jun 21 05:08:12 PM PDT 24 78801239216 ps
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T199 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.284662578 Jun 21 05:06:55 PM PDT 24 Jun 21 05:08:03 PM PDT 24 56895621530 ps
T433 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1002184059 Jun 21 05:07:28 PM PDT 24 Jun 21 05:07:38 PM PDT 24 3093896976 ps
T287 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2655384974 Jun 21 05:07:47 PM PDT 24 Jun 21 05:08:32 PM PDT 24 18839941906 ps
T434 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1358498504 Jun 21 05:06:56 PM PDT 24 Jun 21 05:07:04 PM PDT 24 2258188443 ps
T290 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1515122870 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:17 PM PDT 24 3336117301 ps
T435 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.12913054 Jun 21 05:07:24 PM PDT 24 Jun 21 05:07:41 PM PDT 24 3671221437 ps
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T437 /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2818916797 Jun 21 05:08:32 PM PDT 24 Jun 21 05:08:36 PM PDT 24 2141068924 ps
T438 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2621182956 Jun 21 05:07:39 PM PDT 24 Jun 21 05:07:42 PM PDT 24 2552358095 ps
T439 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3114914886 Jun 21 05:07:11 PM PDT 24 Jun 21 05:07:17 PM PDT 24 2141405301 ps
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T344 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3262123147 Jun 21 05:08:49 PM PDT 24 Jun 21 05:10:15 PM PDT 24 91241794577 ps
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T291 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.444077059 Jun 21 05:07:00 PM PDT 24 Jun 21 05:07:10 PM PDT 24 3498372434 ps
T303 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2989713161 Jun 21 05:06:44 PM PDT 24 Jun 21 05:06:54 PM PDT 24 2513551073 ps
T444 /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4092389328 Jun 21 05:06:30 PM PDT 24 Jun 21 05:06:45 PM PDT 24 4168359299 ps
T445 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3547020346 Jun 21 05:08:37 PM PDT 24 Jun 21 05:08:42 PM PDT 24 2628886775 ps
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T307 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1827644345 Jun 21 05:06:36 PM PDT 24 Jun 21 05:06:40 PM PDT 24 7625723556 ps
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T338 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3619318815 Jun 21 05:08:52 PM PDT 24 Jun 21 05:09:52 PM PDT 24 158730927314 ps
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T137 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.1284230523 Jun 21 05:08:17 PM PDT 24 Jun 21 05:08:25 PM PDT 24 4264008182 ps
T447 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.899690422 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:10 PM PDT 24 2637045962 ps
T448 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.3969223840 Jun 21 05:08:15 PM PDT 24 Jun 21 05:08:23 PM PDT 24 2517798778 ps
T134 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.29971400 Jun 21 05:08:15 PM PDT 24 Jun 21 05:08:56 PM PDT 24 60880173846 ps
T161 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2572346994 Jun 21 05:06:57 PM PDT 24 Jun 21 05:07:07 PM PDT 24 2842259970 ps
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T164 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2313875080 Jun 21 05:06:32 PM PDT 24 Jun 21 05:06:37 PM PDT 24 2636646190 ps
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T160 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1278094528 Jun 21 05:06:39 PM PDT 24 Jun 21 05:06:47 PM PDT 24 3773654581 ps
T166 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3978307348 Jun 21 05:08:28 PM PDT 24 Jun 21 05:08:36 PM PDT 24 2516833213 ps
T167 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3082392671 Jun 21 05:06:36 PM PDT 24 Jun 21 05:06:40 PM PDT 24 2640134725 ps
T168 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.448376932 Jun 21 05:08:08 PM PDT 24 Jun 21 05:08:55 PM PDT 24 34271476426 ps
T449 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1465696989 Jun 21 05:07:31 PM PDT 24 Jun 21 05:07:38 PM PDT 24 2086116010 ps
T450 /workspace/coverage/default/6.sysrst_ctrl_alert_test.3190978264 Jun 21 05:06:56 PM PDT 24 Jun 21 05:07:02 PM PDT 24 2021726397 ps
T451 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2379092645 Jun 21 05:08:22 PM PDT 24 Jun 21 05:08:29 PM PDT 24 2224629282 ps
T384 /workspace/coverage/default/24.sysrst_ctrl_stress_all.1659101056 Jun 21 05:07:32 PM PDT 24 Jun 21 05:12:32 PM PDT 24 151093387660 ps
T452 /workspace/coverage/default/10.sysrst_ctrl_alert_test.131149292 Jun 21 05:07:11 PM PDT 24 Jun 21 05:07:21 PM PDT 24 2013388171 ps
T138 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2449474077 Jun 21 05:08:15 PM PDT 24 Jun 21 05:09:38 PM PDT 24 116412394125 ps
T385 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1109865238 Jun 21 05:08:14 PM PDT 24 Jun 21 05:09:15 PM PDT 24 96708478972 ps
T379 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2559638396 Jun 21 05:08:30 PM PDT 24 Jun 21 05:11:44 PM PDT 24 73469434045 ps
T453 /workspace/coverage/default/9.sysrst_ctrl_stress_all.2461535094 Jun 21 05:07:11 PM PDT 24 Jun 21 05:07:37 PM PDT 24 8365843150 ps
T454 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.795845952 Jun 21 05:08:08 PM PDT 24 Jun 21 05:08:14 PM PDT 24 2519643205 ps
T455 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3346651550 Jun 21 05:08:01 PM PDT 24 Jun 21 05:08:06 PM PDT 24 2616811720 ps
T456 /workspace/coverage/default/22.sysrst_ctrl_smoke.3214404375 Jun 21 05:07:33 PM PDT 24 Jun 21 05:07:43 PM PDT 24 2109519667 ps
T457 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2148331499 Jun 21 05:07:20 PM PDT 24 Jun 21 05:07:28 PM PDT 24 2100633468 ps
T458 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2288788268 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:20 PM PDT 24 2260354792 ps
T459 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3940135203 Jun 21 05:08:06 PM PDT 24 Jun 21 05:08:11 PM PDT 24 2529387055 ps
T460 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.713516538 Jun 21 05:07:20 PM PDT 24 Jun 21 05:07:29 PM PDT 24 2533457247 ps
T461 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.851563637 Jun 21 05:08:17 PM PDT 24 Jun 21 05:08:29 PM PDT 24 2888118594 ps
T462 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2380971450 Jun 21 05:06:43 PM PDT 24 Jun 21 05:07:02 PM PDT 24 27602465699 ps
T463 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3052522425 Jun 21 05:06:43 PM PDT 24 Jun 21 05:06:51 PM PDT 24 2315786947 ps
T339 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.141346997 Jun 21 05:08:33 PM PDT 24 Jun 21 05:12:14 PM PDT 24 84359519383 ps
T464 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.286775024 Jun 21 05:07:49 PM PDT 24 Jun 21 05:07:57 PM PDT 24 2016115687 ps
T370 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3832818399 Jun 21 05:07:56 PM PDT 24 Jun 21 05:12:07 PM PDT 24 99566128566 ps
T342 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1892743515 Jun 21 05:08:35 PM PDT 24 Jun 21 05:08:47 PM PDT 24 43952095401 ps
T343 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3786995353 Jun 21 05:08:51 PM PDT 24 Jun 21 05:12:17 PM PDT 24 111232806890 ps
T465 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3172465434 Jun 21 05:08:14 PM PDT 24 Jun 21 05:08:21 PM PDT 24 2617463505 ps
T382 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1697889022 Jun 21 05:06:57 PM PDT 24 Jun 21 05:08:06 PM PDT 24 107982612911 ps
T254 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.894591175 Jun 21 05:07:49 PM PDT 24 Jun 21 05:08:01 PM PDT 24 27811923486 ps
T355 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2052153193 Jun 21 05:08:38 PM PDT 24 Jun 21 05:09:30 PM PDT 24 56841993082 ps
T466 /workspace/coverage/default/24.sysrst_ctrl_alert_test.2452734011 Jun 21 05:07:40 PM PDT 24 Jun 21 05:07:44 PM PDT 24 2031567053 ps
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