| | | | | | | |
|
prim_sync_reqack |
87.50 |
100.00 |
50.00 |
|
|
100.00 |
100.00 |
|
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_reg_cdc_arb |
92.91 |
96.00 |
93.02 |
|
|
82.61 |
100.00 |
|
prim_reg_cdc_arb |
91.30 |
|
|
|
|
82.61 |
100.00 |
|
prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 ) |
89.02 |
92.00 |
86.05 |
|
|
|
|
|
prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb |
95.83 |
87.50 |
100.00 |
|
|
100.00 |
|
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) |
50.00 |
50.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
sysrst_ctrl_combo |
96.15 |
100.00 |
92.31 |
|
|
|
|
|
prim_reg_cdc |
97.30 |
100.00 |
89.20 |
|
|
100.00 |
100.00 |
|
prim_reg_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) |
87.50 |
|
87.50 |
|
|
|
|
|
prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 ) |
90.91 |
|
90.91 |
|
|
|
|
|
sysrst_ctrl_detect |
98.35 |
100.00 |
96.30 |
|
100.00 |
95.45 |
100.00 |
|
sysrst_ctrl_detect |
100.00 |
|
|
|
100.00 |
|
100.00 |
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 ) |
96.88 |
100.00 |
93.75 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 ) |
95.24 |
|
|
|
|
95.24 |
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 ) |
95.45 |
|
95.45 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 ) |
100.00 |
100.00 |
|
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 ) |
95.65 |
|
|
|
|
95.65 |
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 ) |
94.74 |
|
94.74 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 ) |
95.45 |
|
95.45 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 ) |
94.74 |
|
94.74 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 ) |
100.00 |
100.00 |
|
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
sysrst_ctrl_reg_top |
98.60 |
100.00 |
94.41 |
|
|
100.00 |
100.00 |
|
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
|
sysrst_ctrl |
99.02 |
100.00 |
96.08 |
100.00 |
|
|
100.00 |
|
sysrst_ctrl_comboact |
99.19 |
100.00 |
97.56 |
|
|
100.00 |
|
|
sysrst_ctrl_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
sysrst_ctrl_ulp |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
|
sysrst_ctrl_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
sysrst_ctrl_keyintr |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
|
sysrst_ctrl_pin |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
sysrst_ctrl_autoblock |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
|
prim_generic_flop_2sync |
|
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|