Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1877

1

T1

1

T5

3

T6

1

auto[1]

612

1

T5

8

T7

6

T8

17

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1806

1

T5

6

T6

1

T7

3

auto[1]

683

1

T1

1

T5

5

T7

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T1

1

T5

6

T7

5

auto[1]

537

1

T5

5

T6

1

T7

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1848

1

T5

11

T6

1

T7

6

auto[1]

641

1

T1

1

T7

3

T8

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2321

1

T1

1

T5

11

T6

1

auto[1]

168

1

T8

3

T62

1

T73

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2303

1

T1

1

T5

11

T6

1

auto[1]

186

1

T8

20

T22

4

T23

15

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2190

1

T1

1

T5

11

T6

1

auto[1]

299

1

T8

17

T23

34

T32

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2264

1

T1

1

T5

11

T6

1

auto[1]

225

1

T8

17

T22

4

T23

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2288

1

T1

1

T5

11

T6

1

auto[1]

201

1

T8

14

T23

41

T32

15

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1807

1

T5

3

T6

1

T7

8

auto[1]

682

1

T1

1

T5

8

T7

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	889	1			T1	1		T5	8		T6	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	48	1			T73	2		T180	1		T224	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	34	1			T32	4		T73	2		T224	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T62	1		T73	2		T322	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	86	1			T60	5		T61	15		T314	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T323	1		T324	1		T325	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T74	2		T326	4		T327	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T83	2		T328	3		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	73	1			T61	14		T62	4		T82	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	26	1			T226	2		T323	4		T74	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	44	1			T23	24		T323	3		T202	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T83	4		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	53	1			T32	2		T61	12		T62	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T329	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	7	1			T8	7		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	45	1			T60	8		T61	6		T314	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T322	4		T227	4		T330	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	14	1			T23	7		T32	1		T331	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	9	1			T22	4		T240	2		T332	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T8	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T8	7		T333	1		T328	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	19	1			T8	10		T202	1		T246	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T322	8		T330	4		T334	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T327	4		T335	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T23	3		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T23

15

T60

4

T61

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

127

1

T22

4

T27

10

T183

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T5

6

T319

10

T241

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

115

1

T36

13

T58

1

T177

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

90

1

T8

10

T36

8

T23

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

65

1

T231

7

T244

3

T219

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T28

2

T177

4

T78

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T6

1

T224

4

T74

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

65

1

T8

7

T244

5

T60

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T8

3

T60

5

T180

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T276

2

T336

1

T337

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T27

6

T28

5

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T23

7

T128

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

34

1

T36

1

T68

1

T81

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T183

2

T203

1

T338

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

134

1

T8

7

T61

12

T62

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

47

1

T29

13

T314

2

T248

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T58

1

T32

2

T73

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T7

1

T10

1

T68

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T7

1

T29

5

T58

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T27

2

T68

3

T175

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T1

1

T81

3

T226

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T78

4

T186

2

T276

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

82

1

T7

2

T10

2

T231

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

2

T28

4

T219

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T175

2

T247

2

T261

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T5

2

T10

1

T339

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T29

3

T183

4

T322

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T29

3

T32

2

T247

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T66

3

T177

3

T81

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T204

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded