Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T1

33

T2

10

T14

9

auto[1]

1038

1

T1

27

T2

10

T14

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

509

1

T1

16

T2

8

T14

4

from_0to1

511

1

T1

16

T2

8

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T1

31

T2

6

T14

14

auto[1]

1051

1

T1

29

T2

14

T14

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T1

32

T2

6

T14

11

auto[1]

1055

1

T1

28

T2

14

T14

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T1

1

T14

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T2

1

T14

1

T57

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T1

3

T6

1

T9

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T1

2

T2

2

T14

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T1

4

T2

1

T7

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T1

4

T57

1

T6

3

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T1

1

T2

1

T57

3

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T1

1

T2

2

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T1

3

T14

1

T9

4

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T1

1

T2

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T1

4

T2

2

T6

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T1

2

T2

2

T6

3

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T1

2

T2

1

T14

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

3

T2

1

T14

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T1

1

T57

1

T6

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T2

2

T7

1

T9

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T1

30

T2

9

T14

11

auto[1]

1047

1

T1

30

T2

11

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T1

16

T2

4

T14

4

from_0to1

509

1

T1

15

T2

3

T14

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T1

24

T2

12

T14

11

auto[1]

1082

1

T1

36

T2

8

T14

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T1

32

T2

9

T14

8

auto[1]

1047

1

T1

28

T2

11

T14

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T1

3

T2

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T14

1

T57

3

T6

3

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T1

2

T2

1

T14

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T1

3

T6

1

T9

3

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T1

1

T57

1

T6

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T2

1

T14

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T1

2

T57

2

T6

3

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T1

3

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T1

3

T14

1

T57

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T6

1

T7

3

T9

5

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T1

3

T2

2

T6

2

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T1

2

T7

1

T351

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T1

2

T57

1

T9

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T1

3

T2

1

T7

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T1

1

T14

1

T6

3

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T1

2

T14

2

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T1

26

T2

8

T14

10

auto[1]

967

1

T1

34

T2

12

T14

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T1

17

T2

6

T14

6

from_0to1

520

1

T1

17

T2

6

T14

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T1

26

T2

5

T14

10

auto[1]

1064

1

T1

34

T2

15

T14

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T1

21

T2

13

T14

9

auto[1]

1087

1

T1

39

T2

7

T14

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T14

1

T57

3

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T1

3

T7

2

T9

2

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T1

4

T57

1

T6

3

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T1

2

T2

1

T14

3

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T2

1

T57

1

T6

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T1

1

T14

1

T6

4

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T1

1

T2

2

T9

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T1

5

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T2

1

T57

2

T7

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T1

2

T9

2

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T1

1

T2

2

T14

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T1

4

T2

2

T14

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T1

1

T14

2

T7

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T1

5

T57

3

T6

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T1

1

T2

1

T57

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T1

3

T2

1

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T1

31

T2

7

T14

12

auto[1]

1018

1

T1

29

T2

13

T14

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T1

14

T2

4

T14

5

from_0to1

480

1

T1

13

T2

4

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T1

30

T2

14

T14

7

auto[1]

1029

1

T1

30

T2

6

T14

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T1

24

T2

9

T14

8

auto[1]

1037

1

T1

36

T2

11

T14

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T1

2

T2

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T1

1

T2

1

T6

3

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T1

1

T2

1

T6

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T1

3

T14

2

T7

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T57

1

T9

3

T44

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T1

3

T14

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T1

2

T2

1

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T1

3

T14

1

T57

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T1

1

T2

1

T6

3

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T14

1

T57

1

T9

2

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T1

1

T14

1

T6

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T1

5

T14

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T1

2

T9

2

T31

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T1

3

T2

2

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T6

1

T9

2

T31

3

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T2

1

T14

1

T6

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T1

36

T2

8

T14

8

auto[1]

1072

1

T1

24

T2

12

T14

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T1

14

T2

5

T14

5

from_0to1

494

1

T1

14

T2

4

T14

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T1

33

T2

7

T14

10

auto[1]

1059

1

T1

27

T2

13

T14

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1046

1

T1

33

T2

14

T14

10

auto[1]

1054

1

T1

27

T2

6

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T1

4

T14

2

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T1

2

T7

1

T9

2

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T1

2

T2

2

T6

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T1

2

T6

1

T7

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T1

5

T57

1

T6

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T1

1

T57

1

T6

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T1

2

T2

1

T14

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T1

1

T6

1

T9

3

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T1

1

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T14

1

T57

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T1

1

T2

1

T6

4

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T1

1

T2

1

T14

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T1

2

T2

1

T57

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T1

1

T14

1

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T1

1

T14

1

T6

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T1

1

T2

2

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T1

28

T2

10

T14

11

auto[1]

1058

1

T1

32

T2

10

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T1

15

T2

6

T14

5

from_0to1

496

1

T1

16

T2

7

T14

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T1

32

T2

10

T14

7

auto[1]

1032

1

T1

28

T2

10

T14

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T1

28

T2

8

T14

12

auto[1]

1008

1

T1

32

T2

12

T14

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T1

2

T2

2

T6

4

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T1

1

T2

1

T14

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T1

1

T14

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T1

2

T2

2

T6

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T1

1

T57

1

T6

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T1

3

T2

1

T14

1

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T1

1

T6

1

T7

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T1

3

T2

1

T6

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T1

4

T14

1

T57

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T1

2

T14

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

2

T14

1

T7

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T1

1

T2

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T1

2

T14

1

T9

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T1

5

T2

1

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T2

2

T6

1

T9

4

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T1

1

T2

2

T14

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T1

33

T2

9

T14

7

auto[1]

1039

1

T1

27

T2

11

T14

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T1

14

T2

6

T14

5

from_0to1

510

1

T1

14

T2

5

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T1

37

T2

11

T14

16

auto[1]

1057

1

T1

23

T2

9

T14

4

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T1

31

T2

8

T14

12

auto[1]

1026

1

T1

29

T2

12

T14

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T1

1

T14

2

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T1

3

T57

2

T6

2

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T1

1

T2

2

T351

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T1

1

T6

1

T9

3

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T1

1

T14

2

T57

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T2

1

T6

3

T7

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T1

1

T57

1

T6

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T1

4

T7

1

T9

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T1

5

T14

1

T57

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T1

1

T2

2

T14

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T2

2

T57

1

T6

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T1

2

T57

1

T6

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T1

4

T2

1

T14

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T1

2

T2

3

T57

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T1

1

T6

1

T9

4

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T1

1

T57

1

T6

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1001

1

T1

26

T2

14

T14

10

auto[1]

1099

1

T1

34

T2

6

T14

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

503

1

T1

14

T2

5

T14

3

from_0to1

497

1

T1

15

T2

5

T14

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T1

31

T2

10

T14

10

auto[1]

1051

1

T1

29

T2

10

T14

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T1

21

T2

10

T14

16

auto[1]

1009

1

T1

39

T2

10

T14

4

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T1

1

T2

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T1

1

T2

2

T14

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T1

1

T2

1

T14

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T1

2

T57

2

T6

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T1

3

T2

1

T6

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T2

1

T6

1

T7

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T1

2

T2

1

T6

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T1

2

T2

1

T7

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T1

2

T2

1

T6

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T1

3

T7

3

T31

2

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T1

2

T14

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T1

2

T6

1

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T1

1

T2

1

T57

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

3

T14

1

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T1

1

T14

1

T6

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T1

3

T57

2

T6

1