Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118896

1

T1

495

T2

208

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140326	1			T1	761		T2	215		T3	7
values[0x0]	64073	1			T1	183		T2	148		T3	3
values[0x1]	65295	1			T1	177		T2	136		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147365

1

T1

612

T2

263

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	825	1			T1	5		T2	1		T12	1
valid_sources[0x01]	2364	1			T1	1		T2	5		T5	5
valid_sources[0x02]	696	1			T1	1		T12	3		T4	3
valid_sources[0x03]	873	1			T1	4		T2	2		T14	1
valid_sources[0x04]	783	1			T1	3		T2	8		T5	3
valid_sources[0x05]	815	1			T1	2		T14	1		T4	6
valid_sources[0x06]	805	1			T1	7		T2	5		T5	2
valid_sources[0x07]	832	1			T1	7		T2	2		T5	1
valid_sources[0x08]	1044	1			T1	11		T5	3		T8	7
valid_sources[0x09]	732	1			T1	8		T2	1		T11	2
valid_sources[0x0a]	2275	1			T1	3		T2	1		T6	7
valid_sources[0x0b]	857	1			T1	2		T5	1		T6	2
valid_sources[0x0c]	1619	1			T1	4		T5	2		T8	6
valid_sources[0x0d]	1997	1			T1	7		T2	2		T5	3
valid_sources[0x0e]	866	1			T1	6		T5	4		T8	4
valid_sources[0x0f]	853	1			T1	3		T11	5		T12	1
valid_sources[0x10]	1050	1			T1	12		T2	3		T5	1
valid_sources[0x11]	1065	1			T1	2		T5	5		T6	1
valid_sources[0x12]	763	1			T1	7		T6	2		T7	17
valid_sources[0x13]	927	1			T1	1		T2	3		T5	2
valid_sources[0x14]	1337	1			T1	5		T2	3		T5	1
valid_sources[0x15]	764	1			T1	1		T2	1		T14	1
valid_sources[0x16]	975	1			T1	6		T2	4		T14	1
valid_sources[0x17]	1058	1			T1	4		T2	3		T6	1
valid_sources[0x18]	963	1			T1	3		T2	9		T14	1
valid_sources[0x19]	1927	1			T1	6		T2	1		T6	6
valid_sources[0x1a]	777	1			T1	5		T5	6		T7	86
valid_sources[0x1b]	1130	1			T1	3		T14	3		T5	1
valid_sources[0x1c]	1035	1			T1	5		T14	1		T5	1
valid_sources[0x1d]	874	1			T1	5		T5	2		T6	1
valid_sources[0x1e]	959	1			T1	1		T14	1		T5	3
valid_sources[0x1f]	1858	1			T1	4		T2	4		T14	1
valid_sources[0x20]	1110	1			T1	12		T2	1		T5	5
valid_sources[0x21]	1018	1			T1	6		T2	2		T14	4
valid_sources[0x22]	833	1			T1	4		T2	5		T5	2
valid_sources[0x23]	862	1			T1	3		T2	4		T11	2
valid_sources[0x24]	770	1			T1	5		T2	2		T5	4
valid_sources[0x25]	981	1			T1	8		T2	2		T12	1
valid_sources[0x26]	993	1			T1	5		T2	6		T11	2
valid_sources[0x27]	915	1			T1	5		T2	7		T5	1
valid_sources[0x28]	785	1			T1	6		T2	4		T12	2
valid_sources[0x29]	873	1			T1	4		T14	1		T5	2
valid_sources[0x2a]	893	1			T1	5		T5	2		T6	4
valid_sources[0x2b]	953	1			T1	1		T2	6		T12	1
valid_sources[0x2c]	955	1			T1	4		T2	2		T5	3
valid_sources[0x2d]	696	1			T1	6		T11	2		T5	2
valid_sources[0x2e]	740	1			T1	4		T8	2		T9	3
valid_sources[0x2f]	1082	1			T1	7		T2	1		T14	2
valid_sources[0x30]	833	1			T1	4		T11	6		T14	1
valid_sources[0x31]	1138	1			T1	3		T6	1		T8	7
valid_sources[0x32]	980	1			T1	6		T5	2		T6	6
valid_sources[0x33]	876	1			T1	2		T2	5		T5	1
valid_sources[0x34]	808	1			T1	1		T14	1		T8	8
valid_sources[0x35]	1811	1			T1	3		T2	6		T5	1
valid_sources[0x36]	900	1			T1	3		T5	2		T8	4
valid_sources[0x37]	3809	1			T1	6		T2	2		T5	2
valid_sources[0x38]	858	1			T1	5		T5	3		T7	111
valid_sources[0x39]	904	1			T1	5		T2	5		T57	29
valid_sources[0x3a]	1066	1			T1	6		T2	5		T6	1
valid_sources[0x3b]	1059	1			T1	3		T14	1		T5	1
valid_sources[0x3c]	904	1			T1	5		T5	2		T6	2
valid_sources[0x3d]	1088	1			T1	4		T2	1		T6	6
valid_sources[0x3e]	782	1			T1	8		T2	7		T12	1
valid_sources[0x3f]	1477	1			T1	6		T12	1		T13	1
valid_sources[0x40]	961	1			T1	3		T2	2		T5	1
valid_sources[0x41]	845	1			T1	4		T2	4		T14	2
valid_sources[0x42]	765	1			T1	2		T2	10		T11	3
valid_sources[0x43]	1158	1			T1	7		T2	5		T12	3
valid_sources[0x44]	857	1			T1	3		T5	2		T6	2
valid_sources[0x45]	1266	1			T1	1		T5	2		T6	3
valid_sources[0x46]	992	1			T1	1		T2	2		T5	3
valid_sources[0x47]	1229	1			T1	5		T12	1		T51	1
valid_sources[0x48]	847	1			T1	5		T4	5		T5	1
valid_sources[0x49]	1289	1			T1	8		T5	5		T51	2
valid_sources[0x4a]	806	1			T1	8		T6	22		T51	1
valid_sources[0x4b]	844	1			T1	4		T5	5		T6	6
valid_sources[0x4c]	804	1			T1	3		T11	1		T14	1
valid_sources[0x4d]	781	1			T1	4		T2	2		T11	1
valid_sources[0x4e]	1394	1			T1	5		T5	1		T6	8
valid_sources[0x4f]	859	1			T1	4		T14	2		T5	1
valid_sources[0x50]	1539	1			T1	5		T14	2		T5	3
valid_sources[0x51]	999	1			T1	4		T2	1		T5	3
valid_sources[0x52]	1786	1			T1	4		T2	4		T12	1
valid_sources[0x53]	749	1			T1	3		T13	1		T5	3
valid_sources[0x54]	807	1			T1	1		T6	3		T51	1
valid_sources[0x55]	873	1			T1	4		T2	3		T34	3
valid_sources[0x56]	1126	1			T1	3		T14	2		T5	4
valid_sources[0x57]	1122	1			T14	1		T5	1		T6	2
valid_sources[0x58]	928	1			T1	6		T14	1		T5	1
valid_sources[0x59]	1876	1			T1	8		T14	1		T5	1
valid_sources[0x5a]	720	1			T1	7		T2	3		T14	1
valid_sources[0x5b]	1042	1			T1	4		T8	3		T9	7
valid_sources[0x5c]	1042	1			T1	6		T2	6		T5	3
valid_sources[0x5d]	1354	1			T1	4		T5	1		T6	3
valid_sources[0x5e]	856	1			T1	3		T14	1		T5	1
valid_sources[0x5f]	697	1			T1	1		T14	2		T5	2
valid_sources[0x60]	1085	1			T1	5		T14	1		T5	1
valid_sources[0x61]	822	1			T1	2		T2	5		T5	4
valid_sources[0x62]	2108	1			T1	5		T4	20		T5	1
valid_sources[0x63]	951	1			T1	6		T14	1		T5	2
valid_sources[0x64]	1000	1			T1	4		T2	4		T14	3
valid_sources[0x65]	958	1			T1	6		T2	1		T12	2
valid_sources[0x66]	2926	1			T1	8		T14	1		T5	1
valid_sources[0x67]	732	1			T1	6		T2	1		T5	2
valid_sources[0x68]	1324	1			T1	4		T6	4		T8	4
valid_sources[0x69]	889	1			T1	4		T5	1		T6	2
valid_sources[0x6a]	777	1			T1	5		T2	1		T14	1
valid_sources[0x6b]	1021	1			T1	4		T14	1		T5	3
valid_sources[0x6c]	865	1			T1	8		T6	4		T8	2
valid_sources[0x6d]	1686	1			T1	5		T2	3		T14	1
valid_sources[0x6e]	1986	1			T1	2		T2	2		T11	2
valid_sources[0x6f]	713	1			T1	4		T5	1		T8	9
valid_sources[0x70]	1731	1			T1	3		T8	5		T9	3
valid_sources[0x71]	964	1			T1	3		T2	1		T5	1
valid_sources[0x72]	920	1			T1	7		T2	5		T6	6
valid_sources[0x73]	1065	1			T1	1		T5	1		T6	7
valid_sources[0x74]	2068	1			T1	4		T12	2		T14	2
valid_sources[0x75]	860	1			T1	6		T2	2		T11	8
valid_sources[0x76]	873	1			T1	1		T5	1		T6	8
valid_sources[0x77]	856	1			T1	3		T5	1		T6	1
valid_sources[0x78]	830	1			T1	6		T5	1		T6	12
valid_sources[0x79]	1118	1			T1	2		T2	2		T5	1
valid_sources[0x7a]	968	1			T1	2		T2	1		T5	3
valid_sources[0x7b]	854	1			T1	4		T5	1		T6	3
valid_sources[0x7c]	1118	1			T1	2		T2	2		T12	1
valid_sources[0x7d]	1136	1			T1	6		T2	4		T14	1
valid_sources[0x7e]	790	1			T1	2		T5	1		T6	2
valid_sources[0x7f]	910	1			T1	5		T5	1		T6	5
valid_sources[0x80]	2006	1			T1	8		T8	2		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64910

1

T1

376

T2

105

T3

4

values[0x0]

all_enables

biggest_size

31365

1

T1

79

T2

70

T3

2

values[0x1]

all_enables

biggest_size

22621

1

T1

40

T2

33

T3

2