Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T2,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T72,T92,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T2,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T21
1	-	Covered	T1,T2,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T21
DetectSt	168	Covered	T1,T2,T21
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T2,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T21
DebounceSt->IdleSt	163	Covered	T31,T80,T48
DetectSt->IdleSt	186	Covered	T72,T92,T95
DetectSt->StableSt	191	Covered	T1,T2,T21
IdleSt->DebounceSt	148	Covered	T1,T2,T21
StableSt->IdleSt	206	Covered	T1,T2,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T21
0	1	Covered	T1,T2,T21
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T80,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T21
DetectSt	-	-	-	-	1	-	-	Covered	T72,T92,T95
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	281	0	0
CntIncr_A	7237349	229184	0	0
CntNoWrap_A	7237349	6570224	0	0
DetectStDropOut_A	7237349	3	0	0
DetectedOut_A	7237349	839	0	0
DetectedPulseOut_A	7237349	126	0	0
DisabledIdleSt_A	7237349	6334917	0	0
DisabledNoDetection_A	7237349	6337218	0	0
EnterDebounceSt_A	7237349	152	0	0
EnterDetectSt_A	7237349	129	0	0
EnterStableSt_A	7237349	126	0	0
PulseIsPulse_A	7237349	126	0	0
StayInStableSt	7237349	713	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	6705	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	281	0	0
T1	14749	4	0	0
T2	6923	4	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	4	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	6	0	0
T35	0	4	0	0
T38	0	2	0	0
T80	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	229184	0	0
T1	14749	91	0	0
T2	6923	168	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	57	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	167	0	0
T31	0	15	0	0
T33	0	51	0	0
T34	0	212	0	0
T35	0	2510	0	0
T38	0	39	0	0
T80	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570224	0	0
T1	14749	6770	0	0
T2	6923	1292	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3	0	0
T67	10254	0	0	0
T72	756	1	0	0
T73	29281	0	0	0
T78	359846	0	0	0
T81	10807	0	0	0
T92	0	1	0	0
T95	0	1	0	0
T101	502	0	0	0
T102	503	0	0	0
T103	403	0	0	0
T104	502	0	0	0
T105	1487	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	839	0	0
T1	14749	10	0	0
T2	6923	17	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	8	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	9	0	0
T33	0	7	0	0
T34	0	22	0	0
T35	0	18	0	0
T38	0	11	0	0
T58	0	15	0	0
T80	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	126	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T58	0	3	0	0
T80	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6334917	0	0
T1	14749	6600	0	0
T2	6923	1035	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6337218	0	0
T1	14749	6624	0	0
T2	6923	1049	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	152	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T80	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	129	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T58	0	3	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	126	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T58	0	3	0	0
T80	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	126	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T58	0	3	0	0
T80	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	713	0	0
T1	14749	8	0	0
T2	6923	15	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	7	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	7	0	0
T33	0	6	0	0
T34	0	19	0	0
T35	0	16	0	0
T38	0	10	0	0
T58	0	12	0	0
T80	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6705	0	0
T1	14749	46	0	0
T2	6923	30	0	0
T3	537	1	0	0
T4	7647	34	0	0
T5	0	11	0	0
T11	523	4	0	0
T12	493	8	0	0
T13	449	0	0	0
T14	502	4	0	0
T15	428	4	0	0
T16	600	0	0	0
T21	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	126	0	0
T1	14749	2	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	0	2	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	0	1	0	0
T58	0	3	0	0
T80	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T9,T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Unreachable
1	0	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T48,T50,T66
DetectSt->IdleSt	186	Covered	T9,T78,T79
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T66,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	210	0	0
CntIncr_A	7237349	251837	0	0
CntNoWrap_A	7237349	6570295	0	0
DetectStDropOut_A	7237349	13	0	0
DetectedOut_A	7237349	144204	0	0
DetectedPulseOut_A	7237349	55	0	0
DisabledIdleSt_A	7237349	4835412	0	0
DisabledNoDetection_A	7237349	4837763	0	0
EnterDebounceSt_A	7237349	143	0	0
EnterDetectSt_A	7237349	68	0	0
EnterStableSt_A	7237349	55	0	0
PulseIsPulse_A	7237349	55	0	0
StayInStableSt	7237349	144149	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	6705	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_sticky_sva.StableStDropOut_A	7237349	537070	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	210	0	0
T1	14749	2	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	4	0	0
T9	0	8	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	4	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	4	0	0
T65	0	4	0	0
T66	0	4	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	251837	0	0
T1	14749	82	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	124	0	0
T9	0	137	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	174	0	0
T48	0	38	0	0
T49	0	32528	0	0
T50	0	68	0	0
T65	0	184	0	0
T66	0	176	0	0
T67	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570295	0	0
T1	14749	6772	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	13	0	0
T9	11866	2	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T31	7354	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T52	491	0	0	0
T78	0	3	0	0
T79	0	2	0	0
T111	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	144204	0	0
T1	14749	167	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	135	0	0
T9	0	56	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	733	0	0
T49	0	37171	0	0
T65	0	279	0	0
T67	0	93	0	0
T77	0	135	0	0
T79	0	89	0	0
T108	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	55	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	2	0	0
T49	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4835412	0	0
T1	14749	6304	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4837763	0	0
T1	14749	6328	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	143	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	4	0	0
T65	0	2	0	0
T66	0	4	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	68	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	2	0	0
T49	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	3	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	55	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	2	0	0
T49	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	55	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	2	0	0
T49	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	144149	0	0
T1	14749	166	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	133	0	0
T9	0	54	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	731	0	0
T49	0	37170	0	0
T65	0	277	0	0
T67	0	92	0	0
T77	0	134	0	0
T79	0	88	0	0
T108	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6705	0	0
T1	14749	46	0	0
T2	6923	30	0	0
T3	537	1	0	0
T4	7647	34	0	0
T5	0	11	0	0
T11	523	4	0	0
T12	493	8	0	0
T13	449	0	0	0
T14	502	4	0	0
T15	428	4	0	0
T16	600	0	0	0
T21	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	537070	0	0
T1	14749	212	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	276	0	0
T9	0	186	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	149	0	0
T49	0	63	0	0
T65	0	75	0	0
T67	0	204	0	0
T77	0	57	0	0
T79	0	269	0	0
T108	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T7,T46,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Unreachable
1	0	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T9,T46,T48
DetectSt->IdleSt	186	Covered	T7,T46,T77
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T46,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T7,T46,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	209	0	0
CntIncr_A	7237349	70917	0	0
CntNoWrap_A	7237349	6570296	0	0
DetectStDropOut_A	7237349	19	0	0
DetectedOut_A	7237349	388289	0	0
DetectedPulseOut_A	7237349	48	0	0
DisabledIdleSt_A	7237349	4835412	0	0
DisabledNoDetection_A	7237349	4837763	0	0
EnterDebounceSt_A	7237349	143	0	0
EnterDetectSt_A	7237349	67	0	0
EnterStableSt_A	7237349	48	0	0
PulseIsPulse_A	7237349	48	0	0
StayInStableSt	7237349	388241	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_sticky_sva.StableStDropOut_A	7237349	108109	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	209	0	0
T1	14749	2	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	4	0	0
T9	0	6	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	12	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	4	0	0
T65	0	4	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	70917	0	0
T1	14749	98	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	184	0	0
T9	0	372	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	308	0	0
T48	0	38	0	0
T49	0	106	0	0
T50	0	196	0	0
T65	0	58	0	0
T66	0	72	0	0
T67	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570296	0	0
T1	14749	6772	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	19	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T46	0	5	0	0
T51	495	0	0	0
T77	0	1	0	0
T87	0	2	0	0
T115	0	4	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	388289	0	0
T1	14749	286	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	248	0	0
T9	0	5	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	74	0	0
T66	0	423	0	0
T67	0	87	0	0
T77	0	105	0	0
T78	0	444	0	0
T79	0	509	0	0
T108	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	48	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4835412	0	0
T1	14749	6304	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4837763	0	0
T1	14749	6328	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	143	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	5	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	7	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	67	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	5	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	48	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	48	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	388241	0	0
T1	14749	285	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	247	0	0
T9	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	72	0	0
T66	0	422	0	0
T67	0	86	0	0
T77	0	104	0	0
T78	0	443	0	0
T79	0	508	0	0
T108	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	108109	0	0
T1	14749	65	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	73	0	0
T9	0	79	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T65	0	419	0	0
T66	0	228	0	0
T67	0	207	0	0
T77	0	76	0	0
T78	0	82	0	0
T79	0	275	0	0
T108	0	86	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T7,T46,T65
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Unreachable
1	0	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T46,T48,T50
DetectSt->IdleSt	186	Covered	T7,T46,T65
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T50,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T7,T46,T65
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	208	0	0
CntIncr_A	7237349	199740	0	0
CntNoWrap_A	7237349	6570297	0	0
DetectStDropOut_A	7237349	23	0	0
DetectedOut_A	7237349	700438	0	0
DetectedPulseOut_A	7237349	65	0	0
DisabledIdleSt_A	7237349	4835412	0	0
DisabledNoDetection_A	7237349	4837763	0	0
EnterDebounceSt_A	7237349	121	0	0
EnterDetectSt_A	7237349	88	0	0
EnterStableSt_A	7237349	65	0	0
PulseIsPulse_A	7237349	65	0	0
StayInStableSt	7237349	700373	0	0
gen_high_event_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_sticky_sva.StableStDropOut_A	7237349	658830	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	208	0	0
T1	14749	2	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	4	0	0
T9	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	13	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	4	0	0
T65	0	4	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	199740	0	0
T1	14749	70	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	169	0	0
T9	0	105	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	644	0	0
T48	0	39	0	0
T49	0	25	0	0
T50	0	260	0	0
T65	0	216	0	0
T66	0	32	0	0
T67	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570297	0	0
T1	14749	6772	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	23	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T46	0	5	0	0
T51	495	0	0	0
T65	0	1	0	0
T77	0	3	0	0
T115	0	3	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	700438	0	0
T1	14749	287	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	211	0	0
T9	0	226	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	1	0	0
T49	0	38	0	0
T66	0	223	0	0
T67	0	211	0	0
T78	0	235	0	0
T108	0	4	0	0
T109	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T78	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4835412	0	0
T1	14749	6304	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4837763	0	0
T1	14749	6328	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	121	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	7	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	4	0	0
T65	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	88	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	6	0	0
T49	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T78	0	1	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T78	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	1	0	0
T9	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T78	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	700373	0	0
T1	14749	286	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	210	0	0
T9	0	224	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T49	0	37	0	0
T66	0	222	0	0
T67	0	210	0	0
T78	0	234	0	0
T108	0	3	0	0
T109	0	60	0	0
T124	0	290	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	658830	0	0
T1	14749	107	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T7	0	131	0	0
T9	0	219	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T46	0	69	0	0
T49	0	69711	0	0
T66	0	476	0	0
T67	0	55	0	0
T78	0	360	0	0
T108	0	145	0	0
T109	0	250	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T7,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T31
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T31
0	1	Covered	T31,T125,T126
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T31
1	-	Covered	T31,T125,T126

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T31
DetectSt	168	Covered	T4,T7,T31
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T7,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T31
DebounceSt->IdleSt	163	Covered	T48,T66,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T7,T31
IdleSt->DebounceSt	148	Covered	T4,T7,T31
StableSt->IdleSt	206	Covered	T4,T7,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T31
0	1	Covered	T4,T7,T31
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T127,T128
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T125,T126
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	91	0	0
CntIncr_A	7237349	102246	0	0
CntNoWrap_A	7237349	6570414	0	0
DetectStDropOut_A	7237349	0	0	0
DetectedOut_A	7237349	11859	0	0
DetectedPulseOut_A	7237349	43	0	0
DisabledIdleSt_A	7237349	6288335	0	0
DisabledNoDetection_A	7237349	6290638	0	0
EnterDebounceSt_A	7237349	48	0	0
EnterDetectSt_A	7237349	43	0	0
EnterStableSt_A	7237349	43	0	0
PulseIsPulse_A	7237349	43	0	0
StayInStableSt	7237349	11788	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	91	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T7	0	2	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	4	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T48	0	1	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	3	0	0
T75	0	2	0	0
T78	0	2	0	0
T100	0	2	0	0
T107	427	0	0	0
T125	0	2	0	0
T129	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	102246	0	0
T4	7647	43	0	0
T5	9978	0	0	0
T7	0	71	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	68	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T48	0	38	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	184	0	0
T75	0	11	0	0
T78	0	22	0	0
T100	0	80	0	0
T107	427	0	0	0
T125	0	96	0	0
T129	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570414	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2044	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	11859	0	0
T4	7647	90	0	0
T5	9978	0	0	0
T7	0	45	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	99	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	47	0	0
T75	0	41	0	0
T78	0	43	0	0
T100	0	129	0	0
T107	427	0	0	0
T125	0	44	0	0
T129	0	73	0	0
T130	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6288335	0	0
T1	14749	6774	0	0
T2	6923	1185	0	0
T3	537	136	0	0
T4	7647	1186	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6290638	0	0
T1	14749	6798	0	0
T2	6923	1199	0	0
T3	537	137	0	0
T4	7647	1198	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	48	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T48	0	1	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T78	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	1	0	0
T129	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	11788	0	0
T4	7647	88	0	0
T5	9978	0	0	0
T7	0	43	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	97	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T66	0	45	0	0
T75	0	39	0	0
T78	0	41	0	0
T100	0	127	0	0
T107	427	0	0	0
T125	0	43	0	0
T129	0	71	0	0
T130	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	15	0	0
T29	33478	0	0	0
T30	756	0	0	0
T31	7354	2	0	0
T35	3125	0	0	0
T53	489	0	0	0
T118	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	422	0	0	0
T138	447	0	0	0
T139	672	0	0	0
T140	502	0	0	0
T141	645	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T6,T7,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T132,T133,T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T7,T30,T100
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T30
1	-	Covered	T7,T30,T100

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T30
DetectSt	168	Covered	T6,T7,T30
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T6,T7,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T30
DebounceSt->IdleSt	163	Covered	T48,T143,T130
DetectSt->IdleSt	186	Covered	T132,T133,T142
DetectSt->StableSt	191	Covered	T6,T7,T30
IdleSt->DebounceSt	148	Covered	T6,T7,T30
StableSt->IdleSt	206	Covered	T6,T7,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T30
0	1	Covered	T6,T7,T30
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T143,T130,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T30
DetectSt	-	-	-	-	1	-	-	Covered	T132,T133,T142
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T30,T100
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	137	0	0
CntIncr_A	7237349	3590	0	0
CntNoWrap_A	7237349	6570368	0	0
DetectStDropOut_A	7237349	4	0	0
DetectedOut_A	7237349	4448	0	0
DetectedPulseOut_A	7237349	61	0	0
DisabledIdleSt_A	7237349	6553610	0	0
DisabledNoDetection_A	7237349	6555907	0	0
EnterDebounceSt_A	7237349	72	0	0
EnterDetectSt_A	7237349	65	0	0
EnterStableSt_A	7237349	61	0	0
PulseIsPulse_A	7237349	61	0	0
StayInStableSt	7237349	4365	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	2662	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	137	0	0
T6	11605	2	0	0
T7	28203	2	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	6	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T48	0	1	0	0
T51	495	0	0	0
T71	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T100	0	2	0	0
T143	0	7	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3590	0	0
T6	11605	16	0	0
T7	28203	71	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	90	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T48	0	38	0	0
T51	495	0	0	0
T71	0	15	0	0
T75	0	11	0	0
T76	0	70	0	0
T100	0	80	0	0
T143	0	163	0	0
T144	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570368	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4	0	0
T132	640	1	0	0
T133	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	5600	0	0	0
T147	688	0	0	0
T148	504	0	0	0
T149	422	0	0	0
T150	412	0	0	0
T151	15754	0	0	0
T152	1679	0	0	0
T153	1242	0	0	0
T154	452	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4448	0	0
T6	11605	52	0	0
T7	28203	3	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	185	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	99	0	0
T75	0	1	0	0
T76	0	111	0	0
T100	0	41	0	0
T143	0	143	0	0
T144	0	147	0	0
T155	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	61	0	0
T6	11605	1	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	3	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T100	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6553610	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6555907	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	72	0	0
T6	11605	1	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	3	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T48	0	1	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T100	0	1	0	0
T143	0	4	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T6	11605	1	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	3	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T100	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	61	0	0
T6	11605	1	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	3	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T100	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	61	0	0
T6	11605	1	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	3	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T100	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4365	0	0
T6	11605	50	0	0
T7	28203	2	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	181	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T71	0	98	0	0
T76	0	109	0	0
T77	0	56	0	0
T100	0	40	0	0
T143	0	139	0	0
T144	0	145	0	0
T155	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2662	0	0
T1	14749	32	0	0
T2	6923	31	0	0
T3	537	1	0	0
T4	7647	29	0	0
T11	523	5	0	0
T12	493	3	0	0
T13	449	0	0	0
T14	502	5	0	0
T15	428	1	0	0
T16	600	0	0	0
T56	0	2	0	0
T107	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	39	0	0
T7	28203	1	0	0
T8	34782	0	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T30	0	2	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T51	495	0	0	0
T71	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T100	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T143	0	2	0	0
T156	0	1	0	0