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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.26 93.48 85.71 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT4,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT143
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT4,T7,T126
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT4,T6,T7
1-CoveredT4,T7,T126

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T4,T6,T7
DetectSt 168 Covered T4,T6,T7
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T4,T6,T7


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T4,T6,T7
DebounceSt->IdleSt 163 Covered T48,T157,T118
DetectSt->IdleSt 186 Covered T143
DetectSt->StableSt 191 Covered T4,T6,T7
IdleSt->DebounceSt 148 Covered T4,T6,T7
StableSt->IdleSt 206 Covered T4,T6,T7



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T6,T7
0 1 Covered T4,T6,T7
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T4,T6,T7
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T4,T6,T7
DebounceSt - 0 1 0 - - - Covered T157,T118
DebounceSt - 0 0 - - - - Covered T4,T6,T7
DetectSt - - - - 1 - - Covered T143
DetectSt - - - - 0 1 - Covered T4,T6,T7
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T7,T126
StableSt - - - - - - 0 Covered T4,T6,T7
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 76 0 0
CntIncr_A 7237349 1930 0 0
CntNoWrap_A 7237349 6570429 0 0
DetectStDropOut_A 7237349 1 0 0
DetectedOut_A 7237349 2495 0 0
DetectedPulseOut_A 7237349 35 0 0
DisabledIdleSt_A 7237349 6556307 0 0
DisabledNoDetection_A 7237349 6558616 0 0
EnterDebounceSt_A 7237349 40 0 0
EnterDetectSt_A 7237349 36 0 0
EnterStableSt_A 7237349 35 0 0
PulseIsPulse_A 7237349 35 0 0
StayInStableSt 7237349 2441 0 0
gen_high_level_sva.HighLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 16 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 76 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T7 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 2 0 0
T107 427 0 0 0
T125 0 4 0 0
T126 0 2 0 0
T143 0 4 0 0
T158 0 2 0 0
T159 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 1930 0 0
T4 7647 43 0 0
T5 9978 0 0 0
T6 0 16 0 0
T7 0 30 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 40 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 92 0 0
T107 427 0 0 0
T125 0 108 0 0
T126 0 26 0 0
T143 0 89 0 0
T158 0 47 0 0
T159 0 39 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570429 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 136 0 0
T4 7647 2044 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 1 0 0
T108 605 0 0 0
T143 6170 1 0 0
T160 643 0 0 0
T161 497 0 0 0
T162 1017 0 0 0
T163 525 0 0 0
T164 523 0 0 0
T165 422 0 0 0
T166 502 0 0 0
T167 3004 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 2495 0 0
T4 7647 90 0 0
T5 9978 0 0 0
T6 0 52 0 0
T7 0 83 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 180 0 0
T85 0 41 0 0
T107 427 0 0 0
T125 0 426 0 0
T126 0 12 0 0
T143 0 109 0 0
T158 0 42 0 0
T159 0 52 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 35 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 1 0 0
T85 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T126 0 1 0 0
T143 0 1 0 0
T158 0 1 0 0
T159 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6556307 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 136 0 0
T4 7647 1770 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6558616 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 1783 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 40 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T126 0 1 0 0
T143 0 2 0 0
T158 0 1 0 0
T159 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 36 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 1 0 0
T85 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T126 0 1 0 0
T143 0 2 0 0
T158 0 1 0 0
T159 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 35 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 1 0 0
T85 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T126 0 1 0 0
T143 0 1 0 0
T158 0 1 0 0
T159 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 35 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 1 0 0
T85 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T126 0 1 0 0
T143 0 1 0 0
T158 0 1 0 0
T159 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 2441 0 0
T4 7647 89 0 0
T5 9978 0 0 0
T6 0 50 0 0
T7 0 82 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T66 0 178 0 0
T85 0 39 0 0
T107 427 0 0 0
T125 0 422 0 0
T126 0 11 0 0
T143 0 107 0 0
T158 0 40 0 0
T159 0 50 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 16 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T56 426 0 0 0
T57 504 0 0 0
T107 427 0 0 0
T118 0 1 0 0
T126 0 1 0 0
T135 0 1 0 0
T168 0 1 0 0
T169 0 2 0 0
T170 0 1 0 0
T171 0 1 0 0
T172 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT3,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T4,T6
10CoveredT1,T2,T11
11CoveredT3,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT71,T130,T145
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT4,T6,T31
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T4,T6
1-CoveredT4,T6,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T3,T4,T6
DetectSt 168 Covered T3,T4,T6
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T3,T4,T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T3,T4,T6
DebounceSt->IdleSt 163 Covered T4,T48,T71
DetectSt->IdleSt 186 Covered T71,T130,T145
DetectSt->StableSt 191 Covered T3,T4,T6
IdleSt->DebounceSt 148 Covered T3,T4,T6
StableSt->IdleSt 206 Covered T4,T6,T31



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T3,T4,T6
0 1 Covered T3,T4,T6
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T3,T4,T6
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T3,T4,T6
DebounceSt - 0 1 0 - - - Covered T4,T71,T75
DebounceSt - 0 0 - - - - Covered T3,T4,T6
DetectSt - - - - 1 - - Covered T71,T130,T145
DetectSt - - - - 0 1 - Covered T3,T4,T6
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T6,T31
StableSt - - - - - - 0 Covered T3,T4,T6
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 124 0 0
CntIncr_A 7237349 68284 0 0
CntNoWrap_A 7237349 6570381 0 0
DetectStDropOut_A 7237349 4 0 0
DetectedOut_A 7237349 4568 0 0
DetectedPulseOut_A 7237349 54 0 0
DisabledIdleSt_A 7237349 6424293 0 0
DisabledNoDetection_A 7237349 6426590 0 0
EnterDebounceSt_A 7237349 66 0 0
EnterDetectSt_A 7237349 58 0 0
EnterStableSt_A 7237349 54 0 0
PulseIsPulse_A 7237349 54 0 0
StayInStableSt 7237349 4489 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7237349 2981 0 0
gen_low_level_sva.LowLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 29 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 124 0 0
T3 537 2 0 0
T4 7647 8 0 0
T5 9978 0 0 0
T6 0 4 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 2 0 0
T31 0 4 0 0
T48 0 1 0 0
T50 0 4 0 0
T54 0 2 0 0
T71 0 5 0 0
T173 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 68284 0 0
T3 537 34 0 0
T4 7647 368 0 0
T5 9978 0 0 0
T6 0 26 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 30 0 0
T31 0 68 0 0
T48 0 38 0 0
T50 0 120 0 0
T54 0 33 0 0
T71 0 45 0 0
T173 0 57 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570381 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 134 0 0
T4 7647 2038 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 4 0 0
T64 5020 0 0 0
T66 34604 0 0 0
T71 624 1 0 0
T72 756 0 0 0
T101 502 0 0 0
T110 519 0 0 0
T130 0 1 0 0
T144 617 0 0 0
T145 0 1 0 0
T174 0 1 0 0
T175 11382 0 0 0
T176 10118 0 0 0
T177 38167 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 4568 0 0
T3 537 43 0 0
T4 7647 230 0 0
T5 9978 0 0 0
T6 0 56 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 244 0 0
T31 0 171 0 0
T50 0 86 0 0
T54 0 160 0 0
T71 0 46 0 0
T78 0 42 0 0
T173 0 302 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 54 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T50 0 2 0 0
T54 0 1 0 0
T71 0 1 0 0
T78 0 1 0 0
T173 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6424293 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 3 0 0
T4 7647 1186 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6426590 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 3 0 0
T4 7647 1198 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 66 0 0
T3 537 1 0 0
T4 7647 5 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T48 0 1 0 0
T50 0 2 0 0
T54 0 1 0 0
T71 0 3 0 0
T173 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 58 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T50 0 2 0 0
T54 0 1 0 0
T71 0 2 0 0
T78 0 1 0 0
T173 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 54 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T50 0 2 0 0
T54 0 1 0 0
T71 0 1 0 0
T78 0 1 0 0
T173 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 54 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T50 0 2 0 0
T54 0 1 0 0
T71 0 1 0 0
T78 0 1 0 0
T173 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 4489 0 0
T3 537 41 0 0
T4 7647 225 0 0
T5 9978 0 0 0
T6 0 54 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 243 0 0
T31 0 168 0 0
T50 0 83 0 0
T54 0 158 0 0
T71 0 44 0 0
T78 0 40 0 0
T173 0 300 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 2981 0 0
T1 14749 26 0 0
T2 6923 39 0 0
T3 537 1 0 0
T4 7647 39 0 0
T11 523 6 0 0
T12 493 4 0 0
T13 449 0 0 0
T14 502 7 0 0
T15 428 1 0 0
T16 600 3 0 0
T45 0 4 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 29 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 1 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T107 427 0 0 0
T126 0 1 0 0
T143 0 1 0 0
T157 0 1 0 0
T159 0 1 0 0
T168 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT3,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T4,T6
10CoveredT1,T2,T11
11CoveredT3,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT66,T168
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT4,T7,T31
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T4,T6
1-CoveredT4,T7,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T3,T4,T6
DetectSt 168 Covered T3,T4,T6
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T3,T4,T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T3,T4,T6
DebounceSt->IdleSt 163 Covered T48,T143,T77
DetectSt->IdleSt 186 Covered T66,T168
DetectSt->StableSt 191 Covered T3,T4,T6
IdleSt->DebounceSt 148 Covered T3,T4,T6
StableSt->IdleSt 206 Covered T4,T6,T7



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T3,T4,T6
0 1 Covered T3,T4,T6
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T3,T4,T6
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T3,T4,T6
DebounceSt - 0 1 0 - - - Covered T143,T77,T85
DebounceSt - 0 0 - - - - Covered T3,T4,T6
DetectSt - - - - 1 - - Covered T66,T168
DetectSt - - - - 0 1 - Covered T3,T4,T6
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T7,T31
StableSt - - - - - - 0 Covered T3,T4,T6
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 143 0 0
CntIncr_A 7237349 68736 0 0
CntNoWrap_A 7237349 6570362 0 0
DetectStDropOut_A 7237349 2 0 0
DetectedOut_A 7237349 4438 0 0
DetectedPulseOut_A 7237349 65 0 0
DisabledIdleSt_A 7237349 6423092 0 0
DisabledNoDetection_A 7237349 6425388 0 0
EnterDebounceSt_A 7237349 76 0 0
EnterDetectSt_A 7237349 67 0 0
EnterStableSt_A 7237349 65 0 0
PulseIsPulse_A 7237349 65 0 0
StayInStableSt 7237349 4341 0 0
gen_high_level_sva.HighLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 33 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 143 0 0
T3 537 2 0 0
T4 7647 6 0 0
T5 9978 0 0 0
T6 0 2 0 0
T7 0 6 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 4 0 0
T48 0 1 0 0
T50 0 4 0 0
T58 0 2 0 0
T59 0 2 0 0
T173 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 68736 0 0
T3 537 34 0 0
T4 7647 231 0 0
T5 9978 0 0 0
T6 0 16 0 0
T7 0 172 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 68 0 0
T48 0 40 0 0
T50 0 120 0 0
T58 0 81 0 0
T59 0 17 0 0
T173 0 114 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570362 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 134 0 0
T4 7647 2040 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 2 0 0
T66 34604 1 0 0
T67 10254 0 0 0
T72 756 0 0 0
T73 29281 0 0 0
T81 10807 0 0 0
T101 502 0 0 0
T102 503 0 0 0
T103 403 0 0 0
T104 502 0 0 0
T168 0 1 0 0
T177 38167 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 4438 0 0
T3 537 93 0 0
T4 7647 105 0 0
T5 9978 0 0 0
T6 0 70 0 0
T7 0 238 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 88 0 0
T50 0 73 0 0
T58 0 13 0 0
T59 0 44 0 0
T66 0 41 0 0
T173 0 89 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 65 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 3 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T50 0 2 0 0
T58 0 1 0 0
T59 0 1 0 0
T66 0 1 0 0
T173 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6423092 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 3 0 0
T4 7647 1186 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6425388 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 3 0 0
T4 7647 1198 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 76 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 3 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T48 0 1 0 0
T50 0 2 0 0
T58 0 1 0 0
T59 0 1 0 0
T173 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 67 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 3 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T50 0 2 0 0
T58 0 1 0 0
T59 0 1 0 0
T66 0 2 0 0
T173 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 65 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 3 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T50 0 2 0 0
T58 0 1 0 0
T59 0 1 0 0
T66 0 1 0 0
T173 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 65 0 0
T3 537 1 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T7 0 3 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T50 0 2 0 0
T58 0 1 0 0
T59 0 1 0 0
T66 0 1 0 0
T173 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 4341 0 0
T3 537 91 0 0
T4 7647 101 0 0
T5 9978 0 0 0
T6 0 68 0 0
T7 0 233 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 86 0 0
T50 0 70 0 0
T58 0 12 0 0
T59 0 42 0 0
T66 0 40 0 0
T173 0 86 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 33 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T7 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T58 0 1 0 0
T66 0 1 0 0
T77 0 1 0 0
T107 427 0 0 0
T125 0 1 0 0
T126 0 1 0 0
T173 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT4,T6,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT4,T6,T31
10CoveredT1,T2,T11
11CoveredT4,T6,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT4,T6,T31
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT4,T6,T31
01CoveredT4,T6,T31
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT4,T6,T31
1-CoveredT4,T6,T31

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T4,T6,T31
DetectSt 168 Covered T4,T6,T31
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T4,T6,T31


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T4,T6,T31
DebounceSt->IdleSt 163 Covered T48,T69
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T4,T6,T31
IdleSt->DebounceSt 148 Covered T4,T6,T31
StableSt->IdleSt 206 Covered T4,T6,T31



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T6,T31
0 1 Covered T4,T6,T31
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T4,T6,T31
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T4,T6,T31
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T4,T6,T31
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T4,T6,T31
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T4,T6,T31
StableSt - - - - - - 0 Covered T4,T6,T31
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 86 0 0
CntIncr_A 7237349 2146 0 0
CntNoWrap_A 7237349 6570419 0 0
DetectStDropOut_A 7237349 0 0 0
DetectedOut_A 7237349 3949 0 0
DetectedPulseOut_A 7237349 42 0 0
DisabledIdleSt_A 7237349 6552835 0 0
DisabledNoDetection_A 7237349 6555139 0 0
EnterDebounceSt_A 7237349 44 0 0
EnterDetectSt_A 7237349 42 0 0
EnterStableSt_A 7237349 42 0 0
PulseIsPulse_A 7237349 42 0 0
StayInStableSt 7237349 3883 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7237349 6505 0 0
gen_low_level_sva.LowLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 18 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 86 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 4 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 2 0 0
T31 0 4 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 1 0 0
T50 0 2 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 2 0 0
T107 427 0 0 0
T125 0 4 0 0
T143 0 2 0 0
T173 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 2146 0 0
T4 7647 137 0 0
T5 9978 0 0 0
T6 0 20 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 30 0 0
T31 0 68 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 38 0 0
T50 0 60 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 80 0 0
T107 427 0 0 0
T125 0 108 0 0
T143 0 69 0 0
T173 0 57 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570419 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 136 0 0
T4 7647 2042 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 3949 0 0
T4 7647 210 0 0
T5 9978 0 0 0
T6 0 87 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 183 0 0
T31 0 146 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 105 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 40 0 0
T107 427 0 0 0
T125 0 83 0 0
T143 0 115 0 0
T158 0 41 0 0
T173 0 198 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 42 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T143 0 1 0 0
T158 0 1 0 0
T173 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6552835 0 0
T1 14749 6774 0 0
T2 6923 1296 0 0
T3 537 136 0 0
T4 7647 1186 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6555139 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 1198 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 44 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T48 0 1 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T143 0 1 0 0
T173 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 42 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T143 0 1 0 0
T158 0 1 0 0
T173 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 42 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T143 0 1 0 0
T158 0 1 0 0
T173 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 42 0 0
T4 7647 2 0 0
T5 9978 0 0 0
T6 0 2 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 2 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 2 0 0
T143 0 1 0 0
T158 0 1 0 0
T173 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 3883 0 0
T4 7647 207 0 0
T5 9978 0 0 0
T6 0 84 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 182 0 0
T31 0 143 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 104 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 39 0 0
T107 427 0 0 0
T125 0 80 0 0
T143 0 113 0 0
T158 0 39 0 0
T173 0 197 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6505 0 0
T1 14749 37 0 0
T2 6923 27 0 0
T3 537 0 0 0
T4 7647 33 0 0
T5 0 10 0 0
T11 523 4 0 0
T12 493 6 0 0
T13 449 0 0 0
T14 502 4 0 0
T15 428 3 0 0
T16 600 0 0 0
T56 0 3 0 0
T107 0 2 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 18 0 0
T4 7647 1 0 0
T5 9978 0 0 0
T6 0 1 0 0
T16 600 0 0 0
T21 751 0 0 0
T30 0 1 0 0
T31 0 1 0 0
T33 753 0 0 0
T34 744 0 0 0
T45 631 0 0 0
T50 0 1 0 0
T56 426 0 0 0
T57 504 0 0 0
T100 0 1 0 0
T107 427 0 0 0
T125 0 1 0 0
T157 0 2 0 0
T168 0 1 0 0
T173 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT2,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT2,T4,T6
01CoveredT76
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T4,T6
01CoveredT2,T4,T6
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT2,T4,T6
1-CoveredT2,T4,T6

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T2,T4,T6
DetectSt 168 Covered T2,T4,T6
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T2,T4,T6


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T2,T4,T6
DebounceSt->IdleSt 163 Covered T48,T85,T178
DetectSt->IdleSt 186 Covered T76
DetectSt->StableSt 191 Covered T2,T4,T6
IdleSt->DebounceSt 148 Covered T2,T4,T6
StableSt->IdleSt 206 Covered T2,T4,T6



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T2,T4,T6
0 1 Covered T2,T4,T6
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T2,T4,T6
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T2,T4,T6
DebounceSt - 0 1 0 - - - Covered T85,T178,T179
DebounceSt - 0 0 - - - - Covered T2,T4,T6
DetectSt - - - - 1 - - Covered T76
DetectSt - - - - 0 1 - Covered T2,T4,T6
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T2,T4,T6
StableSt - - - - - - 0 Covered T2,T4,T6
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 123 0 0
CntIncr_A 7237349 3178 0 0
CntNoWrap_A 7237349 6570382 0 0
DetectStDropOut_A 7237349 1 0 0
DetectedOut_A 7237349 3625 0 0
DetectedPulseOut_A 7237349 57 0 0
DisabledIdleSt_A 7237349 6555608 0 0
DisabledNoDetection_A 7237349 6557912 0 0
EnterDebounceSt_A 7237349 65 0 0
EnterDetectSt_A 7237349 58 0 0
EnterStableSt_A 7237349 57 0 0
PulseIsPulse_A 7237349 57 0 0
StayInStableSt 7237349 3544 0 0
gen_high_level_sva.HighLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 33 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 123 0 0
T2 6923 4 0 0
T3 537 0 0 0
T4 7647 8 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T48 0 1 0 0
T50 0 2 0 0
T76 0 2 0 0
T129 0 2 0 0
T143 0 4 0 0
T144 0 2 0 0
T173 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 3178 0 0
T2 6923 26 0 0
T3 537 0 0 0
T4 7647 274 0 0
T5 9978 0 0 0
T6 0 10 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T48 0 39 0 0
T50 0 60 0 0
T76 0 70 0 0
T129 0 23 0 0
T143 0 57 0 0
T144 0 60 0 0
T173 0 114 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570382 0 0
T1 14749 6774 0 0
T2 6923 1292 0 0
T3 537 136 0 0
T4 7647 2038 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 1 0 0
T76 591 1 0 0
T129 593 0 0 0
T180 9613 0 0 0
T181 881 0 0 0
T182 70988 0 0 0
T183 19780 0 0 0
T184 522 0 0 0
T185 720 0 0 0
T186 17044 0 0 0
T187 8403 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 3625 0 0
T2 6923 15 0 0
T3 537 0 0 0
T4 7647 218 0 0
T5 9978 0 0 0
T6 0 63 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 31 0 0
T125 0 282 0 0
T129 0 5 0 0
T143 0 97 0 0
T144 0 147 0 0
T156 0 41 0 0
T173 0 139 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 57 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 1 0 0
T125 0 2 0 0
T129 0 1 0 0
T143 0 2 0 0
T144 0 1 0 0
T156 0 1 0 0
T173 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6555608 0 0
T1 14749 6774 0 0
T2 6923 1185 0 0
T3 537 136 0 0
T4 7647 1186 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6557912 0 0
T1 14749 6798 0 0
T2 6923 1199 0 0
T3 537 137 0 0
T4 7647 1198 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 65 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T48 0 1 0 0
T50 0 1 0 0
T76 0 1 0 0
T129 0 1 0 0
T143 0 2 0 0
T144 0 1 0 0
T173 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 58 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 1 0 0
T76 0 1 0 0
T125 0 2 0 0
T129 0 1 0 0
T143 0 2 0 0
T144 0 1 0 0
T173 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 57 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 1 0 0
T125 0 2 0 0
T129 0 1 0 0
T143 0 2 0 0
T144 0 1 0 0
T156 0 1 0 0
T173 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 57 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 4 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 1 0 0
T125 0 2 0 0
T129 0 1 0 0
T143 0 2 0 0
T144 0 1 0 0
T156 0 1 0 0
T173 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 3544 0 0
T2 6923 13 0 0
T3 537 0 0 0
T4 7647 213 0 0
T5 9978 0 0 0
T6 0 62 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 30 0 0
T125 0 279 0 0
T129 0 4 0 0
T143 0 94 0 0
T144 0 145 0 0
T156 0 39 0 0
T173 0 137 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 33 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 3 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T50 0 1 0 0
T85 0 1 0 0
T125 0 1 0 0
T129 0 1 0 0
T143 0 1 0 0
T173 0 2 0 0
T178 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T2,T3 VC_COV_UNR
1CoveredT2,T6,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T2,T11
11CoveredT2,T6,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT2,T6,T31
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT2,T6,T31
01CoveredT2,T54,T100
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT2,T6,T31
1-CoveredT2,T54,T100

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T2,T6,T31
DetectSt 168 Covered T2,T6,T31
IdleSt 163 Covered T1,T2,T3
StableSt 191 Covered T2,T6,T31


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T2,T6,T31
DebounceSt->IdleSt 163 Covered T2,T48,T85
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T2,T6,T31
IdleSt->DebounceSt 148 Covered T2,T6,T31
StableSt->IdleSt 206 Covered T2,T6,T31



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T2,T6,T31
0 1 Covered T2,T6,T31
0 0 Excluded T1,T2,T3 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T2,T6,T31
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T48,T69
DebounceSt - 0 1 1 - - - Covered T2,T6,T31
DebounceSt - 0 1 0 - - - Covered T85
DebounceSt - 0 0 - - - - Covered T2,T6,T31
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T2,T6,T31
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T2,T54,T100
StableSt - - - - - - 0 Covered T2,T6,T31
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7237349 59 0 0
CntIncr_A 7237349 36451 0 0
CntNoWrap_A 7237349 6570446 0 0
DetectStDropOut_A 7237349 0 0 0
DetectedOut_A 7237349 11061 0 0
DetectedPulseOut_A 7237349 28 0 0
DisabledIdleSt_A 7237349 6291820 0 0
DisabledNoDetection_A 7237349 6294129 0 0
EnterDebounceSt_A 7237349 32 0 0
EnterDetectSt_A 7237349 28 0 0
EnterStableSt_A 7237349 28 0 0
PulseIsPulse_A 7237349 28 0 0
StayInStableSt 7237349 11015 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7237349 6137 0 0
gen_low_level_sva.LowLevelEvent_A 7237349 6572858 0 0
gen_not_sticky_sva.StableStDropOut_A 7237349 10 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 59 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 2 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 2 0 0
T48 0 1 0 0
T50 0 2 0 0
T54 0 2 0 0
T71 0 4 0 0
T76 0 2 0 0
T100 0 2 0 0
T129 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 36451 0 0
T2 6923 22 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 10 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 34 0 0
T48 0 39 0 0
T50 0 60 0 0
T54 0 33 0 0
T71 0 30 0 0
T76 0 70 0 0
T100 0 80 0 0
T129 0 23 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6570446 0 0
T1 14749 6774 0 0
T2 6923 1294 0 0
T3 537 136 0 0
T4 7647 2046 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 11061 0 0
T2 6923 40 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 44 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 157 0 0
T50 0 208 0 0
T54 0 85 0 0
T71 0 81 0 0
T76 0 41 0 0
T100 0 40 0 0
T129 0 43 0 0
T143 0 40 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 28 0 0
T2 6923 1 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 1 0 0
T50 0 1 0 0
T54 0 1 0 0
T71 0 2 0 0
T76 0 1 0 0
T100 0 1 0 0
T129 0 1 0 0
T143 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6291820 0 0
T1 14749 6774 0 0
T2 6923 1185 0 0
T3 537 3 0 0
T4 7647 2046 0 0
T11 523 122 0 0
T12 493 92 0 0
T13 449 48 0 0
T14 502 101 0 0
T15 428 27 0 0
T16 600 199 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6294129 0 0
T1 14749 6798 0 0
T2 6923 1199 0 0
T3 537 3 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 32 0 0
T2 6923 2 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 1 0 0
T48 0 1 0 0
T50 0 1 0 0
T54 0 1 0 0
T71 0 2 0 0
T76 0 1 0 0
T100 0 1 0 0
T129 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 28 0 0
T2 6923 1 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 1 0 0
T50 0 1 0 0
T54 0 1 0 0
T71 0 2 0 0
T76 0 1 0 0
T100 0 1 0 0
T129 0 1 0 0
T143 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 28 0 0
T2 6923 1 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 1 0 0
T50 0 1 0 0
T54 0 1 0 0
T71 0 2 0 0
T76 0 1 0 0
T100 0 1 0 0
T129 0 1 0 0
T143 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 28 0 0
T2 6923 1 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 1 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 1 0 0
T50 0 1 0 0
T54 0 1 0 0
T71 0 2 0 0
T76 0 1 0 0
T100 0 1 0 0
T129 0 1 0 0
T143 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 11015 0 0
T2 6923 39 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T6 0 42 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T31 0 155 0 0
T50 0 206 0 0
T54 0 84 0 0
T71 0 79 0 0
T76 0 39 0 0
T100 0 39 0 0
T129 0 41 0 0
T143 0 38 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6137 0 0
T1 14749 33 0 0
T2 6923 32 0 0
T3 537 0 0 0
T4 7647 33 0 0
T5 0 15 0 0
T11 523 6 0 0
T12 493 5 0 0
T13 449 1 0 0
T14 502 4 0 0
T15 428 2 0 0
T16 600 0 0 0
T56 0 1 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 6572858 0 0
T1 14749 6798 0 0
T2 6923 1311 0 0
T3 537 137 0 0
T4 7647 2060 0 0
T11 523 123 0 0
T12 493 93 0 0
T13 449 49 0 0
T14 502 102 0 0
T15 428 28 0 0
T16 600 200 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7237349 10 0 0
T2 6923 1 0 0
T3 537 0 0 0
T4 7647 0 0 0
T5 9978 0 0 0
T11 523 0 0 0
T12 493 0 0 0
T13 449 0 0 0
T14 502 0 0 0
T15 428 0 0 0
T16 600 0 0 0
T54 0 1 0 0
T71 0 2 0 0
T100 0 1 0 0
T131 0 1 0 0
T132 0 1 0 0
T170 0 1 0 0
T179 0 1 0 0
T188 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%