Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T4,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T31
0	1	Covered	T75,T129,T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T31
0	1	Covered	T2,T4,T173
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T31
1	-	Covered	T2,T4,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T31
DetectSt	168	Covered	T2,T4,T31
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T4,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T31
DebounceSt->IdleSt	163	Covered	T59,T48,T143
DetectSt->IdleSt	186	Covered	T75,T129,T132
DetectSt->StableSt	191	Covered	T2,T4,T31
IdleSt->DebounceSt	148	Covered	T2,T4,T31
StableSt->IdleSt	206	Covered	T2,T4,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T31
0	1	Covered	T2,T4,T31
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T143,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T31
DetectSt	-	-	-	-	1	-	-	Covered	T75,T129,T132
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T173
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	137	0	0
CntIncr_A	7237349	73331	0	0
CntNoWrap_A	7237349	6570368	0	0
DetectStDropOut_A	7237349	6	0	0
DetectedOut_A	7237349	26023	0	0
DetectedPulseOut_A	7237349	59	0	0
DisabledIdleSt_A	7237349	6290446	0	0
DisabledNoDetection_A	7237349	6292747	0	0
EnterDebounceSt_A	7237349	73	0	0
EnterDetectSt_A	7237349	65	0	0
EnterStableSt_A	7237349	59	0	0
PulseIsPulse_A	7237349	59	0	0
StayInStableSt	7237349	25931	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	137	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	6	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	2	0	0
T48	0	1	0	0
T59	0	1	0	0
T66	0	2	0	0
T75	0	2	0	0
T129	0	4	0	0
T144	0	2	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	73331	0	0
T2	6923	13	0	0
T3	537	0	0	0
T4	7647	282	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	34	0	0
T48	0	38	0	0
T59	0	17	0	0
T66	0	92	0	0
T75	0	11	0	0
T129	0	46	0	0
T144	0	60	0	0
T173	0	114	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570368	0	0
T1	14749	6774	0	0
T2	6923	1294	0	0
T3	537	136	0	0
T4	7647	2040	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6	0	0
T75	474	1	0	0
T76	591	0	0	0
T129	593	1	0	0
T132	0	1	0	0
T135	0	1	0	0
T180	9613	0	0	0
T181	881	0	0	0
T182	70988	0	0	0
T183	19780	0	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	419	0	0	0
T193	445	0	0	0
T194	734	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	26023	0	0
T2	6923	66	0	0
T3	537	0	0	0
T4	7647	125	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	47	0	0
T66	0	39	0	0
T77	0	241	0	0
T129	0	5	0	0
T143	0	114	0	0
T144	0	40	0	0
T173	0	330	0	0
T195	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	59	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	1	0	0
T66	0	1	0	0
T77	0	3	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0
T195	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6290446	0	0
T1	14749	6774	0	0
T2	6923	1185	0	0
T3	537	136	0	0
T4	7647	1462	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6292747	0	0
T1	14749	6798	0	0
T2	6923	1199	0	0
T3	537	137	0	0
T4	7647	1475	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	73	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	1	0	0
T48	0	1	0	0
T59	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T129	0	2	0	0
T144	0	1	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T77	0	3	0	0
T129	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	59	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	1	0	0
T66	0	1	0	0
T77	0	3	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0
T195	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	59	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	1	0	0
T66	0	1	0	0
T77	0	3	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0
T195	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	25931	0	0
T2	6923	65	0	0
T3	537	0	0	0
T4	7647	121	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T31	0	45	0	0
T66	0	38	0	0
T77	0	236	0	0
T129	0	4	0	0
T143	0	112	0	0
T144	0	38	0	0
T173	0	327	0	0
T195	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	26	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T66	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T126	0	1	0	0
T129	0	1	0	0
T173	0	1	0	0
T178	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T3,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T11
1	1	Covered	T3,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T4,T7,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T7
1	-	Covered	T4,T7,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T7
DetectSt	168	Covered	T3,T4,T7
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T3,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T7
DebounceSt->IdleSt	163	Covered	T4,T48,T133
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T4,T7
IdleSt->DebounceSt	148	Covered	T3,T4,T7
StableSt->IdleSt	206	Covered	T4,T7,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T54
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	68	0	0
CntIncr_A	7237349	1688	0	0
CntNoWrap_A	7237349	6570437	0	0
DetectStDropOut_A	7237349	0	0	0
DetectedOut_A	7237349	2619	0	0
DetectedPulseOut_A	7237349	32	0	0
DisabledIdleSt_A	7237349	6556721	0	0
DisabledNoDetection_A	7237349	6559029	0	0
EnterDebounceSt_A	7237349	36	0	0
EnterDetectSt_A	7237349	32	0	0
EnterStableSt_A	7237349	32	0	0
PulseIsPulse_A	7237349	32	0	0
StayInStableSt	7237349	2572	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	6092	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	68	0	0
T3	537	2	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	2	0	0
T48	0	1	0	0
T54	0	2	0	0
T59	0	2	0	0
T71	0	4	0	0
T75	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1688	0	0
T3	537	34	0	0
T4	7647	188	0	0
T5	9978	0	0	0
T7	0	71	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	30	0	0
T48	0	40	0	0
T54	0	33	0	0
T59	0	17	0	0
T71	0	30	0	0
T75	0	11	0	0
T173	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570437	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	134	0	0
T4	7647	2043	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2619	0	0
T3	537	44	0	0
T4	7647	38	0	0
T5	9978	0	0	0
T7	0	209	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	146	0	0
T54	0	8	0	0
T59	0	44	0	0
T71	0	86	0	0
T75	0	41	0	0
T143	0	40	0	0
T173	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	32	0	0
T3	537	1	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T143	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6556721	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	3	0	0
T4	7647	1462	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6559029	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	3	0	0
T4	7647	1475	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36	0	0
T3	537	1	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	32	0	0
T3	537	1	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T143	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	32	0	0
T3	537	1	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T143	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	32	0	0
T3	537	1	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T71	0	2	0	0
T75	0	1	0	0
T143	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2572	0	0
T3	537	42	0	0
T4	7647	37	0	0
T5	9978	0	0	0
T7	0	208	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	144	0	0
T54	0	7	0	0
T59	0	42	0	0
T71	0	83	0	0
T75	0	39	0	0
T143	0	39	0	0
T173	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6092	0	0
T1	14749	31	0	0
T2	6923	27	0	0
T3	537	1	0	0
T4	7647	37	0	0
T5	0	10	0	0
T11	523	5	0	0
T12	493	5	0	0
T13	449	1	0	0
T14	502	4	0	0
T15	428	1	0	0
T16	600	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	17	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T16	600	0	0	0
T21	751	0	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T54	0	1	0	0
T56	426	0	0	0
T57	504	0	0	0
T71	0	1	0	0
T107	427	0	0	0
T118	0	2	0	0
T125	0	1	0	0
T132	0	2	0	0
T143	0	1	0	0
T173	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T3,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T11
1	1	Covered	T3,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T4,T7,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T7
1	-	Covered	T4,T7,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T7
DetectSt	168	Covered	T3,T4,T7
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T3,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T7
DebounceSt->IdleSt	163	Covered	T48,T143,T77
DetectSt->IdleSt	186	Covered	T168
DetectSt->StableSt	191	Covered	T3,T4,T7
IdleSt->DebounceSt	148	Covered	T3,T4,T7
StableSt->IdleSt	206	Covered	T4,T7,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T143,T77,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	1	-	-	Covered	T168
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T31
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	108	0	0
CntIncr_A	7237349	137988	0	0
CntNoWrap_A	7237349	6570397	0	0
DetectStDropOut_A	7237349	1	0	0
DetectedOut_A	7237349	25989	0	0
DetectedPulseOut_A	7237349	50	0	0
DisabledIdleSt_A	7237349	6290599	0	0
DisabledNoDetection_A	7237349	6292905	0	0
EnterDebounceSt_A	7237349	57	0	0
EnterDetectSt_A	7237349	51	0	0
EnterStableSt_A	7237349	50	0	0
PulseIsPulse_A	7237349	50	0	0
StayInStableSt	7237349	25913	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	108	0	0
T3	537	2	0	0
T4	7647	6	0	0
T5	9978	0	0	0
T7	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	4	0	0
T48	0	1	0	0
T50	0	4	0	0
T58	0	2	0	0
T76	0	2	0	0
T100	0	4	0	0
T143	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	137988	0	0
T3	537	34	0	0
T4	7647	180	0	0
T5	9978	0	0	0
T7	0	142	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	68	0	0
T48	0	39	0	0
T50	0	120	0	0
T58	0	81	0	0
T76	0	70	0	0
T100	0	160	0	0
T143	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570397	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	134	0	0
T4	7647	2040	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1	0	0
T120	21055	0	0	0
T157	912	0	0	0
T168	7626	1	0	0
T198	869	0	0	0
T199	522	0	0	0
T200	555	0	0	0
T201	566	0	0	0
T202	15809	0	0	0
T203	21360	0	0	0
T204	22924	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	25989	0	0
T3	537	43	0	0
T4	7647	449	0	0
T5	9978	0	0	0
T7	0	227	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	97	0	0
T50	0	177	0	0
T58	0	13	0	0
T76	0	112	0	0
T100	0	86	0	0
T143	0	32	0	0
T155	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	50	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T50	0	2	0	0
T58	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6290599	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	3	0	0
T4	7647	1186	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6292905	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	3	0	0
T4	7647	1198	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	57	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T58	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T143	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	51	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T50	0	2	0	0
T58	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	50	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T50	0	2	0	0
T58	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	50	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	2	0	0
T50	0	2	0	0
T58	0	1	0	0
T76	0	1	0	0
T100	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	25913	0	0
T3	537	41	0	0
T4	7647	445	0	0
T5	9978	0	0	0
T7	0	225	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	94	0	0
T50	0	174	0	0
T58	0	12	0	0
T76	0	110	0	0
T100	0	83	0	0
T125	0	97	0	0
T143	0	31	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	24	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T7	0	2	0	0
T16	600	0	0	0
T21	751	0	0	0
T31	0	1	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T50	0	1	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	1	0	0
T100	0	1	0	0
T107	427	0	0	0
T125	0	2	0	0
T143	0	1	0	0
T155	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T4,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T11
1	1	Covered	T2,T4,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T7
1	-	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T7
DetectSt	168	Covered	T2,T4,T7
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T7
DebounceSt->IdleSt	163	Covered	T48,T69,T128
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T4,T7
IdleSt->DebounceSt	148	Covered	T2,T4,T7
StableSt->IdleSt	206	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T128
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	75	0	0
CntIncr_A	7237349	36900	0	0
CntNoWrap_A	7237349	6570430	0	0
DetectStDropOut_A	7237349	0	0	0
DetectedOut_A	7237349	11203	0	0
DetectedPulseOut_A	7237349	36	0	0
DisabledIdleSt_A	7237349	6419134	0	0
DisabledNoDetection_A	7237349	6421433	0	0
EnterDebounceSt_A	7237349	39	0	0
EnterDetectSt_A	7237349	36	0	0
EnterStableSt_A	7237349	36	0	0
PulseIsPulse_A	7237349	36	0	0
StayInStableSt	7237349	11152	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	6083	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	75	0	0
T2	6923	2	0	0
T3	537	0	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T7	0	4	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T143	0	6	0	0
T155	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36900	0	0
T2	6923	13	0	0
T3	537	0	0	0
T4	7647	43	0	0
T5	9978	0	0	0
T7	0	142	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	30	0	0
T31	0	34	0	0
T48	0	40	0	0
T50	0	60	0	0
T143	0	143	0	0
T155	0	43	0	0
T173	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570430	0	0
T1	14749	6774	0	0
T2	6923	1294	0	0
T3	537	136	0	0
T4	7647	2044	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	11203	0	0
T2	6923	58	0	0
T3	537	0	0	0
T4	7647	5	0	0
T5	9978	0	0	0
T7	0	68	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	8	0	0
T31	0	173	0	0
T50	0	1	0	0
T143	0	127	0	0
T155	0	42	0	0
T158	0	41	0	0
T173	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T50	0	1	0	0
T143	0	3	0	0
T155	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6419134	0	0
T1	14749	6774	0	0
T2	6923	1185	0	0
T3	537	3	0	0
T4	7647	1770	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6421433	0	0
T1	14749	6798	0	0
T2	6923	1199	0	0
T3	537	3	0	0
T4	7647	1783	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	39	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T143	0	3	0	0
T155	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T50	0	1	0	0
T143	0	3	0	0
T155	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T50	0	1	0	0
T143	0	3	0	0
T155	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	36	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T50	0	1	0	0
T143	0	3	0	0
T155	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	11152	0	0
T2	6923	57	0	0
T3	537	0	0	0
T4	7647	4	0	0
T5	9978	0	0	0
T7	0	65	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	7	0	0
T31	0	172	0	0
T85	0	260	0	0
T143	0	122	0	0
T155	0	40	0	0
T158	0	39	0	0
T173	0	97	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6083	0	0
T1	14749	33	0	0
T2	6923	22	0	0
T3	537	0	0	0
T4	7647	26	0	0
T5	0	9	0	0
T11	523	5	0	0
T12	493	11	0	0
T13	449	1	0	0
T14	502	7	0	0
T15	428	2	0	0
T16	600	0	0	0
T56	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	21	0	0
T2	6923	1	0	0
T3	537	0	0	0
T4	7647	1	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T50	0	1	0	0
T143	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T11
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T179,T171,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T4,T48,T158
DetectSt->IdleSt	186	Covered	T179,T171,T191
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T158,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T179,T171,T191
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	135	0	0
CntIncr_A	7237349	3709	0	0
CntNoWrap_A	7237349	6570370	0	0
DetectStDropOut_A	7237349	3	0	0
DetectedOut_A	7237349	5029	0	0
DetectedPulseOut_A	7237349	62	0	0
DisabledIdleSt_A	7237349	6553453	0	0
DisabledNoDetection_A	7237349	6555752	0	0
EnterDebounceSt_A	7237349	70	0	0
EnterDetectSt_A	7237349	65	0	0
EnterStableSt_A	7237349	62	0	0
PulseIsPulse_A	7237349	62	0	0
StayInStableSt	7237349	4944	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	135	0	0
T2	6923	2	0	0
T3	537	2	0	0
T4	7647	7	0	0
T5	9978	0	0	0
T7	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	6	0	0
T31	0	2	0	0
T48	0	1	0	0
T54	0	2	0	0
T100	0	2	0	0
T173	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3709	0	0
T2	6923	13	0	0
T3	537	34	0	0
T4	7647	325	0	0
T5	9978	0	0	0
T7	0	30	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	90	0	0
T31	0	34	0	0
T48	0	40	0	0
T54	0	33	0	0
T100	0	80	0	0
T173	0	114	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570370	0	0
T1	14749	6774	0	0
T2	6923	1294	0	0
T3	537	134	0	0
T4	7647	2039	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3	0	0
T87	18084	0	0	0
T88	12025	0	0	0
T171	0	1	0	0
T179	806	1	0	0
T191	0	1	0	0
T205	10036	0	0	0
T206	502	0	0	0
T207	503	0	0	0
T208	493	0	0	0
T209	776	0	0	0
T210	70630	0	0	0
T211	567	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	5029	0	0
T2	6923	40	0	0
T3	537	14	0	0
T4	7647	99	0	0
T5	9978	0	0	0
T7	0	159	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	125	0	0
T31	0	222	0	0
T54	0	84	0	0
T100	0	129	0	0
T144	0	47	0	0
T173	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	62	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T54	0	1	0	0
T100	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6553453	0	0
T1	14749	6774	0	0
T2	6923	1185	0	0
T3	537	3	0	0
T4	7647	1186	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6555752	0	0
T1	14749	6798	0	0
T2	6923	1199	0	0
T3	537	3	0	0
T4	7647	1198	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	70	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	4	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T100	0	1	0	0
T173	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	65	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T54	0	1	0	0
T100	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	62	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T54	0	1	0	0
T100	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	62	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T7	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T54	0	1	0	0
T100	0	1	0	0
T144	0	1	0	0
T173	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	4944	0	0
T2	6923	39	0	0
T3	537	13	0	0
T4	7647	95	0	0
T5	9978	0	0	0
T7	0	157	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	121	0	0
T31	0	221	0	0
T54	0	82	0	0
T100	0	127	0	0
T144	0	46	0	0
T173	0	170	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	39	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T77	0	1	0	0
T125	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T11
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T30
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T30,T129
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T4,T30,T129

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T48,T69,T145
DetectSt->IdleSt	186	Covered	T30
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T4,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T145
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T30
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T30,T129
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	91	0	0
CntIncr_A	7237349	2436	0	0
CntNoWrap_A	7237349	6570414	0	0
DetectStDropOut_A	7237349	1	0	0
DetectedOut_A	7237349	2834	0	0
DetectedPulseOut_A	7237349	43	0	0
DisabledIdleSt_A	7237349	6290171	0	0
DisabledNoDetection_A	7237349	6292472	0	0
EnterDebounceSt_A	7237349	47	0	0
EnterDetectSt_A	7237349	44	0	0
EnterStableSt_A	7237349	43	0	0
PulseIsPulse_A	7237349	43	0	0
StayInStableSt	7237349	2762	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7237349	6705	0	0
gen_low_level_sva.LowLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	91	0	0
T2	6923	2	0	0
T3	537	2	0	0
T4	7647	6	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	4	0	0
T48	0	1	0	0
T66	0	2	0	0
T76	0	2	0	0
T129	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2436	0	0
T2	6923	13	0	0
T3	537	34	0	0
T4	7647	231	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	60	0	0
T48	0	38	0	0
T66	0	92	0	0
T76	0	70	0	0
T129	0	23	0	0
T143	0	37	0	0
T144	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6570414	0	0
T1	14749	6774	0	0
T2	6923	1294	0	0
T3	537	134	0	0
T4	7647	2040	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1	0	0
T27	30653	0	0	0
T30	756	1	0	0
T36	24543	0	0	0
T37	647	0	0	0
T68	18399	0	0	0
T106	480	0	0	0
T139	672	0	0	0
T140	502	0	0	0
T141	645	0	0	0
T212	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2834	0	0
T2	6923	13	0	0
T3	537	44	0	0
T4	7647	116	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	8	0	0
T66	0	274	0	0
T76	0	41	0	0
T77	0	40	0	0
T129	0	5	0	0
T143	0	45	0	0
T144	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6290171	0	0
T1	14749	6774	0	0
T2	6923	1185	0	0
T3	537	3	0	0
T4	7647	1186	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6292472	0	0
T1	14749	6798	0	0
T2	6923	1199	0	0
T3	537	3	0	0
T4	7647	1198	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	47	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	2	0	0
T48	0	1	0	0
T66	0	1	0	0
T76	0	1	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	44	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	2	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	43	0	0
T2	6923	1	0	0
T3	537	1	0	0
T4	7647	3	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	1	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T129	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2762	0	0
T2	6923	11	0	0
T3	537	42	0	0
T4	7647	112	0	0
T5	9978	0	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T30	0	7	0	0
T66	0	272	0	0
T76	0	39	0	0
T77	0	38	0	0
T129	0	4	0	0
T143	0	43	0	0
T144	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6705	0	0
T1	14749	46	0	0
T2	6923	30	0	0
T3	537	1	0	0
T4	7647	34	0	0
T5	0	11	0	0
T11	523	4	0	0
T12	493	8	0	0
T13	449	0	0	0
T14	502	4	0	0
T15	428	4	0	0
T16	600	0	0	0
T21	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	14	0	0
T4	7647	2	0	0
T5	9978	0	0	0
T16	600	0	0	0
T21	751	0	0	0
T30	0	1	0	0
T33	753	0	0	0
T34	744	0	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T107	427	0	0	0
T126	0	1	0	0
T129	0	1	0	0
T136	0	1	0	0
T142	0	1	0	0
T153	0	2	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	2	0	0