Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T22,T23
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T48,T62,T63
1	0	Covered	T48,T62,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T22,T23
1	-	Covered	T8,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T8,T22,T23
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T8,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T22,T23
DebounceSt->IdleSt	163	Covered	T48,T176,T216
DetectSt->IdleSt	186	Covered	T48,T62,T63
DetectSt->StableSt	191	Covered	T8,T22,T23
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T8,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T22,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T8,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T176,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T48,T62,T63
DetectSt	-	-	-	-	0	1	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	0	0	-	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T8,T22,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	3036	0	0
CntIncr_A	7237349	105616	0	0
CntNoWrap_A	7237349	6567469	0	0
DetectStDropOut_A	7237349	410	0	0
DetectedOut_A	7237349	80282	0	0
DetectedPulseOut_A	7237349	896	0	0
DisabledIdleSt_A	7237349	6113262	0	0
DisabledNoDetection_A	7237349	6115420	0	0
EnterDebounceSt_A	7237349	1545	0	0
EnterDetectSt_A	7237349	1493	0	0
EnterStableSt_A	7237349	896	0	0
PulseIsPulse_A	7237349	896	0	0
StayInStableSt	7237349	79279	0	0
gen_high_event_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3036	0	0
T8	34782	30	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	6	0	0
T23	0	28	0	0
T32	0	36	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	16	0	0
T60	0	12	0	0
T61	0	48	0	0
T62	0	18	0	0
T63	0	58	0	0
T64	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	105616	0	0
T8	34782	870	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	114	0	0
T23	0	1232	0	0
T32	0	1296	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	610	0	0
T60	0	324	0	0
T61	0	1248	0	0
T62	0	794	0	0
T63	0	1710	0	0
T64	0	1394	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6567469	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	410	0	0
T48	8021	1	0	0
T49	71524	0	0	0
T61	30237	0	0	0
T62	12592	3	0	0
T63	0	29	0	0
T64	0	29	0	0
T82	0	11	0	0
T83	0	3	0	0
T84	0	13	0	0
T89	0	27	0	0
T146	0	13	0	0
T217	0	27	0	0
T218	422	0	0	0
T219	26364	0	0	0
T220	424	0	0	0
T221	402	0	0	0
T222	406	0	0	0
T223	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	80282	0	0
T8	34782	1585	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	938	0	0
T23	0	2304	0	0
T32	0	2301	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	419	0	0
T60	0	170	0	0
T61	0	3201	0	0
T73	0	2962	0	0
T176	0	162	0	0
T180	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	896	0	0
T8	34782	15	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	6	0	0
T61	0	24	0	0
T73	0	14	0	0
T176	0	8	0	0
T180	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6113262	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6115420	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1545	0	0
T8	34782	15	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	9	0	0
T60	0	6	0	0
T61	0	24	0	0
T62	0	9	0	0
T63	0	29	0	0
T64	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1493	0	0
T8	34782	15	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	7	0	0
T60	0	6	0	0
T61	0	24	0	0
T62	0	9	0	0
T63	0	29	0	0
T64	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	896	0	0
T8	34782	15	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	6	0	0
T61	0	24	0	0
T73	0	14	0	0
T176	0	8	0	0
T180	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	896	0	0
T8	34782	15	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	6	0	0
T61	0	24	0	0
T73	0	14	0	0
T176	0	8	0	0
T180	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	79279	0	0
T8	34782	1562	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	935	0	0
T23	0	2284	0	0
T32	0	2281	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	414	0	0
T60	0	164	0	0
T61	0	3170	0	0
T73	0	2947	0	0
T176	0	154	0	0
T180	0	126	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	788	0	0
T8	34782	7	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	3	0	0
T23	0	8	0	0
T32	0	16	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	6	0	0
T61	0	17	0	0
T73	0	13	0	0
T176	0	8	0	0
T180	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T13,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T13,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T58,T81,T85
1	0	Covered	T48,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T7
1	-	Covered	T1,T5,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T5
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T1,T13,T8
DetectSt->IdleSt	186	Covered	T58,T48,T81
DetectSt->StableSt	191	Covered	T1,T5,T7
IdleSt->DebounceSt	148	Covered	T1,T13,T5
StableSt->IdleSt	206	Covered	T1,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T13,T5
0	1	Covered	T1,T13,T5
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T13,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T5
DetectSt	-	-	-	-	1	-	-	Covered	T58,T48,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	980	0	0
CntIncr_A	7237349	48481	0	0
CntNoWrap_A	7237349	6569525	0	0
DetectStDropOut_A	7237349	55	0	0
DetectedOut_A	7237349	16283	0	0
DetectedPulseOut_A	7237349	397	0	0
DisabledIdleSt_A	7237349	6169822	0	0
DisabledNoDetection_A	7237349	6171401	0	0
EnterDebounceSt_A	7237349	529	0	0
EnterDetectSt_A	7237349	457	0	0
EnterStableSt_A	7237349	397	0	0
PulseIsPulse_A	7237349	397	0	0
StayInStableSt	7237349	15853	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	362	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	980	0	0
T1	14749	3	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	6	0	0
T7	0	8	0	0
T8	0	15	0	0
T9	0	1	0	0
T10	0	3	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	1	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	22	0	0
T29	0	27	0	0
T36	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	48481	0	0
T1	14749	243	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	306	0	0
T7	0	332	0	0
T8	0	365	0	0
T9	0	20	0	0
T10	0	179	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	20	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	1678	0	0
T29	0	1458	0	0
T36	0	1638	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6569525	0	0
T1	14749	6771	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	47	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	55	0	0
T23	23367	0	0	0
T46	1558	0	0	0
T47	760	0	0	0
T58	16014	2	0	0
T59	486	0	0	0
T81	0	2	0	0
T85	0	12	0	0
T86	0	5	0	0
T87	0	2	0	0
T88	0	5	0	0
T90	0	3	0	0
T91	0	9	0	0
T93	0	2	0	0
T94	0	1	0	0
T96	402	0	0	0
T97	402	0	0	0
T98	751	0	0	0
T99	775	0	0	0
T100	3429	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	16283	0	0
T1	14749	36	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	39	0	0
T7	0	237	0	0
T8	0	271	0	0
T10	0	72	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	138	0	0
T29	0	1008	0	0
T36	0	349	0	0
T68	0	22	0	0
T106	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	397	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	7	0	0
T10	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	10	0	0
T29	0	13	0	0
T36	0	13	0	0
T68	0	3	0	0
T106	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6169822	0	0
T1	14749	5722	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2013	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	3	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6171401	0	0
T1	14749	5743	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2026	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	3	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	529	0	0
T1	14749	3	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	8	0	0
T9	0	1	0	0
T10	0	2	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	1	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	12	0	0
T29	0	14	0	0
T36	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	457	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	7	0	0
T10	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	10	0	0
T29	0	13	0	0
T36	0	13	0	0
T68	0	3	0	0
T106	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	397	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	7	0	0
T10	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	10	0	0
T29	0	13	0	0
T36	0	13	0	0
T68	0	3	0	0
T106	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	397	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	7	0	0
T10	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	10	0	0
T29	0	13	0	0
T36	0	13	0	0
T68	0	3	0	0
T106	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	15853	0	0
T1	14749	35	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	36	0	0
T7	0	233	0	0
T8	0	264	0	0
T10	0	71	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	128	0	0
T29	0	995	0	0
T36	0	336	0	0
T68	0	19	0	0
T106	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	362	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	3	0	0
T7	0	4	0	0
T8	0	7	0	0
T10	0	1	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	10	0	0
T29	0	13	0	0
T36	0	13	0	0
T68	0	3	0	0
T106	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T22,T23
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T48,T63,T64
1	0	Covered	T22,T48,T224

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T23,T32
0	1	Covered	T8,T23,T32
1	0	Covered	T225

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T23,T32
1	-	Covered	T8,T23,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T8,T22,T23
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T8,T23,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T22,T23
DebounceSt->IdleSt	163	Covered	T48,T176,T216
DetectSt->IdleSt	186	Covered	T22,T48,T63
DetectSt->StableSt	191	Covered	T8,T23,T32
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T8,T23,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T22,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T8,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T176,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T22,T48,T63
DetectSt	-	-	-	-	0	1	-	Covered	T8,T23,T32
DetectSt	-	-	-	-	0	0	-	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T8,T23,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T23,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	2865	0	0
CntIncr_A	7237349	110463	0	0
CntNoWrap_A	7237349	6567640	0	0
DetectStDropOut_A	7237349	310	0	0
DetectedOut_A	7237349	79237	0	0
DetectedPulseOut_A	7237349	905	0	0
DisabledIdleSt_A	7237349	6112699	0	0
DisabledNoDetection_A	7237349	6114856	0	0
EnterDebounceSt_A	7237349	1465	0	0
EnterDetectSt_A	7237349	1402	0	0
EnterStableSt_A	7237349	905	0	0
PulseIsPulse_A	7237349	905	0	0
StayInStableSt	7237349	78224	0	0
gen_high_event_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	785	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	2865	0	0
T8	34782	16	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	22	0	0
T23	0	6	0	0
T32	0	14	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	16	0	0
T60	0	56	0	0
T61	0	32	0	0
T62	0	42	0	0
T63	0	14	0	0
T64	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	110463	0	0
T8	34782	440	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	761	0	0
T23	0	219	0	0
T32	0	462	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	637	0	0
T60	0	1876	0	0
T61	0	1024	0	0
T62	0	1302	0	0
T63	0	407	0	0
T64	0	1154	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6567640	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	310	0	0
T48	8021	1	0	0
T49	71524	0	0	0
T61	30237	0	0	0
T62	12592	0	0	0
T63	0	7	0	0
T64	0	24	0	0
T89	0	25	0	0
T146	0	3	0	0
T217	0	16	0	0
T218	422	0	0	0
T219	26364	0	0	0
T220	424	0	0	0
T221	402	0	0	0
T222	406	0	0	0
T223	526	0	0	0
T226	0	10	0	0
T227	0	4	0	0
T228	0	12	0	0
T229	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	79237	0	0
T8	34782	727	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	314	0	0
T32	0	776	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	412	0	0
T60	0	921	0	0
T61	0	1981	0	0
T62	0	1887	0	0
T73	0	7295	0	0
T176	0	74	0	0
T180	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	905	0	0
T8	34782	8	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	3	0	0
T32	0	7	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	16	0	0
T62	0	21	0	0
T73	0	30	0	0
T176	0	3	0	0
T180	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6112699	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6114856	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1465	0	0
T8	34782	8	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	3	0	0
T32	0	7	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	9	0	0
T60	0	28	0	0
T61	0	16	0	0
T62	0	21	0	0
T63	0	7	0	0
T64	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1402	0	0
T8	34782	8	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	3	0	0
T32	0	7	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	7	0	0
T60	0	28	0	0
T61	0	16	0	0
T62	0	21	0	0
T63	0	7	0	0
T64	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	905	0	0
T8	34782	8	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	3	0	0
T32	0	7	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	16	0	0
T62	0	21	0	0
T73	0	30	0	0
T176	0	3	0	0
T180	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	905	0	0
T8	34782	8	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	3	0	0
T32	0	7	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	16	0	0
T62	0	21	0	0
T73	0	30	0	0
T176	0	3	0	0
T180	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	78224	0	0
T8	34782	715	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	310	0	0
T32	0	768	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	407	0	0
T60	0	891	0	0
T61	0	1959	0	0
T62	0	1864	0	0
T73	0	7264	0	0
T176	0	71	0	0
T180	0	79	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	785	0	0
T8	34782	4	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	2	0	0
T32	0	6	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	26	0	0
T61	0	10	0	0
T62	0	19	0	0
T73	0	29	0	0
T176	0	3	0	0
T180	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T68,T175,T230
1	0	Covered	T48,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T69,T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T8
1	-	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T5,T7,T8
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T8
DebounceSt->IdleSt	163	Covered	T1,T10,T29
DetectSt->IdleSt	186	Covered	T68,T48,T175
DetectSt->StableSt	191	Covered	T5,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T5,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T8
0	1	Covered	T1,T5,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T29,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T68,T48,T175
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	962	0	0
CntIncr_A	7237349	52788	0	0
CntNoWrap_A	7237349	6569543	0	0
DetectStDropOut_A	7237349	103	0	0
DetectedOut_A	7237349	15177	0	0
DetectedPulseOut_A	7237349	350	0	0
DisabledIdleSt_A	7237349	6182027	0	0
DisabledNoDetection_A	7237349	6183678	0	0
EnterDebounceSt_A	7237349	507	0	0
EnterDetectSt_A	7237349	457	0	0
EnterStableSt_A	7237349	350	0	0
PulseIsPulse_A	7237349	350	0	0
StayInStableSt	7237349	14789	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	962	0	0
T5	9978	12	0	0
T6	11605	0	0	0
T7	28203	4	0	0
T8	0	8	0	0
T10	0	5	0	0
T21	751	0	0	0
T27	0	4	0	0
T28	0	5	0	0
T29	0	11	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	6	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	11	0	0
T107	427	0	0	0
T231	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	52788	0	0
T1	14749	66	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	660	0	0
T7	0	178	0	0
T8	0	184	0	0
T10	0	414	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	288	0	0
T28	0	285	0	0
T29	0	560	0	0
T36	0	282	0	0
T68	0	534	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6569543	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	103	0	0
T28	20909	0	0	0
T38	683	0	0	0
T54	1555	0	0	0
T55	2120	0	0	0
T68	18399	5	0	0
T80	44662	0	0	0
T121	0	8	0	0
T175	0	1	0	0
T186	0	3	0	0
T230	0	1	0	0
T231	39704	0	0	0
T232	0	2	0	0
T233	0	11	0	0
T234	0	5	0	0
T235	0	11	0	0
T236	0	16	0	0
T237	567	0	0	0
T238	491	0	0	0
T239	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	15177	0	0
T5	9978	28	0	0
T6	11605	0	0	0
T7	28203	168	0	0
T8	0	172	0	0
T10	0	9	0	0
T21	751	0	0	0
T23	0	82	0	0
T27	0	39	0	0
T28	0	116	0	0
T29	0	436	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	175	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	59	0	0
T107	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	350	0	0
T5	9978	6	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	4	0	0
T10	0	2	0	0
T21	751	0	0	0
T23	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	3	0	0
T107	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6182027	0	0
T1	14749	5750	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6183678	0	0
T1	14749	5772	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	507	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	6	0	0
T7	0	2	0	0
T8	0	4	0	0
T10	0	3	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T29	0	6	0	0
T36	0	3	0	0
T68	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	457	0	0
T5	9978	6	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	4	0	0
T10	0	2	0	0
T21	751	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	3	0	0
T68	0	5	0	0
T107	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	350	0	0
T5	9978	6	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	4	0	0
T10	0	2	0	0
T21	751	0	0	0
T23	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	3	0	0
T107	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	350	0	0
T5	9978	6	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	4	0	0
T10	0	2	0	0
T21	751	0	0	0
T23	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	3	0	0
T107	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	14789	0	0
T5	9978	22	0	0
T6	11605	0	0	0
T7	28203	166	0	0
T8	0	167	0	0
T10	0	7	0	0
T21	751	0	0	0
T23	0	81	0	0
T27	0	37	0	0
T28	0	114	0	0
T29	0	431	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	172	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	56	0	0
T107	427	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	307	0	0
T5	9978	6	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	3	0	0
T10	0	2	0	0
T21	751	0	0	0
T23	0	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	5	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T58	0	3	0	0
T107	427	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T22,T23
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T48,T63,T64
1	0	Covered	T22,T48,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T23,T32
0	1	Covered	T8,T23,T32
1	0	Covered	T48,T73

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T23,T32
1	-	Covered	T8,T23,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T8,T22,T23
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T8,T23,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T22,T23
DebounceSt->IdleSt	163	Covered	T48,T176,T216
DetectSt->IdleSt	186	Covered	T22,T48,T63
DetectSt->StableSt	191	Covered	T8,T23,T32
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T8,T23,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T22,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T8,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T176,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T22,T48,T63
DetectSt	-	-	-	-	0	1	-	Covered	T8,T23,T32
DetectSt	-	-	-	-	0	0	-	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T8,T23,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T23,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	3090	0	0
CntIncr_A	7237349	116276	0	0
CntNoWrap_A	7237349	6567415	0	0
DetectStDropOut_A	7237349	346	0	0
DetectedOut_A	7237349	76439	0	0
DetectedPulseOut_A	7237349	966	0	0
DisabledIdleSt_A	7237349	6113750	0	0
DisabledNoDetection_A	7237349	6115911	0	0
EnterDebounceSt_A	7237349	1577	0	0
EnterDetectSt_A	7237349	1515	0	0
EnterStableSt_A	7237349	966	0	0
PulseIsPulse_A	7237349	966	0	0
StayInStableSt	7237349	75368	0	0
gen_high_event_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	840	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3090	0	0
T8	34782	10	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	22	0	0
T23	0	28	0	0
T32	0	36	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	17	0	0
T60	0	56	0	0
T61	0	58	0	0
T62	0	18	0	0
T63	0	58	0	0
T64	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	116276	0	0
T8	34782	300	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	761	0	0
T23	0	1232	0	0
T32	0	1278	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	548	0	0
T60	0	1176	0	0
T61	0	2146	0	0
T62	0	495	0	0
T63	0	1710	0	0
T64	0	331	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6567415	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	346	0	0
T48	8021	1	0	0
T49	71524	0	0	0
T61	30237	0	0	0
T62	12592	0	0	0
T63	0	29	0	0
T64	0	7	0	0
T82	0	9	0	0
T84	0	11	0	0
T89	0	15	0	0
T146	0	12	0	0
T151	0	8	0	0
T217	0	6	0	0
T218	422	0	0	0
T219	26364	0	0	0
T220	424	0	0	0
T221	402	0	0	0
T222	406	0	0	0
T223	526	0	0	0
T240	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	76439	0	0
T8	34782	271	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	2304	0	0
T32	0	2319	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	404	0	0
T60	0	1621	0	0
T61	0	2626	0	0
T62	0	910	0	0
T73	0	3214	0	0
T176	0	107	0	0
T180	0	206	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	966	0	0
T8	34782	5	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	29	0	0
T62	0	9	0	0
T73	0	23	0	0
T176	0	2	0	0
T180	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6113750	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6115911	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1577	0	0
T8	34782	5	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	10	0	0
T60	0	28	0	0
T61	0	29	0	0
T62	0	9	0	0
T63	0	29	0	0
T64	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1515	0	0
T8	34782	5	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	7	0	0
T60	0	28	0	0
T61	0	29	0	0
T62	0	9	0	0
T63	0	29	0	0
T64	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	966	0	0
T8	34782	5	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	29	0	0
T62	0	9	0	0
T73	0	23	0	0
T176	0	2	0	0
T180	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	966	0	0
T8	34782	5	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	14	0	0
T32	0	18	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	29	0	0
T62	0	9	0	0
T73	0	23	0	0
T176	0	2	0	0
T180	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	75368	0	0
T8	34782	264	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	2284	0	0
T32	0	2299	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	399	0	0
T60	0	1591	0	0
T61	0	2588	0	0
T62	0	899	0	0
T73	0	3191	0	0
T176	0	105	0	0
T180	0	201	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	840	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	0	0	0
T23	0	8	0	0
T32	0	16	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	4	0	0
T60	0	26	0	0
T61	0	20	0	0
T62	0	7	0	0
T73	0	5	0	0
T176	0	2	0	0
T180	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T10,T231,T58
1	0	Covered	T48,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T8
1	-	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T5,T7,T8
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T5,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T8
DebounceSt->IdleSt	163	Covered	T1,T10,T36
DetectSt->IdleSt	186	Covered	T10,T231,T58
DetectSt->StableSt	191	Covered	T5,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T5,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T8
0	1	Covered	T1,T5,T7
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T36,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T10,T231,T58
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	865	0	0
CntIncr_A	7237349	47901	0	0
CntNoWrap_A	7237349	6569640	0	0
DetectStDropOut_A	7237349	81	0	0
DetectedOut_A	7237349	14992	0	0
DetectedPulseOut_A	7237349	329	0	0
DisabledIdleSt_A	7237349	6191716	0	0
DisabledNoDetection_A	7237349	6193374	0	0
EnterDebounceSt_A	7237349	454	0	0
EnterDetectSt_A	7237349	413	0	0
EnterStableSt_A	7237349	329	0	0
PulseIsPulse_A	7237349	329	0	0
StayInStableSt	7237349	14630	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	865	0	0
T5	9978	4	0	0
T6	11605	0	0	0
T7	28203	2	0	0
T8	0	4	0	0
T10	0	12	0	0
T21	751	0	0	0
T27	0	17	0	0
T28	0	12	0	0
T29	0	6	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	3	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	6	0	0
T107	427	0	0	0
T231	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	47901	0	0
T1	14749	65	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	144	0	0
T7	0	74	0	0
T8	0	98	0	0
T10	0	1019	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	1345	0	0
T28	0	925	0	0
T29	0	525	0	0
T36	0	218	0	0
T68	0	255	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6569640	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	81	0	0
T10	10993	5	0	0
T22	16533	0	0	0
T29	33478	0	0	0
T31	7354	0	0	0
T35	3125	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	1	0	0
T52	491	0	0	0
T58	0	4	0	0
T66	0	6	0	0
T86	0	9	0	0
T93	0	2	0	0
T137	422	0	0	0
T231	0	4	0	0
T241	0	4	0	0
T242	0	5	0	0
T243	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	14992	0	0
T5	9978	84	0	0
T6	11605	0	0	0
T7	28203	58	0	0
T8	0	82	0	0
T21	751	0	0	0
T23	0	540	0	0
T27	0	55	0	0
T28	0	34	0	0
T29	0	24	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	7	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	29	0	0
T107	427	0	0	0
T244	0	360	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	329	0	0
T5	9978	2	0	0
T6	11605	0	0	0
T7	28203	1	0	0
T8	0	2	0	0
T21	751	0	0	0
T23	0	6	0	0
T27	0	8	0	0
T28	0	5	0	0
T29	0	3	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	1	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	3	0	0
T107	427	0	0	0
T244	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6191716	0	0
T1	14749	6706	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6193374	0	0
T1	14749	6729	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	454	0	0
T1	14749	1	0	0
T2	6923	0	0	0
T3	537	0	0	0
T4	7647	0	0	0
T5	0	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	7	0	0
T11	523	0	0	0
T12	493	0	0	0
T13	449	0	0	0
T14	502	0	0	0
T15	428	0	0	0
T16	600	0	0	0
T27	0	9	0	0
T28	0	7	0	0
T29	0	3	0	0
T36	0	2	0	0
T68	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	413	0	0
T5	9978	2	0	0
T6	11605	0	0	0
T7	28203	1	0	0
T8	0	2	0	0
T10	0	5	0	0
T21	751	0	0	0
T27	0	8	0	0
T28	0	5	0	0
T29	0	3	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	1	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	3	0	0
T107	427	0	0	0
T231	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	329	0	0
T5	9978	2	0	0
T6	11605	0	0	0
T7	28203	1	0	0
T8	0	2	0	0
T21	751	0	0	0
T23	0	6	0	0
T27	0	8	0	0
T28	0	5	0	0
T29	0	3	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	1	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	3	0	0
T107	427	0	0	0
T244	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	329	0	0
T5	9978	2	0	0
T6	11605	0	0	0
T7	28203	1	0	0
T8	0	2	0	0
T21	751	0	0	0
T23	0	6	0	0
T27	0	8	0	0
T28	0	5	0	0
T29	0	3	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	1	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	3	0	0
T107	427	0	0	0
T244	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	14630	0	0
T5	9978	82	0	0
T6	11605	0	0	0
T7	28203	57	0	0
T8	0	80	0	0
T21	751	0	0	0
T23	0	529	0	0
T27	0	47	0	0
T28	0	29	0	0
T29	0	21	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	6	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	26	0	0
T107	427	0	0	0
T244	0	355	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	294	0	0
T5	9978	2	0	0
T6	11605	0	0	0
T7	28203	1	0	0
T8	0	2	0	0
T21	751	0	0	0
T23	0	1	0	0
T27	0	8	0	0
T28	0	5	0	0
T29	0	3	0	0
T33	753	0	0	0
T34	744	0	0	0
T36	0	1	0	0
T45	631	0	0	0
T56	426	0	0	0
T57	504	0	0	0
T68	0	3	0	0
T107	427	0	0	0
T244	0	5	0	0