Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T22,T23
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T22,T23
1	0	Covered	T8,T22,T23
1	1	Covered	T8,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T48,T63,T64
1	0	Covered	T48,T224,T226

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
1	0	Covered	T74,T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T22,T23
1	-	Covered	T8,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T22,T23
DetectSt	168	Covered	T8,T22,T23
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T8,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T22,T23
DebounceSt->IdleSt	163	Covered	T48,T176,T216
DetectSt->IdleSt	186	Covered	T48,T63,T64
DetectSt->StableSt	191	Covered	T8,T22,T23
IdleSt->DebounceSt	148	Covered	T8,T22,T23
StableSt->IdleSt	206	Covered	T8,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T22,T23
0	1	Covered	T8,T22,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T22,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T8,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T176,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T48,T63,T64
DetectSt	-	-	-	-	0	1	-	Covered	T8,T22,T23
DetectSt	-	-	-	-	0	0	-	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T8,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T8,T22,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	3054	0	0
CntIncr_A	7237349	110710	0	0
CntNoWrap_A	7237349	6567451	0	0
DetectStDropOut_A	7237349	407	0	0
DetectedOut_A	7237349	74873	0	0
DetectedPulseOut_A	7237349	830	0	0
DisabledIdleSt_A	7237349	6120826	0	0
DisabledNoDetection_A	7237349	6123012	0	0
EnterDebounceSt_A	7237349	1559	0	0
EnterDetectSt_A	7237349	1496	0	0
EnterStableSt_A	7237349	830	0	0
PulseIsPulse_A	7237349	830	0	0
StayInStableSt	7237349	73963	0	0
gen_high_event_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	740	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	3054	0	0
T8	34782	18	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	22	0	0
T23	0	16	0	0
T32	0	20	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	16	0	0
T60	0	56	0	0
T61	0	38	0	0
T62	0	24	0	0
T63	0	54	0	0
T64	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	110710	0	0
T8	34782	396	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	660	0	0
T23	0	704	0	0
T32	0	770	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	665	0	0
T60	0	1792	0	0
T61	0	1368	0	0
T62	0	864	0	0
T63	0	1593	0	0
T64	0	765	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6567451	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	407	0	0
T48	8021	1	0	0
T49	71524	0	0	0
T61	30237	0	0	0
T62	12592	0	0	0
T63	0	27	0	0
T64	0	16	0	0
T74	0	8	0	0
T89	0	25	0	0
T146	0	22	0	0
T217	0	29	0	0
T218	422	0	0	0
T219	26364	0	0	0
T220	424	0	0	0
T221	402	0	0	0
T222	406	0	0	0
T223	526	0	0	0
T226	0	4	0	0
T228	0	12	0	0
T246	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	74873	0	0
T8	34782	950	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	2508	0	0
T23	0	1635	0	0
T32	0	870	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	405	0	0
T60	0	1743	0	0
T61	0	1505	0	0
T62	0	348	0	0
T73	0	4549	0	0
T176	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	830	0	0
T8	34782	9	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	8	0	0
T32	0	10	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	19	0	0
T62	0	12	0	0
T73	0	26	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6120826	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6123012	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1559	0	0
T8	34782	9	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	8	0	0
T32	0	10	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	9	0	0
T60	0	28	0	0
T61	0	19	0	0
T62	0	12	0	0
T63	0	27	0	0
T64	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	1496	0	0
T8	34782	9	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	8	0	0
T32	0	10	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	7	0	0
T60	0	28	0	0
T61	0	19	0	0
T62	0	12	0	0
T63	0	27	0	0
T64	0	16	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	830	0	0
T8	34782	9	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	8	0	0
T32	0	10	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	19	0	0
T62	0	12	0	0
T73	0	26	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	830	0	0
T8	34782	9	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	11	0	0
T23	0	8	0	0
T32	0	10	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	28	0	0
T61	0	19	0	0
T62	0	12	0	0
T73	0	26	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	73963	0	0
T8	34782	936	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	2493	0	0
T23	0	1624	0	0
T32	0	858	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	400	0	0
T60	0	1714	0	0
T61	0	1481	0	0
T62	0	336	0	0
T73	0	4522	0	0
T176	0	35	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	740	0	0
T8	34782	4	0	0
T9	11866	0	0	0
T10	10993	0	0	0
T22	16533	7	0	0
T23	0	5	0	0
T32	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T43	523	0	0	0
T44	510	0	0	0
T48	0	5	0	0
T60	0	27	0	0
T61	0	14	0	0
T62	0	12	0	0
T73	0	25	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T6,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T244,T219,T230
1	0	Covered	T48,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T8
1	-	Covered	T6,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T8
DetectSt	168	Covered	T6,T7,T8
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T8
DebounceSt->IdleSt	163	Covered	T27,T28,T231
DetectSt->IdleSt	186	Covered	T244,T48,T219
DetectSt->StableSt	191	Covered	T6,T7,T8
IdleSt->DebounceSt	148	Covered	T6,T7,T8
StableSt->IdleSt	206	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T48,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T28,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T244,T48,T219
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7237349	853	0	0
CntIncr_A	7237349	49030	0	0
CntNoWrap_A	7237349	6569652	0	0
DetectStDropOut_A	7237349	110	0	0
DetectedOut_A	7237349	12459	0	0
DetectedPulseOut_A	7237349	290	0	0
DisabledIdleSt_A	7237349	6183869	0	0
DisabledNoDetection_A	7237349	6185540	0	0
EnterDebounceSt_A	7237349	450	0	0
EnterDetectSt_A	7237349	405	0	0
EnterStableSt_A	7237349	290	0	0
PulseIsPulse_A	7237349	290	0	0
StayInStableSt	7237349	12151	0	0
gen_high_level_sva.HighLevelEvent_A	7237349	6572858	0	0
gen_not_sticky_sva.StableStDropOut_A	7237349	268	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	853	0	0
T6	11605	2	0	0
T7	28203	6	0	0
T8	34782	6	0	0
T9	11866	0	0	0
T10	10993	2	0	0
T22	0	8	0	0
T27	0	13	0	0
T28	0	8	0	0
T29	0	6	0	0
T36	0	16	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	49030	0	0
T6	11605	115	0	0
T7	28203	444	0	0
T8	34782	102	0	0
T9	11866	0	0	0
T10	10993	158	0	0
T22	0	448	0	0
T27	0	785	0	0
T28	0	572	0	0
T29	0	450	0	0
T36	0	920	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6569652	0	0
T1	14749	6774	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	110	0	0
T32	16539	0	0	0
T48	8021	0	0	0
T60	12267	0	0	0
T85	0	1	0	0
T86	0	4	0	0
T88	0	2	0	0
T204	0	4	0	0
T219	0	2	0	0
T230	0	5	0	0
T241	0	11	0	0
T244	25874	4	0	0
T247	0	5	0	0
T248	0	1	0	0
T249	505	0	0	0
T250	1045	0	0	0
T251	408	0	0	0
T252	8401	0	0	0
T253	148988	0	0	0
T254	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	12459	0	0
T6	11605	83	0	0
T7	28203	107	0	0
T8	34782	164	0	0
T9	11866	0	0	0
T10	10993	13	0	0
T22	0	213	0	0
T27	0	285	0	0
T28	0	72	0	0
T29	0	99	0	0
T36	0	298	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	290	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	6	0	0
T28	0	3	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6183869	0	0
T1	14749	5750	0	0
T2	6923	1296	0	0
T3	537	136	0	0
T4	7647	2046	0	0
T11	523	122	0	0
T12	493	92	0	0
T13	449	48	0	0
T14	502	101	0	0
T15	428	27	0	0
T16	600	199	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6185540	0	0
T1	14749	5772	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	450	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	7	0	0
T28	0	5	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	405	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	6	0	0
T28	0	3	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	290	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	6	0	0
T28	0	3	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	290	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	6	0	0
T28	0	3	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	12151	0	0
T6	11605	82	0	0
T7	28203	104	0	0
T8	34782	161	0	0
T9	11866	0	0	0
T10	10993	12	0	0
T22	0	209	0	0
T27	0	279	0	0
T28	0	69	0	0
T29	0	96	0	0
T36	0	290	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	6572858	0	0
T1	14749	6798	0	0
T2	6923	1311	0	0
T3	537	137	0	0
T4	7647	2060	0	0
T11	523	123	0	0
T12	493	93	0	0
T13	449	49	0	0
T14	502	102	0	0
T15	428	28	0	0
T16	600	200	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7237349	268	0	0
T6	11605	1	0	0
T7	28203	3	0	0
T8	34782	3	0	0
T9	11866	0	0	0
T10	10993	1	0	0
T22	0	4	0	0
T27	0	6	0	0
T28	0	3	0	0
T29	0	3	0	0
T36	0	8	0	0
T39	452	0	0	0
T40	404	0	0	0
T41	501	0	0	0
T42	404	0	0	0
T51	495	0	0	0
T68	0	1	0	0