Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1201996941	11303	0	0
auto_block_debounce_ctl_rd_A	1201996941	1890	0	0
auto_block_out_ctl_rd_A	1201996941	2737	0	0
com_det_ctl_0_rd_A	1201996941	3713	0	0
com_det_ctl_1_rd_A	1201996941	3711	0	0
com_det_ctl_2_rd_A	1201996941	3443	0	0
com_det_ctl_3_rd_A	1201996941	3816	0	0
com_out_ctl_0_rd_A	1201996941	4146	0	0
com_out_ctl_1_rd_A	1201996941	4004	0	0
com_out_ctl_2_rd_A	1201996941	4225	0	0
com_out_ctl_3_rd_A	1201996941	4129	0	0
com_pre_det_ctl_0_rd_A	1201996941	1320	0	0
com_pre_det_ctl_1_rd_A	1201996941	1417	0	0
com_pre_det_ctl_2_rd_A	1201996941	1540	0	0
com_pre_det_ctl_3_rd_A	1201996941	1461	0	0
com_pre_sel_ctl_0_rd_A	1201996941	4256	0	0
com_pre_sel_ctl_1_rd_A	1201996941	4394	0	0
com_pre_sel_ctl_2_rd_A	1201996941	4636	0	0
com_pre_sel_ctl_3_rd_A	1201996941	4398	0	0
com_sel_ctl_0_rd_A	1201996941	4359	0	0
com_sel_ctl_1_rd_A	1201996941	4252	0	0
com_sel_ctl_2_rd_A	1201996941	4221	0	0
com_sel_ctl_3_rd_A	1201996941	4386	0	0
ec_rst_ctl_rd_A	1201996941	2491	0	0
intr_enable_rd_A	1201996941	1858	0	0
key_intr_ctl_rd_A	1201996941	3696	0	0
key_intr_debounce_ctl_rd_A	1201996941	1418	0	0
key_invert_ctl_rd_A	1201996941	4778	0	0
pin_allowed_ctl_rd_A	1201996941	6204	0	0
pin_out_ctl_rd_A	1201996941	4039	0	0
pin_out_value_rd_A	1201996941	4797	0	0
regwen_rd_A	1201996941	1472	0	0
ulp_ac_debounce_ctl_rd_A	1201996941	1478	0	0
ulp_ctl_rd_A	1201996941	1523	0	0
ulp_lid_debounce_ctl_rd_A	1201996941	1488	0	0
ulp_pwrb_debounce_ctl_rd_A	1201996941	1538	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	11303	0	0
T1	348228	9	0	0
T2	315009	2	0	0
T3	55325	0	0	0
T4	233409	8	0	0
T6	0	10	0	0
T7	0	19	0	0
T9	0	9	0	0
T11	125700	0	0	0
T12	61797	0	0	0
T13	56230	0	0	0
T14	251529	0	0	0
T15	40757	0	0	0
T16	282144	0	0	0
T31	0	1	0	0
T58	0	7	0	0
T66	0	12	0	0
T67	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1890	0	0
T6	119307	0	0	0
T7	322001	0	0	0
T21	184054	3	0	0
T31	0	18	0	0
T33	41444	6	0	0
T34	96725	0	0	0
T35	0	14	0	0
T38	0	6	0	0
T45	315989	0	0	0
T51	61894	0	0	0
T56	48989	0	0	0
T57	123510	0	0	0
T67	0	34	0	0
T72	0	7	0	0
T78	0	34	0	0
T80	0	2	0	0
T107	19206	0	0	0
T275	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	2737	0	0
T6	119307	0	0	0
T7	322001	0	0	0
T21	184054	7	0	0
T31	0	4	0	0
T33	41444	9	0	0
T34	96725	0	0	0
T35	0	8	0	0
T38	0	4	0	0
T45	315989	0	0	0
T51	61894	0	0	0
T56	48989	0	0	0
T57	123510	0	0	0
T67	0	38	0	0
T72	0	10	0	0
T78	0	44	0	0
T80	0	8	0	0
T107	19206	0	0	0
T275	0	16	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	3713	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	23	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	37	0	0
T73	0	48	0	0
T78	0	85	0	0
T125	0	15	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	65	0	0
T230	0	32	0	0
T231	0	81	0	0
T244	0	24	0	0
T276	0	16	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	3711	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	3	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	38	0	0
T73	0	32	0	0
T78	0	72	0	0
T125	0	14	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	71	0	0
T230	0	43	0	0
T231	0	77	0	0
T244	0	29	0	0
T276	0	35	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	3443	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	3	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	32	0	0
T73	0	34	0	0
T78	0	83	0	0
T125	0	30	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	74	0	0
T230	0	56	0	0
T231	0	87	0	0
T244	0	27	0	0
T276	0	38	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	3816	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	12	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	33	0	0
T73	0	40	0	0
T78	0	90	0	0
T125	0	18	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	65	0	0
T230	0	59	0	0
T231	0	73	0	0
T244	0	52	0	0
T276	0	49	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4146	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	18	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	17	0	0
T73	0	38	0	0
T78	0	73	0	0
T125	0	2	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	84	0	0
T230	0	57	0	0
T231	0	73	0	0
T244	0	33	0	0
T276	0	69	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4004	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	8	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	34	0	0
T73	0	44	0	0
T78	0	91	0	0
T125	0	8	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	62	0	0
T230	0	37	0	0
T231	0	70	0	0
T244	0	31	0	0
T276	0	38	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4225	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	4	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	44	0	0
T73	0	36	0	0
T78	0	89	0	0
T125	0	19	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	87	0	0
T230	0	30	0	0
T231	0	58	0	0
T244	0	40	0	0
T276	0	48	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4129	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	11	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	21	0	0
T73	0	42	0	0
T78	0	67	0	0
T125	0	27	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	78	0	0
T230	0	60	0	0
T231	0	78	0	0
T244	0	51	0	0
T276	0	52	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1320	0	0
T24	0	35	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	9	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	12	0	0
T78	0	14	0	0
T95	0	3	0	0
T123	0	9	0	0
T125	0	17	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	9	0	0
T277	0	18	0	0
T278	0	24	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1417	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	18	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	37	0	0
T78	0	16	0	0
T95	0	8	0	0
T123	0	11	0	0
T125	0	18	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	5	0	0
T277	0	34	0	0
T278	0	25	0	0
T279	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1540	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	9	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	37	0	0
T78	0	20	0	0
T95	0	6	0	0
T123	0	8	0	0
T125	0	31	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	11	0	0
T277	0	19	0	0
T278	0	63	0	0
T279	0	5	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1461	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	21	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	30	0	0
T78	0	17	0	0
T95	0	5	0	0
T123	0	12	0	0
T125	0	31	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	13	0	0
T277	0	25	0	0
T278	0	43	0	0
T279	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4256	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	16	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	15	0	0
T73	0	31	0	0
T78	0	125	0	0
T125	0	35	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	68	0	0
T230	0	42	0	0
T231	0	59	0	0
T244	0	51	0	0
T276	0	46	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4394	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	4	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	18	0	0
T73	0	45	0	0
T78	0	98	0	0
T125	0	28	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	48	0	0
T230	0	58	0	0
T231	0	66	0	0
T244	0	40	0	0
T276	0	52	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4636	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	22	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	25	0	0
T73	0	54	0	0
T78	0	117	0	0
T125	0	39	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	74	0	0
T230	0	58	0	0
T231	0	83	0	0
T244	0	54	0	0
T276	0	17	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4398	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	8	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	33	0	0
T73	0	33	0	0
T78	0	73	0	0
T125	0	10	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	65	0	0
T230	0	43	0	0
T231	0	56	0	0
T244	0	61	0	0
T276	0	58	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4359	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	5	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	34	0	0
T73	0	50	0	0
T78	0	92	0	0
T125	0	37	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	67	0	0
T230	0	21	0	0
T231	0	58	0	0
T244	0	52	0	0
T276	0	24	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4252	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	14	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	19	0	0
T73	0	33	0	0
T78	0	98	0	0
T125	0	13	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	83	0	0
T230	0	62	0	0
T231	0	76	0	0
T244	0	16	0	0
T276	0	24	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4221	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	4	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	24	0	0
T73	0	39	0	0
T78	0	100	0	0
T125	0	13	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	69	0	0
T230	0	23	0	0
T231	0	66	0	0
T244	0	28	0	0
T276	0	43	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4386	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	13	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	33	0	0
T73	0	25	0	0
T78	0	103	0	0
T125	0	10	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T183	0	62	0	0
T230	0	22	0	0
T231	0	62	0	0
T244	0	28	0	0
T276	0	49	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	2491	0	0
T6	119307	0	0	0
T7	322001	0	0	0
T8	434779	0	0	0
T31	0	12	0	0
T33	41444	0	0	0
T34	96725	0	0	0
T45	315989	4	0	0
T51	61894	0	0	0
T55	0	3	0	0
T56	48989	0	0	0
T57	123510	0	0	0
T67	0	61	0	0
T73	0	8	0	0
T78	0	53	0	0
T107	19206	0	0	0
T183	0	23	0	0
T230	0	22	0	0
T231	0	55	0	0
T244	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1858	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	7	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	68	0	0
T78	0	87	0	0
T125	0	29	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T230	0	9	0	0
T241	0	70	0	0
T242	0	6	0	0
T277	0	42	0	0
T278	0	29	0	0
T279	0	19	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	3696	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	12	0	0
T35	781335	0	0	0
T50	0	3	0	0
T53	229820	0	0	0
T67	0	21	0	0
T78	0	17	0	0
T125	0	23	0	0
T134	0	4	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T195	0	3	0	0
T196	0	3	0	0
T241	0	4	0	0
T277	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1418	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	6	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	37	0	0
T78	0	10	0	0
T95	0	3	0	0
T123	0	9	0	0
T125	0	8	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	10	0	0
T277	0	13	0	0
T278	0	33	0	0
T279	0	11	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4778	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	5	0	0
T35	781335	0	0	0
T50	0	54	0	0
T53	229820	0	0	0
T55	0	67	0	0
T67	0	79	0	0
T78	0	70	0	0
T125	0	67	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T280	0	51	0	0
T281	0	45	0	0
T282	0	72	0	0
T283	0	37	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	6204	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	89	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	167	0	0
T78	0	372	0	0
T125	0	82	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T207	0	69	0	0
T213	0	62	0	0
T241	0	76	0	0
T242	0	41	0	0
T284	0	55	0	0
T285	0	43	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4039	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	112	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	138	0	0
T78	0	358	0	0
T125	0	67	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T207	0	75	0	0
T213	0	52	0	0
T241	0	69	0	0
T242	0	43	0	0
T284	0	67	0	0
T285	0	69	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	4797	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	78	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	182	0	0
T78	0	354	0	0
T125	0	56	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T207	0	72	0	0
T213	0	77	0	0
T241	0	80	0	0
T242	0	70	0	0
T284	0	81	0	0
T285	0	52	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1472	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	22	0	0
T35	781335	0	0	0
T53	229820	0	0	0
T67	0	27	0	0
T78	0	16	0	0
T95	0	1	0	0
T123	0	22	0	0
T125	0	27	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	7	0	0
T277	0	16	0	0
T278	0	47	0	0
T279	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1478	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	3	0	0
T35	781335	0	0	0
T50	0	2	0	0
T53	229820	0	0	0
T65	0	9	0	0
T67	0	32	0	0
T78	0	24	0	0
T105	0	14	0	0
T109	0	1	0	0
T111	0	16	0	0
T125	0	23	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1523	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	3	0	0
T35	781335	0	0	0
T50	0	2	0	0
T53	229820	0	0	0
T65	0	3	0	0
T67	0	24	0	0
T78	0	30	0	0
T105	0	21	0	0
T108	0	2	0	0
T109	0	2	0	0
T125	0	10	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1488	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	8	0	0
T35	781335	0	0	0
T50	0	5	0	0
T53	229820	0	0	0
T65	0	3	0	0
T67	0	29	0	0
T78	0	38	0	0
T105	0	10	0	0
T108	0	4	0	0
T109	0	9	0	0
T125	0	22	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1201996941	1538	0	0
T29	164047	0	0	0
T30	289911	0	0	0
T31	802985	13	0	0
T35	781335	0	0	0
T50	0	2	0	0
T53	229820	0	0	0
T65	0	17	0	0
T67	0	39	0	0
T78	0	25	0	0
T105	0	12	0	0
T109	0	1	0	0
T111	0	2	0	0
T125	0	17	0	0
T137	208722	0	0	0
T138	172521	0	0	0
T139	67248	0	0	0
T140	125740	0	0	0
T141	80732	0	0	0
T241	0	8	0	0