Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2026

1

T1

11

T2

10

T8

21

auto[1]

732

1

T1

4

T2

4

T8

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T1

10

T2

10

T8

28

auto[1]

786

1

T1

5

T2

4

T9

20

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2082

1

T1

5

T2

2

T8

28

auto[1]

676

1

T1

10

T2

12

T10

24

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2130

1

T1

5

T2

12

T8

28

auto[1]

628

1

T1

10

T2

2

T9

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2486

1

T1

15

T2

14

T8

28

auto[1]

272

1

T9

20

T13

1

T48

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2548

1

T1

15

T2

14

T8

21

auto[1]

210

1

T8

7

T13

1

T48

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2554

1

T1

15

T2

14

T8

28

auto[1]

204

1

T13

1

T36

6

T49

12

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2566

1

T1

15

T2

14

T8

28

auto[1]

192

1

T9

3

T36

6

T49

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2490

1

T1

15

T2

14

T8

28

auto[1]

268

1

T9

8

T36

7

T49

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2083

1

T1

10

T8

28

T9

27

auto[1]

675

1

T1

5

T2

14

T9

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

912

1

T1

11

T2

14

T10

24

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

112

1

T9

8

T74

7

T263

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

79

1

T36

7

T247

3

T84

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39

1

T9

7

T74

3

T247

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

84

1

T36

6

T249

6

T264

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T9

2

T264

6

T354

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T49

4

T245

8

T355

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

67

1

T36

6

T49

6

T246

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T247

2

T347

4

T199

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T356

6

T357

3

T358

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T347

4

T356

2

T359

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T49

2

T84

2

T360

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T361

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T8

7

T49

6

T74

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T47

2

T54

2

T252

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T86

1

T354

3

T190

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T101

1

T102

4

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

16

1

T85

4

T199

2

T360

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T362

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13

1

T100

6

T357

3

T359

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T13

1

T252

2

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T356

6

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T363

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

172

1

T8

7

T36

7

T242

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

125

1

T13

1

T247

2

T99

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T181

4

T146

2

T199

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

96

1

T266

8

T102

4

T346

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

55

1

T49

6

T250

5

T86

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T36

6

T265

5

T89

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T37

1

T181

2

T81

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

92

1

T10

11

T101

1

T281

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

74

1

T49

6

T354

3

T364

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T2

6

T10

7

T95

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T2

4

T74

8

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T1

6

T181

3

T74

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T120

5

T99

3

T105

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T47

2

T74

7

T81

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T143

1

T251

3

T146

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T9

2

T12

1

T247

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

87

1

T35

6

T49

2

T245

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

115

1

T1

5

T9

8

T246

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T95

5

T114

6

T249

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

77

1

T9

7

T247

2

T272

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T95

3

T37

1

T101

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T2

2

T35

6

T174

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T272

3

T123

1

T109

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T10

6

T12

1

T49

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T266

2

T123

3

T108

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T2

2

T264

6

T265

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T36

6

T120

2

T281

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T143

2

T113

2

T249

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T105

4

T364

2

T199

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T81

1

T120

2

T263

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T99

2

T365

4

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded