Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T6

9

T23

12

T15

7

auto[1]

1029

1

T6

11

T23

8

T15

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T6

4

T23

4

T15

4

from_0to1

481

1

T6

4

T23

4

T15

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T6

8

T23

12

T15

13

auto[1]

1048

1

T6

12

T23

8

T15

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T6

11

T23

9

T15

10

auto[1]

1051

1

T6

9

T23

11

T15

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T15

1

T17

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T6

1

T15

1

T17

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T23

1

T10

2

T168

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T23

1

T17

1

T10

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T6

2

T10

3

T168

1

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T6

1

T23

1

T15

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T23

1

T15

2

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T23

1

T17

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T23

1

T17

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T15

1

T10

2

T39

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T23

1

T17

1

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T6

2

T15

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T17

1

T132

1

T374

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T23

1

T15

1

T17

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T6

1

T17

1

T132

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T17

1

T10

1

T132

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T6

10

T23

11

T15

9

auto[1]

1004

1

T6

10

T23

9

T15

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T6

6

T23

4

T15

5

from_0to1

502

1

T6

5

T23

5

T15

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T6

11

T23

12

T15

7

auto[1]

999

1

T6

9

T23

8

T15

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T6

9

T23

10

T15

9

auto[1]

1064

1

T6

11

T23

10

T15

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T23

1

T15

1

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T6

1

T23

1

T15

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T6

1

T23

1

T15

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T6

1

T17

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T6

1

T23

1

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T6

2

T23

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T23

1

T15

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T23

1

T10

2

T132

2

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T15

1

T17

1

T168

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T23

1

T17

1

T132

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T6

1

T17

1

T10

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T6

2

T10

1

T132

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T17

2

T10

2

T168

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T15

1

T17

2

T374

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T6

2

T23

1

T15

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T15

1

T311

1

T96

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T6

4

T23

11

T15

8

auto[1]

1064

1

T6

16

T23

9

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T6

6

T23

5

T15

4

from_0to1

518

1

T6

6

T23

6

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T6

11

T23

10

T15

7

auto[1]

1018

1

T6

9

T23

10

T15

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T6

11

T23

11

T15

14

auto[1]

1027

1

T6

9

T23

9

T15

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T6

1

T168

1

T96

3

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T6

1

T10

2

T374

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T23

1

T15

1

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T17

1

T10

1

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T15

1

T17

1

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T23

1

T10

1

T132

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T23

1

T15

2

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T23

1

T17

2

T168

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T23

3

T17

4

T168

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T6

3

T23

1

T15

2

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T6

1

T15

1

T10

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T10

4

T132

1

T96

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T6

1

T23

1

T15

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T6

2

T10

3

T311

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T6

2

T23

2

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T6

1

T15

1

T17

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T6

10

T23

11

T15

9

auto[1]

1032

1

T6

10

T23

9

T15

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T6

4

T23

8

T15

6

from_0to1

494

1

T6

5

T23

7

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T6

13

T23

10

T15

9

auto[1]

1023

1

T6

7

T23

10

T15

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T6

9

T23

14

T15

9

auto[1]

1037

1

T6

11

T23

6

T15

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T6

1

T23

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

94

1

T6

1

T23

1

T15

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T23

1

T15

1

T10

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T6

1

T15

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T6

1

T23

3

T15

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T10

1

T168

1

T311

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T6

1

T23

2

T10

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T15

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T6

1

T15

1

T168

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T23

1

T10

1

T132

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T23

3

T17

1

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T23

1

T10

2

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T23

1

T15

2

T17

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T6

2

T23

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T15

1

T17

1

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T15

1

T10

1

T39

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T6

16

T23

7

T15

8

auto[1]

1022

1

T6

4

T23

13

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T6

5

T23

6

T15

6

from_0to1

512

1

T6

5

T23

6

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T6

10

T23

11

T15

9

auto[1]

1013

1

T6

10

T23

9

T15

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T6

12

T23

9

T15

10

auto[1]

1010

1

T6

8

T23

11

T15

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

82

1

T6

2

T15

1

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T6

1

T23

1

T15

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T23

3

T17

3

T10

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T23

1

T10

2

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T6

2

T168

3

T132

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T15

1

T17

2

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T6

1

T15

1

T168

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T6

1

T15

1

T10

3

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T15

2

T17

1

T168

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T10

2

T132

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T23

1

T15

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T6

1

T15

1

T17

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T23

3

T17

2

T132

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T23

3

T15

1

T17

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T6

1

T15

1

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T15

1

T17

1

T10

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T6

10

T23

12

T15

7

auto[1]

1053

1

T6

10

T23

8

T15

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T6

5

T23

6

T15

4

from_0to1

494

1

T6

6

T23

5

T15

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T6

13

T23

9

T15

10

auto[1]

1048

1

T6

7

T23

11

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T6

8

T23

10

T15

7

auto[1]

1059

1

T6

12

T23

10

T15

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T6

1

T17

2

T168

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T15

2

T17

2

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T6

1

T23

1

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T23

2

T17

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T6

1

T23

2

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T6

3

T132

2

T374

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T15

1

T17

1

T168

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T23

1

T17

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T10

2

T374

2

T311

3

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T6

1

T15

1

T168

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T23

2

T17

1

T10

2

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T6

2

T23

1

T15

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T15

1

T10

1

T168

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T6

1

T23

2

T15

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T6

1

T15

1

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T17

1

T10

1

T168

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T6

14

T23

9

T15

7

auto[1]

1056

1

T6

6

T23

11

T15

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T6

5

T23

2

T15

4

from_0to1

512

1

T6

5

T23

2

T15

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T6

9

T23

5

T15

10

auto[1]

1028

1

T6

11

T23

15

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T6

7

T23

9

T15

8

auto[1]

1016

1

T6

13

T23

11

T15

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T132

2

T39

1

T374

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T6

2

T10

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T15

1

T17

2

T10

3

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T6

1

T17

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T6

2

T168

1

T311

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T10

1

T132

1

T313

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T6

1

T15

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T6

1

T15

1

T17

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T6

1

T17

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T15

1

T10

2

T96

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T17

1

T10

3

T168

3

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T6

1

T23

2

T15

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T10

1

T168

1

T39

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T23

1

T15

1

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T17

3

T10

1

T132

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T6

1

T23

1

T10

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T6

12

T23

12

T15

8

auto[1]

1023

1

T6

8

T23

8

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T6

5

T23

4

T15

5

from_0to1

514

1

T6

6

T23

4

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T6

11

T23

8

T15

15

auto[1]

1007

1

T6

9

T23

12

T15

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T6

12

T23

11

T15

9

auto[1]

1060

1

T6

8

T23

9

T15

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T15

2

T17

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T6

1

T15

1

T17

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T6

1

T23

2

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T23

1

T15

1

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T6

2

T168

1

T132

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T6

1

T23

1

T15

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T17

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T23

1

T15

1

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T168

1

T132

1

T374

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T6

1

T17

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T23

1

T15

1

T132

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T6

1

T17

1

T10

3

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T23

1

T15

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T6

2

T15

1

T39

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T23

1

T15

1

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T17

1

T168

1

T311

2