Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
51.52 51.52 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_wkup_event_cg 51.52 1 100 1 64 64




Group Instance : sysrst_ctrl_wkup_event_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
51.52 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 1 9 90.00
Crosses 23 15 8 34.78


Variables for Group Instance sysrst_ctrl_wkup_event_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_h2l_pwrb 2 0 2 100.00 100 1 1 2
cp_h_ac_present 2 0 2 100.00 100 1 1 2
cp_interrupt_gen 2 1 1 50.00 100 1 1 2
cp_l2h_lid_open 2 0 2 100.00 100 1 1 2
cp_wakeup_sts 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_wkup_event_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_wkup_sts 23 15 8 34.78 100 1 1 0


Summary for Variable cp_h2l_pwrb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h2l_pwrb

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 855 1 T6 3 T21 2 T22 3
auto[1] 762 1 T6 1 T21 2 T22 3



Summary for Variable cp_h_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 975 1 T21 1 T22 3 T24 1
auto[1] 642 1 T6 4 T21 3 T22 3



Summary for Variable cp_interrupt_gen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_interrupt_gen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1617 1 T6 4 T21 4 T22 6



Summary for Variable cp_l2h_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_l2h_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 988 1 T21 1 T22 6 T24 1
auto[1] 629 1 T6 4 T21 3 T23 1



Summary for Variable cp_wakeup_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wakeup_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1548 1 T6 4 T21 4 T22 6
auto[1] 69 1 T7 1 T12 2 T29 1



Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 23 15 8 34.78 15
Automatically Generated Cross Bins 23 15 8 34.78 15
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_wkup_sts

Element holes
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[1]] * * -- -- 4


Uncovered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 361 1 T22 1 T15 1 T55 1
auto[0] auto[0] auto[0] auto[1] auto[0] 161 1 T22 2 T15 1 T55 2
auto[0] auto[0] auto[1] auto[0] auto[0] 152 1 T10 1 T70 1 T12 1
auto[0] auto[0] auto[1] auto[1] auto[0] 181 1 T6 3 T21 2 T23 1
auto[0] auto[1] auto[0] auto[0] auto[0] 244 1 T21 1 T22 2 T24 1
auto[0] auto[1] auto[0] auto[1] auto[0] 153 1 T22 1 T20 1 T68 1
auto[0] auto[1] auto[1] auto[0] auto[0] 149 1 T15 1 T20 3 T55 1
auto[0] auto[1] auto[1] auto[1] auto[0] 147 1 T6 1 T21 1 T20 2


User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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