Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120155

1

T4

2

T5

4

T6

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142920	1			T4	3		T5	6		T6	62
values[0x0]	66436	1			T4	1		T6	28		T21	11
values[0x1]	67901	1			T4	1		T6	33		T21	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149708

1

T4

2

T5

5

T6

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1103	1			T1	1		T14	4		T17	9
valid_sources[0x01]	896	1			T6	1		T1	1		T14	5
valid_sources[0x02]	881	1			T23	6		T1	1		T8	1
valid_sources[0x03]	1084	1			T1	1		T14	1		T2	4
valid_sources[0x04]	1406	1			T1	2		T14	2		T2	19
valid_sources[0x05]	1149	1			T1	3		T8	4		T10	6
valid_sources[0x06]	838	1			T2	1		T8	6		T55	1
valid_sources[0x07]	825	1			T1	1		T14	3		T8	2
valid_sources[0x08]	961	1			T14	3		T17	9		T68	3
valid_sources[0x09]	1071	1			T1	1		T2	1		T8	2
valid_sources[0x0a]	827	1			T1	4		T14	1		T2	3
valid_sources[0x0b]	1904	1			T1	1		T14	2		T2	1
valid_sources[0x0c]	1046	1			T1	1		T14	1		T2	4
valid_sources[0x0d]	899	1			T6	1		T1	3		T14	1
valid_sources[0x0e]	881	1			T6	2		T23	7		T1	5
valid_sources[0x0f]	874	1			T14	2		T16	1		T2	13
valid_sources[0x10]	887	1			T1	4		T14	1		T8	6
valid_sources[0x11]	758	1			T1	7		T14	1		T8	5
valid_sources[0x12]	829	1			T1	6		T2	10		T8	1
valid_sources[0x13]	928	1			T6	1		T1	3		T14	2
valid_sources[0x14]	1032	1			T24	2		T1	4		T14	1
valid_sources[0x15]	903	1			T1	1		T8	2		T10	2
valid_sources[0x16]	825	1			T1	4		T14	2		T8	3
valid_sources[0x17]	1179	1			T1	2		T8	5		T10	4
valid_sources[0x18]	813	1			T1	3		T14	1		T2	4
valid_sources[0x19]	800	1			T6	2		T1	3		T14	2
valid_sources[0x1a]	827	1			T1	4		T8	4		T69	1
valid_sources[0x1b]	1416	1			T6	2		T1	4		T14	1
valid_sources[0x1c]	931	1			T1	4		T2	2		T3	1
valid_sources[0x1d]	1334	1			T1	3		T2	1		T7	1
valid_sources[0x1e]	1376	1			T4	5		T5	1		T1	6
valid_sources[0x1f]	1205	1			T6	5		T1	4		T14	1
valid_sources[0x20]	906	1			T1	1		T14	4		T10	3
valid_sources[0x21]	1039	1			T1	2		T2	13		T8	2
valid_sources[0x22]	869	1			T1	1		T14	4		T2	4
valid_sources[0x23]	1083	1			T6	3		T1	1		T3	1
valid_sources[0x24]	911	1			T1	1		T14	5		T2	4
valid_sources[0x25]	922	1			T6	4		T1	2		T14	1
valid_sources[0x26]	934	1			T21	3		T1	5		T14	3
valid_sources[0x27]	1423	1			T1	2		T14	5		T8	2
valid_sources[0x28]	984	1			T1	1		T14	4		T2	4
valid_sources[0x29]	994	1			T1	2		T14	3		T2	3
valid_sources[0x2a]	865	1			T6	2		T23	13		T14	1
valid_sources[0x2b]	1116	1			T1	3		T14	1		T2	4
valid_sources[0x2c]	941	1			T1	1		T14	3		T2	1
valid_sources[0x2d]	2250	1			T24	1		T1	3		T14	3
valid_sources[0x2e]	871	1			T1	2		T8	1		T69	2
valid_sources[0x2f]	942	1			T1	1		T14	1		T2	2
valid_sources[0x30]	808	1			T1	6		T14	1		T2	2
valid_sources[0x31]	971	1			T1	1		T14	1		T8	9
valid_sources[0x32]	890	1			T6	1		T1	4		T14	2
valid_sources[0x33]	1398	1			T23	10		T1	3		T14	1
valid_sources[0x34]	972	1			T14	1		T17	1		T2	1
valid_sources[0x35]	935	1			T6	1		T23	1		T1	1
valid_sources[0x36]	786	1			T6	1		T1	2		T14	2
valid_sources[0x37]	974	1			T1	5		T14	1		T2	5
valid_sources[0x38]	976	1			T1	2		T14	2		T2	4
valid_sources[0x39]	1052	1			T6	4		T1	3		T2	2
valid_sources[0x3a]	1080	1			T1	1		T16	1		T2	1
valid_sources[0x3b]	1123	1			T1	3		T14	4		T7	1
valid_sources[0x3c]	806	1			T1	3		T14	1		T2	2
valid_sources[0x3d]	1000	1			T1	4		T2	3		T8	1
valid_sources[0x3e]	799	1			T1	4		T14	5		T17	3
valid_sources[0x3f]	985	1			T1	1		T14	1		T8	8
valid_sources[0x40]	856	1			T6	2		T14	5		T8	2
valid_sources[0x41]	965	1			T1	3		T14	3		T2	9
valid_sources[0x42]	1110	1			T1	2		T14	1		T2	9
valid_sources[0x43]	1029	1			T8	2		T55	1		T34	1
valid_sources[0x44]	819	1			T14	4		T2	5		T7	2
valid_sources[0x45]	929	1			T1	2		T14	1		T2	4
valid_sources[0x46]	1243	1			T1	1		T14	1		T8	3
valid_sources[0x47]	815	1			T14	2		T2	3		T8	1
valid_sources[0x48]	1109	1			T21	12		T14	4		T8	1
valid_sources[0x49]	991	1			T6	6		T14	2		T8	1
valid_sources[0x4a]	913	1			T14	1		T16	1		T69	1
valid_sources[0x4b]	1041	1			T1	5		T14	1		T2	1
valid_sources[0x4c]	1162	1			T2	1		T8	6		T68	3
valid_sources[0x4d]	993	1			T1	2		T14	1		T17	5
valid_sources[0x4e]	1362	1			T1	1		T14	1		T2	7
valid_sources[0x4f]	1349	1			T1	3		T14	1		T2	1
valid_sources[0x50]	1058	1			T1	3		T14	4		T8	3
valid_sources[0x51]	1536	1			T1	4		T14	2		T2	10
valid_sources[0x52]	1371	1			T6	5		T1	4		T2	6
valid_sources[0x53]	925	1			T6	1		T1	4		T14	1
valid_sources[0x54]	1282	1			T1	6		T14	5		T2	1
valid_sources[0x55]	1088	1			T6	2		T1	3		T14	3
valid_sources[0x56]	1081	1			T6	2		T1	2		T14	3
valid_sources[0x57]	925	1			T1	1		T17	2		T2	4
valid_sources[0x58]	1123	1			T6	1		T1	1		T14	6
valid_sources[0x59]	1509	1			T1	1		T14	3		T8	12
valid_sources[0x5a]	908	1			T1	2		T14	3		T8	2
valid_sources[0x5b]	948	1			T1	1		T14	2		T17	5
valid_sources[0x5c]	998	1			T14	1		T2	1		T8	7
valid_sources[0x5d]	1097	1			T23	5		T1	2		T14	2
valid_sources[0x5e]	1065	1			T14	4		T2	2		T68	1
valid_sources[0x5f]	1977	1			T1	5		T16	1		T2	4
valid_sources[0x60]	1614	1			T1	1		T14	2		T8	3
valid_sources[0x61]	1444	1			T6	1		T1	1		T14	2
valid_sources[0x62]	987	1			T6	1		T1	3		T14	2
valid_sources[0x63]	769	1			T1	1		T14	2		T2	1
valid_sources[0x64]	983	1			T23	6		T1	1		T14	3
valid_sources[0x65]	1412	1			T6	1		T14	1		T2	1
valid_sources[0x66]	985	1			T1	4		T14	1		T16	1
valid_sources[0x67]	1902	1			T22	2		T1	3		T14	1
valid_sources[0x68]	1038	1			T1	5		T14	1		T16	1
valid_sources[0x69]	1137	1			T6	3		T1	2		T14	4
valid_sources[0x6a]	1777	1			T6	2		T1	1		T14	5
valid_sources[0x6b]	972	1			T23	2		T1	2		T14	1
valid_sources[0x6c]	973	1			T1	3		T14	2		T2	1
valid_sources[0x6d]	806	1			T1	4		T14	2		T2	3
valid_sources[0x6e]	980	1			T1	2		T14	1		T8	4
valid_sources[0x6f]	2026	1			T1	6		T14	3		T8	2
valid_sources[0x70]	967	1			T1	3		T14	1		T2	10
valid_sources[0x71]	763	1			T1	3		T14	2		T2	3
valid_sources[0x72]	938	1			T6	1		T14	4		T16	1
valid_sources[0x73]	977	1			T14	1		T8	1		T68	1
valid_sources[0x74]	847	1			T6	1		T1	2		T14	2
valid_sources[0x75]	944	1			T1	1		T14	1		T16	1
valid_sources[0x76]	1056	1			T23	9		T24	1		T1	4
valid_sources[0x77]	795	1			T1	1		T14	1		T8	4
valid_sources[0x78]	1598	1			T1	3		T14	2		T16	3
valid_sources[0x79]	811	1			T1	1		T14	3		T2	1
valid_sources[0x7a]	1807	1			T6	2		T1	1		T14	4
valid_sources[0x7b]	1058	1			T1	3		T14	2		T17	2
valid_sources[0x7c]	839	1			T6	2		T23	8		T1	4
valid_sources[0x7d]	962	1			T6	5		T1	7		T17	10
valid_sources[0x7e]	1827	1			T6	1		T1	1		T14	3
valid_sources[0x7f]	911	1			T1	1		T17	19		T2	1
valid_sources[0x80]	881	1			T6	1		T1	2		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64856

1

T4

1

T5

4

T6

30

values[0x0]

all_enables

biggest_size

32384

1

T4

1

T6

9

T21

5

values[0x1]

all_enables

biggest_size

22915

1

T6

4

T21

3

T22

3