Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 91.67 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block] 91.67 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.67 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 2 12 91.67


Variables for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 1 3 75.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 290760 0 T4 5 T5 6 T6 123



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 290552 1 T4 5 T5 6 T6 123
values[1] 24 1 T279 4 T351 1 T352 2
values[3] 107 1 T33 4 T279 2 T280 5



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 290553 1 T4 5 T5 6 T6 123
values[1] 16 1 T279 2 T292 1 T293 1
values[2] 3 1 T280 1 T293 1 T353 1
values[3] 111 1 T33 4 T279 7 T280 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 290450 1 T4 5 T5 6 T6 123
auto[TlIntgErrCmd] 103 1 T33 3 T279 3 T280 4
auto[TlIntgErrData] 102 1 T33 4 T279 8 T280 3
auto[TlIntgErrBoth] 105 1 T33 3 T279 9 T280 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%