Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1082074859	9422	0	0
auto_block_debounce_ctl_rd_A	1082074859	1634	0	0
auto_block_out_ctl_rd_A	1082074859	2059	0	0
com_det_ctl_0_rd_A	1082074859	3183	0	0
com_det_ctl_1_rd_A	1082074859	3299	0	0
com_det_ctl_2_rd_A	1082074859	3082	0	0
com_det_ctl_3_rd_A	1082074859	3229	0	0
com_out_ctl_0_rd_A	1082074859	3589	0	0
com_out_ctl_1_rd_A	1082074859	3753	0	0
com_out_ctl_2_rd_A	1082074859	3631	0	0
com_out_ctl_3_rd_A	1082074859	3568	0	0
com_pre_det_ctl_0_rd_A	1082074859	1113	0	0
com_pre_det_ctl_1_rd_A	1082074859	1203	0	0
com_pre_det_ctl_2_rd_A	1082074859	1109	0	0
com_pre_det_ctl_3_rd_A	1082074859	1182	0	0
com_pre_sel_ctl_0_rd_A	1082074859	4053	0	0
com_pre_sel_ctl_1_rd_A	1082074859	3749	0	0
com_pre_sel_ctl_2_rd_A	1082074859	3657	0	0
com_pre_sel_ctl_3_rd_A	1082074859	3772	0	0
com_sel_ctl_0_rd_A	1082074859	3740	0	0
com_sel_ctl_1_rd_A	1082074859	3934	0	0
com_sel_ctl_2_rd_A	1082074859	3930	0	0
com_sel_ctl_3_rd_A	1082074859	3862	0	0
ec_rst_ctl_rd_A	1082074859	2088	0	0
intr_enable_rd_A	1082074859	1669	0	0
key_intr_ctl_rd_A	1082074859	3297	0	0
key_intr_debounce_ctl_rd_A	1082074859	1152	0	0
key_invert_ctl_rd_A	1082074859	4908	0	0
pin_allowed_ctl_rd_A	1082074859	5601	0	0
pin_out_ctl_rd_A	1082074859	4238	0	0
pin_out_value_rd_A	1082074859	4276	0	0
regwen_rd_A	1082074859	1182	0	0
ulp_ac_debounce_ctl_rd_A	1082074859	1235	0	0
ulp_ctl_rd_A	1082074859	1301	0	0
ulp_lid_debounce_ctl_rd_A	1082074859	1298	0	0
ulp_pwrb_debounce_ctl_rd_A	1082074859	1384	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	9422	0	0
T10	406323	10	0	0
T11	76620	0	0	0
T12	603365	21	0	0
T39	0	28	0	0
T41	0	10	0	0
T59	386962	0	0	0
T60	202340	0	0	0
T70	174899	0	0	0
T71	128215	0	0	0
T78	0	16	0	0
T81	0	6	0	0
T96	0	10	0	0
T121	0	15	0	0
T164	209655	0	0	0
T183	0	13	0	0
T210	200391	0	0	0
T211	57323	0	0	0
T223	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1634	0	0
T8	598486	0	0	0
T9	101883	0	0	0
T30	366973	10	0	0
T34	54066	0	0	0
T41	0	30	0	0
T50	340612	0	0	0
T51	0	8	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T104	0	7	0	0
T112	95709	0	0	0
T122	0	44	0	0
T124	0	6	0	0
T146	0	37	0	0
T273	0	18	0	0
T281	0	43	0	0
T303	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	2059	0	0
T8	598486	0	0	0
T9	101883	0	0	0
T30	366973	6	0	0
T34	54066	0	0	0
T41	0	26	0	0
T50	340612	0	0	0
T51	0	8	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T104	0	5	0	0
T112	95709	0	0	0
T122	0	37	0	0
T124	0	11	0	0
T146	0	28	0	0
T273	0	10	0	0
T281	0	24	0	0
T303	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3183	0	0
T8	598486	40	0	0
T9	101883	64	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	42	0	0
T41	0	21	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	44	0	0
T112	95709	0	0	0
T181	0	59	0	0
T242	0	39	0	0
T247	0	23	0	0
T250	0	44	0	0
T266	0	84	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3299	0	0
T8	598486	44	0	0
T9	101883	55	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	47	0	0
T41	0	22	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	43	0	0
T112	95709	0	0	0
T181	0	54	0	0
T242	0	20	0	0
T247	0	35	0	0
T250	0	32	0	0
T266	0	68	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3082	0	0
T8	598486	39	0	0
T9	101883	77	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	32	0	0
T41	0	18	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	67	0	0
T112	95709	0	0	0
T181	0	40	0	0
T242	0	29	0	0
T247	0	49	0	0
T250	0	13	0	0
T266	0	90	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3229	0	0
T8	598486	30	0	0
T9	101883	50	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	28	0	0
T41	0	22	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	91	0	0
T112	95709	0	0	0
T181	0	44	0	0
T242	0	46	0	0
T247	0	28	0	0
T250	0	53	0	0
T266	0	88	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3589	0	0
T8	598486	29	0	0
T9	101883	55	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	17	0	0
T41	0	20	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	64	0	0
T112	95709	0	0	0
T181	0	31	0	0
T242	0	32	0	0
T247	0	29	0	0
T250	0	57	0	0
T266	0	75	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3753	0	0
T8	598486	15	0	0
T9	101883	44	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	56	0	0
T41	0	22	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	65	0	0
T112	95709	0	0	0
T181	0	46	0	0
T242	0	29	0	0
T247	0	49	0	0
T250	0	42	0	0
T266	0	81	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3631	0	0
T8	598486	47	0	0
T9	101883	53	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	41	0	0
T41	0	19	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	66	0	0
T112	95709	0	0	0
T181	0	52	0	0
T242	0	28	0	0
T247	0	27	0	0
T250	0	63	0	0
T266	0	89	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3568	0	0
T8	598486	21	0	0
T9	101883	72	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	19	0	0
T41	0	26	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	56	0	0
T112	95709	0	0	0
T181	0	49	0	0
T242	0	37	0	0
T247	0	37	0	0
T250	0	42	0	0
T266	0	77	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1113	0	0
T41	269724	14	0	0
T89	0	13	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	11	0	0
T146	0	13	0	0
T151	0	26	0	0
T152	0	46	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	8	0	0
T281	0	11	0	0
T304	0	10	0	0
T305	0	12	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1203	0	0
T41	269724	10	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	20	0	0
T146	0	4	0	0
T151	0	15	0	0
T152	0	37	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	11	0	0
T281	0	24	0	0
T304	0	5	0	0
T305	0	24	0	0
T306	0	14	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1109	0	0
T41	269724	8	0	0
T89	0	12	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	7	0	0
T146	0	17	0	0
T151	0	9	0	0
T152	0	28	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	1	0	0
T281	0	20	0	0
T304	0	6	0	0
T305	0	14	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1182	0	0
T41	269724	5	0	0
T89	0	5	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	15	0	0
T146	0	10	0	0
T151	0	27	0	0
T152	0	30	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	10	0	0
T281	0	25	0	0
T304	0	12	0	0
T305	0	3	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	4053	0	0
T8	598486	30	0	0
T9	101883	73	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	40	0	0
T41	0	12	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	56	0	0
T112	95709	0	0	0
T181	0	52	0	0
T242	0	36	0	0
T247	0	38	0	0
T250	0	46	0	0
T266	0	69	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3749	0	0
T8	598486	42	0	0
T9	101883	49	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	39	0	0
T41	0	8	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	71	0	0
T112	95709	0	0	0
T181	0	32	0	0
T242	0	31	0	0
T247	0	36	0	0
T250	0	41	0	0
T266	0	93	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3657	0	0
T8	598486	24	0	0
T9	101883	55	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	46	0	0
T41	0	22	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	69	0	0
T112	95709	0	0	0
T181	0	38	0	0
T242	0	33	0	0
T247	0	30	0	0
T250	0	35	0	0
T266	0	64	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3772	0	0
T8	598486	36	0	0
T9	101883	50	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	41	0	0
T41	0	11	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	47	0	0
T112	95709	0	0	0
T181	0	27	0	0
T242	0	31	0	0
T247	0	54	0	0
T250	0	53	0	0
T266	0	72	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3740	0	0
T8	598486	40	0	0
T9	101883	65	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	55	0	0
T41	0	15	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	76	0	0
T112	95709	0	0	0
T181	0	33	0	0
T242	0	34	0	0
T247	0	36	0	0
T250	0	27	0	0
T266	0	69	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3934	0	0
T8	598486	23	0	0
T9	101883	63	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	26	0	0
T41	0	23	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	76	0	0
T112	95709	0	0	0
T181	0	47	0	0
T242	0	36	0	0
T247	0	69	0	0
T250	0	26	0	0
T266	0	75	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3930	0	0
T8	598486	34	0	0
T9	101883	64	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	33	0	0
T41	0	25	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	54	0	0
T112	95709	0	0	0
T181	0	39	0	0
T242	0	26	0	0
T247	0	39	0	0
T250	0	41	0	0
T266	0	85	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3862	0	0
T8	598486	54	0	0
T9	101883	46	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	29	0	0
T41	0	25	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	0	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	85	0	0
T112	95709	0	0	0
T181	0	38	0	0
T242	0	35	0	0
T247	0	28	0	0
T250	0	45	0	0
T266	0	55	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	2088	0	0
T8	598486	6	0	0
T9	101883	35	0	0
T10	406323	0	0	0
T34	54066	0	0	0
T35	0	4	0	0
T50	340612	0	0	0
T55	63254	0	0	0
T58	57216	4	0	0
T68	248176	0	0	0
T69	63251	0	0	0
T95	0	50	0	0
T112	95709	0	0	0
T165	0	7	0	0
T181	0	42	0	0
T237	0	2	0	0
T242	0	6	0	0
T266	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1669	0	0
T41	269724	56	0	0
T89	0	13	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	45	0	0
T146	0	56	0	0
T151	0	9	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	5	0	0
T281	0	38	0	0
T304	0	16	0	0
T305	0	20	0	0
T307	0	6	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	3297	0	0
T35	238663	0	0	0
T36	229971	0	0	0
T38	0	6	0	0
T41	0	31	0	0
T42	34789	3	0	0
T47	359897	0	0	0
T64	231446	0	0	0
T72	60465	5	0	0
T73	230422	1	0	0
T122	0	30	0	0
T139	0	3	0	0
T146	0	29	0	0
T154	0	4	0	0
T177	46784	0	0	0
T178	98493	0	0	0
T179	256264	0	0	0
T281	0	26	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1152	0	0
T41	269724	8	0	0
T89	0	2	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	19	0	0
T146	0	17	0	0
T151	0	13	0	0
T152	0	37	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	12	0	0
T281	0	14	0	0
T304	0	8	0	0
T305	0	20	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	4908	0	0
T41	0	66	0	0
T54	101132	0	0	0
T74	110122	0	0	0
T76	25066	0	0	0
T122	0	149	0	0
T139	0	84	0	0
T146	0	64	0	0
T185	233130	67	0	0
T186	193106	0	0	0
T242	295889	0	0	0
T266	776829	0	0	0
T273	0	59	0	0
T281	0	15	0	0
T304	0	86	0	0
T308	0	73	0	0
T309	0	75	0	0
T310	57966	0	0	0
T311	63163	0	0	0
T312	63046	0	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	5601	0	0
T1	637456	0	0	0
T2	272586	0	0	0
T14	204112	0	0	0
T15	250999	95	0	0
T16	212177	0	0	0
T17	63473	0	0	0
T18	199451	0	0	0
T19	195363	0	0	0
T23	63059	87	0	0
T24	195154	0	0	0
T41	0	158	0	0
T122	0	139	0	0
T146	0	2	0	0
T168	0	10	0	0
T311	0	36	0	0
T313	0	52	0	0
T314	0	65	0	0
T315	0	91	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	4238	0	0
T1	637456	0	0	0
T2	272586	0	0	0
T14	204112	0	0	0
T15	250999	45	0	0
T16	212177	0	0	0
T17	63473	0	0	0
T18	199451	0	0	0
T19	195363	0	0	0
T23	63059	66	0	0
T24	195154	0	0	0
T41	0	141	0	0
T122	0	149	0	0
T146	0	16	0	0
T168	0	47	0	0
T311	0	49	0	0
T313	0	62	0	0
T314	0	58	0	0
T315	0	92	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	4276	0	0
T1	637456	0	0	0
T2	272586	0	0	0
T14	204112	0	0	0
T15	250999	75	0	0
T16	212177	0	0	0
T17	63473	0	0	0
T18	199451	0	0	0
T19	195363	0	0	0
T23	63059	68	0	0
T24	195154	0	0	0
T41	0	172	0	0
T122	0	166	0	0
T146	0	5	0	0
T168	0	69	0	0
T311	0	50	0	0
T313	0	74	0	0
T314	0	62	0	0
T315	0	79	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1182	0	0
T41	269724	2	0	0
T89	0	8	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	22	0	0
T146	0	8	0	0
T151	0	29	0	0
T152	0	36	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T273	0	3	0	0
T281	0	16	0	0
T304	0	10	0	0
T305	0	13	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1235	0	0
T1	637456	0	0	0
T2	272586	0	0	0
T14	204112	0	0	0
T15	250999	0	0	0
T16	212177	0	0	0
T17	63473	0	0	0
T18	199451	0	0	0
T19	195363	0	0	0
T20	221959	0	0	0
T24	195154	2	0	0
T41	0	14	0	0
T61	0	2	0	0
T122	0	38	0	0
T146	0	13	0	0
T273	0	12	0	0
T281	0	39	0	0
T304	0	2	0	0
T305	0	13	0	0
T316	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1301	0	0
T29	56249	8	0	0
T41	0	21	0	0
T45	157222	0	0	0
T46	54242	0	0	0
T49	798984	0	0	0
T51	319404	0	0	0
T61	194803	4	0	0
T62	250063	0	0	0
T89	0	13	0	0
T122	0	13	0	0
T146	0	19	0	0
T273	0	11	0	0
T281	0	20	0	0
T304	0	5	0	0
T305	0	25	0	0
T317	109398	0	0	0
T318	103956	0	0	0
T319	208810	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1298	0	0
T29	56249	0	0	0
T41	0	25	0	0
T45	157222	0	0	0
T46	54242	0	0	0
T49	798984	0	0	0
T51	319404	0	0	0
T61	194803	5	0	0
T62	250063	0	0	0
T89	0	6	0	0
T122	0	38	0	0
T146	0	13	0	0
T273	0	13	0	0
T281	0	41	0	0
T304	0	10	0	0
T305	0	9	0	0
T317	109398	0	0	0
T318	103956	0	0	0
T319	208810	0	0	0
T320	0	12	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1082074859	1384	0	0
T41	269724	18	0	0
T89	0	10	0	0
T115	115058	0	0	0
T116	609605	0	0	0
T117	63090	0	0	0
T118	236165	0	0	0
T119	51618	0	0	0
T120	249455	0	0	0
T122	0	15	0	0
T146	0	16	0	0
T222	50782	0	0	0
T223	184066	0	0	0
T224	158232	0	0	0
T281	0	36	0	0
T304	0	7	0	0
T305	0	19	0	0
T316	0	3	0	0
T320	0	15	0	0
T321	0	2	0	0