Unified Coverage Report :: Module

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORE	LINE
83.33	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
283	1	1
284	1	1
299		unreachable

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.16	92.00

tb.dut.u_reg.u_wkup_status_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	46	92.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	5	83.33
ALWAYS	155	10	9	90.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	17	89.47
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	1	1
129	1	1
132	1	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	0	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	0	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	0	1
211	0	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORE	COND
83.33	66.67

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.16	86.05

tb.dut.u_reg.u_wkup_status_cdc.u_arb

	Total	Covered	Percent
Conditions	43	37	86.05
Logical	43	37	86.05
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T26,T27
1	1	Covered	T28,T25,T26

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T28,T25,T26

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T7
1	0	Covered	T28,T25,T26

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T26,T27
1	1	Covered	T1,T2,T7

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T28,T25,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T7

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

Branch Coverage for Module : prim_reg_cdc_arb

	Line No.	Total	Covered	Percent
Branches		23	19	82.61
IF	111	2	2	100.00
IF	121	4	4	100.00
IF	139	4	3	75.00
IF	155	6	5	83.33
CASE	197	7	5	71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T28,T25,T26
0	0	1	Covered	T28,T25,T26
0	0	0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T7
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T1,T2,T7
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Not Covered
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

Assert Coverage for Module : prim_reg_cdc_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	6699677	780	0	914
gen_wr_req.HwIdSelCheck_A	6699677	780	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Incomplete
Total	6699677	780	914
T1	25498	9	1
T2	24781	8	1
T3	786	1	1
T7	0	1	0
T8	0	7	0
T9	0	3	0
T10	0	12	0
T11	0	1	0
T12	0	4	0
T13	0	1	0
T14	5102	0	1
T15	502	0	1
T16	424	0	1
T17	507	0	1
T18	40704	0	1
T19	406	0	1
T20	492	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes
Total	6699677	780
T1	25498	9
T2	24781	8
T3	786	1
T7	0	1
T8	0	7
T9	0	3
T10	0	12
T11	0	1
T12	0	4
T13	0	1
T14	5102	0
T15	502	0
T16	424	0
T17	507	0
T18	40704	0
T19	406	0
T20	492	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.91	96.00	93.02			82.61	100.00