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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 98.81 96.78 100.00 95.51 98.26 99.52 88.50


Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T31 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3169188057 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:10 PM PDT 24 2046988095 ps
T32 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3333521708 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:18 PM PDT 24 4055017804 ps
T33 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4104640060 Jun 24 05:44:10 PM PDT 24 Jun 24 05:45:07 PM PDT 24 22174795720 ps
T275 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.936557580 Jun 24 05:43:54 PM PDT 24 Jun 24 05:44:02 PM PDT 24 2085626408 ps
T283 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1556893630 Jun 24 05:43:58 PM PDT 24 Jun 24 05:44:02 PM PDT 24 2130698815 ps
T794 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1867398151 Jun 24 05:44:16 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2035708640 ps
T284 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.926653360 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2118791531 ps
T285 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.139299917 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:15 PM PDT 24 2095764843 ps
T339 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.553794968 Jun 24 05:43:58 PM PDT 24 Jun 24 05:44:05 PM PDT 24 2038650122 ps
T286 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1089790565 Jun 24 05:44:09 PM PDT 24 Jun 24 05:44:16 PM PDT 24 5019653091 ps
T28 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2425859035 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:17 PM PDT 24 2050591979 ps
T282 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.155125806 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:09 PM PDT 24 2495154151 ps
T795 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2728510269 Jun 24 05:44:08 PM PDT 24 Jun 24 05:44:12 PM PDT 24 2021331591 ps
T796 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2663747948 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:18 PM PDT 24 2061552625 ps
T25 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1681150683 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:24 PM PDT 24 4306457000 ps
T797 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3583071198 Jun 24 05:44:08 PM PDT 24 Jun 24 05:44:11 PM PDT 24 2032837644 ps
T279 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.439467742 Jun 24 05:43:55 PM PDT 24 Jun 24 05:45:49 PM PDT 24 42400768447 ps
T26 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1737780262 Jun 24 05:44:17 PM PDT 24 Jun 24 05:44:24 PM PDT 24 5441821784 ps
T798 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2532694603 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:15 PM PDT 24 2013785579 ps
T799 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3812768234 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:10 PM PDT 24 2015880333 ps
T27 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1708244568 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:30 PM PDT 24 4534291247 ps
T340 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4287462506 Jun 24 05:44:00 PM PDT 24 Jun 24 05:44:05 PM PDT 24 5020245261 ps
T341 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2733057219 Jun 24 05:43:52 PM PDT 24 Jun 24 05:43:59 PM PDT 24 4615995834 ps
T326 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.596612206 Jun 24 05:43:58 PM PDT 24 Jun 24 05:44:08 PM PDT 24 6018658702 ps
T280 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.816292868 Jun 24 05:44:21 PM PDT 24 Jun 24 05:44:27 PM PDT 24 24326873798 ps
T292 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1793782929 Jun 24 05:44:09 PM PDT 24 Jun 24 05:44:27 PM PDT 24 22277802273 ps
T800 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.522836580 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:32 PM PDT 24 2019395369 ps
T327 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.4068616588 Jun 24 05:44:10 PM PDT 24 Jun 24 05:44:12 PM PDT 24 2151341625 ps
T342 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.521654580 Jun 24 05:44:00 PM PDT 24 Jun 24 05:44:43 PM PDT 24 8914544364 ps
T294 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1539803294 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:52 PM PDT 24 2084931785 ps
T801 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3026674030 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:08 PM PDT 24 2015837691 ps
T328 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1747640585 Jun 24 05:43:50 PM PDT 24 Jun 24 05:44:00 PM PDT 24 2278832815 ps
T802 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3666689374 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:31 PM PDT 24 2028300372 ps
T803 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2637869642 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:22 PM PDT 24 2010271476 ps
T804 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1142934264 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:31 PM PDT 24 2028485364 ps
T287 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3709317632 Jun 24 05:44:01 PM PDT 24 Jun 24 05:44:07 PM PDT 24 2096191822 ps
T805 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1312610454 Jun 24 05:44:31 PM PDT 24 Jun 24 05:44:40 PM PDT 24 2023718666 ps
T806 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1580996063 Jun 24 05:44:03 PM PDT 24 Jun 24 05:44:10 PM PDT 24 2076624575 ps
T807 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3571482435 Jun 24 05:44:20 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2015286887 ps
T288 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3422945185 Jun 24 05:44:10 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2328770663 ps
T808 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1575165904 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:57 PM PDT 24 2038488597 ps
T293 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1160429592 Jun 24 05:43:47 PM PDT 24 Jun 24 05:44:49 PM PDT 24 22198938910 ps
T329 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1276263522 Jun 24 05:43:46 PM PDT 24 Jun 24 05:46:04 PM PDT 24 50889391507 ps
T351 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.125633818 Jun 24 05:43:54 PM PDT 24 Jun 24 05:44:20 PM PDT 24 22238319971 ps
T809 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2099566458 Jun 24 05:44:01 PM PDT 24 Jun 24 05:44:33 PM PDT 24 8574267173 ps
T810 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2446001459 Jun 24 05:43:55 PM PDT 24 Jun 24 05:44:10 PM PDT 24 5318833325 ps
T811 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.503526980 Jun 24 05:44:22 PM PDT 24 Jun 24 05:44:29 PM PDT 24 2076203079 ps
T289 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3004691484 Jun 24 05:43:52 PM PDT 24 Jun 24 05:43:58 PM PDT 24 2090048333 ps
T812 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1674620331 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:30 PM PDT 24 2031423015 ps
T813 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1716457403 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 2042585689 ps
T814 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3507466866 Jun 24 05:44:07 PM PDT 24 Jun 24 05:44:10 PM PDT 24 2028811044 ps
T815 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1099859839 Jun 24 05:43:51 PM PDT 24 Jun 24 05:44:08 PM PDT 24 3013345710 ps
T816 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3581399798 Jun 24 05:44:17 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2041592520 ps
T817 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3686965218 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:34 PM PDT 24 2016365406 ps
T818 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.966920301 Jun 24 05:43:53 PM PDT 24 Jun 24 05:44:02 PM PDT 24 5344008185 ps
T330 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.64978536 Jun 24 05:43:52 PM PDT 24 Jun 24 05:44:00 PM PDT 24 2042620189 ps
T819 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1468199952 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:52 PM PDT 24 2015684047 ps
T820 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3005495255 Jun 24 05:44:10 PM PDT 24 Jun 24 05:44:13 PM PDT 24 2356596149 ps
T821 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.569037653 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2052754494 ps
T822 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.574723361 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2048100103 ps
T823 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2032240647 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:20 PM PDT 24 4156898547 ps
T824 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.991801635 Jun 24 05:44:22 PM PDT 24 Jun 24 05:45:24 PM PDT 24 22180689657 ps
T331 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.514921887 Jun 24 05:43:57 PM PDT 24 Jun 24 05:49:16 PM PDT 24 73396553386 ps
T291 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.880901575 Jun 24 05:44:28 PM PDT 24 Jun 24 05:44:37 PM PDT 24 2060263641 ps
T352 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1902961978 Jun 24 05:44:10 PM PDT 24 Jun 24 05:45:11 PM PDT 24 22225287796 ps
T825 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4203646780 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:11 PM PDT 24 2009660002 ps
T826 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1105352025 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:08 PM PDT 24 2022137509 ps
T827 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3116022562 Jun 24 05:44:12 PM PDT 24 Jun 24 05:45:16 PM PDT 24 22198432727 ps
T290 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3244307680 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2038019608 ps
T828 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2963253396 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:24 PM PDT 24 9949814873 ps
T829 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2370116484 Jun 24 05:44:17 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2039971475 ps
T830 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4291064336 Jun 24 05:44:21 PM PDT 24 Jun 24 05:44:25 PM PDT 24 2024757393 ps
T831 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1306706986 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 2187424917 ps
T832 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2424431734 Jun 24 05:44:29 PM PDT 24 Jun 24 05:44:35 PM PDT 24 2145158946 ps
T833 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3430865817 Jun 24 05:44:29 PM PDT 24 Jun 24 05:44:35 PM PDT 24 2096239199 ps
T834 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1294323154 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:19 PM PDT 24 2040825755 ps
T835 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.376077119 Jun 24 05:44:21 PM PDT 24 Jun 24 05:44:24 PM PDT 24 2026055491 ps
T836 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.94374687 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:15 PM PDT 24 2035338662 ps
T837 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3475382232 Jun 24 05:43:49 PM PDT 24 Jun 24 05:44:07 PM PDT 24 5128108658 ps
T332 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3916783514 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2080586179 ps
T838 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2636567605 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:19 PM PDT 24 2046264830 ps
T839 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.164154088 Jun 24 05:44:09 PM PDT 24 Jun 24 05:44:12 PM PDT 24 6272389281 ps
T840 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3413019605 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2050487998 ps
T841 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.283693995 Jun 24 05:44:18 PM PDT 24 Jun 24 05:44:24 PM PDT 24 2218996193 ps
T842 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.770638697 Jun 24 05:44:10 PM PDT 24 Jun 24 05:44:34 PM PDT 24 9482872490 ps
T333 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2156864571 Jun 24 05:44:14 PM PDT 24 Jun 24 05:47:22 PM PDT 24 40483460371 ps
T334 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.658005673 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:50 PM PDT 24 2129450430 ps
T843 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.331956461 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:14 PM PDT 24 2034293705 ps
T844 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1930448281 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:27 PM PDT 24 43297698669 ps
T845 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2203348680 Jun 24 05:43:50 PM PDT 24 Jun 24 05:44:00 PM PDT 24 7600265671 ps
T846 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2836465142 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:54 PM PDT 24 2136674771 ps
T847 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1692775572 Jun 24 05:43:52 PM PDT 24 Jun 24 05:45:46 PM PDT 24 42364621498 ps
T848 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4155248395 Jun 24 05:44:20 PM PDT 24 Jun 24 05:44:23 PM PDT 24 2054407830 ps
T849 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3905421717 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:54 PM PDT 24 2038447254 ps
T335 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3390154266 Jun 24 05:43:52 PM PDT 24 Jun 24 05:44:01 PM PDT 24 2925820692 ps
T850 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2023359003 Jun 24 05:44:07 PM PDT 24 Jun 24 05:44:09 PM PDT 24 2087987259 ps
T851 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.88180222 Jun 24 05:43:54 PM PDT 24 Jun 24 05:44:08 PM PDT 24 4011982020 ps
T852 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1180091222 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:22 PM PDT 24 2011637429 ps
T853 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.820418392 Jun 24 05:44:25 PM PDT 24 Jun 24 05:44:32 PM PDT 24 2010225095 ps
T854 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.564055613 Jun 24 05:44:18 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2079943134 ps
T353 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3550516197 Jun 24 05:44:17 PM PDT 24 Jun 24 05:45:41 PM PDT 24 42433867307 ps
T855 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4149144559 Jun 24 05:44:01 PM PDT 24 Jun 24 05:44:11 PM PDT 24 6038300233 ps
T856 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2937123999 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:24 PM PDT 24 2072738516 ps
T857 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3997380737 Jun 24 05:43:53 PM PDT 24 Jun 24 05:45:36 PM PDT 24 42376791074 ps
T858 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1902316468 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:21 PM PDT 24 2114369201 ps
T859 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1979580855 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:14 PM PDT 24 2037122036 ps
T860 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1956721462 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2039763485 ps
T336 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.237316601 Jun 24 05:43:49 PM PDT 24 Jun 24 05:44:01 PM PDT 24 5239860408 ps
T861 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.197429677 Jun 24 05:44:08 PM PDT 24 Jun 24 05:44:14 PM PDT 24 2013155261 ps
T862 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3124567356 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:19 PM PDT 24 2254155138 ps
T863 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2034498251 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:10 PM PDT 24 3213822690 ps
T864 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.118308009 Jun 24 05:44:19 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2019525674 ps
T865 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2256037085 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:20 PM PDT 24 2062040793 ps
T866 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1944925463 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:23 PM PDT 24 2031726465 ps
T867 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2600418495 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:18 PM PDT 24 2238717848 ps
T868 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2222045548 Jun 24 05:44:24 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2044943181 ps
T869 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.4024969144 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:18 PM PDT 24 2327987851 ps
T870 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2019998384 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:42 PM PDT 24 9951408518 ps
T871 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4207285319 Jun 24 05:43:57 PM PDT 24 Jun 24 05:44:04 PM PDT 24 2010512564 ps
T872 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2422738571 Jun 24 05:44:05 PM PDT 24 Jun 24 05:44:22 PM PDT 24 7726705369 ps
T873 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2386383887 Jun 24 05:44:37 PM PDT 24 Jun 24 05:44:42 PM PDT 24 2042240904 ps
T874 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3598538992 Jun 24 05:44:29 PM PDT 24 Jun 24 05:44:33 PM PDT 24 2042518869 ps
T875 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2988428512 Jun 24 05:44:01 PM PDT 24 Jun 24 05:44:06 PM PDT 24 2234111658 ps
T876 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3141372480 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:13 PM PDT 24 2544848087 ps
T877 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3417420894 Jun 24 05:44:22 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2218809347 ps
T878 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.135059451 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:20 PM PDT 24 2125253531 ps
T879 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3801322074 Jun 24 05:44:23 PM PDT 24 Jun 24 05:44:26 PM PDT 24 2055635298 ps
T880 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2788081212 Jun 24 05:44:09 PM PDT 24 Jun 24 05:44:20 PM PDT 24 9026561570 ps
T881 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.88146024 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:15 PM PDT 24 3324905881 ps
T882 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1998923335 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:15 PM PDT 24 2069699987 ps
T883 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.603833108 Jun 24 05:44:16 PM PDT 24 Jun 24 05:44:25 PM PDT 24 2011787034 ps
T884 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3999445353 Jun 24 05:44:25 PM PDT 24 Jun 24 05:44:32 PM PDT 24 2010205710 ps
T885 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1049135621 Jun 24 05:44:28 PM PDT 24 Jun 24 05:44:36 PM PDT 24 2014673029 ps
T886 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1391496222 Jun 24 05:44:28 PM PDT 24 Jun 24 05:44:33 PM PDT 24 2021473641 ps
T887 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2811946459 Jun 24 05:43:47 PM PDT 24 Jun 24 05:45:10 PM PDT 24 68773803291 ps
T888 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2295012233 Jun 24 05:43:52 PM PDT 24 Jun 24 05:44:15 PM PDT 24 22370683806 ps
T889 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2936505499 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:25 PM PDT 24 8423126485 ps
T890 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.187211270 Jun 24 05:43:59 PM PDT 24 Jun 24 05:44:31 PM PDT 24 42949393276 ps
T891 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2666526613 Jun 24 05:44:29 PM PDT 24 Jun 24 05:45:01 PM PDT 24 42545723319 ps
T892 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1680369484 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:17 PM PDT 24 2105059786 ps
T893 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.841261754 Jun 24 05:44:09 PM PDT 24 Jun 24 05:44:13 PM PDT 24 2021735460 ps
T337 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1816659824 Jun 24 05:44:00 PM PDT 24 Jun 24 05:44:04 PM PDT 24 2078052091 ps
T894 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3985545122 Jun 24 05:43:52 PM PDT 24 Jun 24 05:44:24 PM PDT 24 42530611602 ps
T895 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1456026298 Jun 24 05:44:16 PM PDT 24 Jun 24 05:44:22 PM PDT 24 2077932917 ps
T896 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4186986223 Jun 24 05:44:31 PM PDT 24 Jun 24 05:44:37 PM PDT 24 2071934499 ps
T897 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4073793662 Jun 24 05:43:48 PM PDT 24 Jun 24 05:44:03 PM PDT 24 10927179462 ps
T898 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3339115090 Jun 24 05:44:27 PM PDT 24 Jun 24 05:44:34 PM PDT 24 2012526756 ps
T338 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2693879902 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2083798342 ps
T899 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3659803325 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2096133863 ps
T900 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.698895013 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:17 PM PDT 24 2065998431 ps
T901 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1057718199 Jun 24 05:43:56 PM PDT 24 Jun 24 05:43:59 PM PDT 24 2057469276 ps
T902 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1697184561 Jun 24 05:44:28 PM PDT 24 Jun 24 05:44:34 PM PDT 24 2061355926 ps
T903 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3947153254 Jun 24 05:43:52 PM PDT 24 Jun 24 05:44:02 PM PDT 24 2063905679 ps
T904 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3056778593 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:59 PM PDT 24 2117802850 ps
T905 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1975668648 Jun 24 05:44:08 PM PDT 24 Jun 24 05:44:13 PM PDT 24 2043171943 ps
T906 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.655285788 Jun 24 05:43:57 PM PDT 24 Jun 24 05:44:00 PM PDT 24 2039737529 ps
T907 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2981048866 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:16 PM PDT 24 2033529189 ps
T908 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2938015663 Jun 24 05:43:59 PM PDT 24 Jun 24 05:44:02 PM PDT 24 2036832301 ps
T909 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.792069787 Jun 24 05:43:56 PM PDT 24 Jun 24 05:43:59 PM PDT 24 2046165305 ps
T910 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3610805339 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:15 PM PDT 24 2087768716 ps
T911 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1816270729 Jun 24 05:44:14 PM PDT 24 Jun 24 05:44:37 PM PDT 24 42608998165 ps
T912 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2941020978 Jun 24 05:44:30 PM PDT 24 Jun 24 05:44:53 PM PDT 24 43513841784 ps
T913 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2356427951 Jun 24 05:43:59 PM PDT 24 Jun 24 05:44:05 PM PDT 24 2121541228 ps
T914 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1473748172 Jun 24 05:43:50 PM PDT 24 Jun 24 05:45:38 PM PDT 24 42474306560 ps

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.224613101
Short name T1
Test name
Test status
Simulation time 127491398975 ps
CPU time 165.66 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:37:37 PM PDT 24
Peak memory 201452 kb
Host smart-b8cfd05e-f2ec-4a38-b629-137c185d5107
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224613101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.224613101
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3569370720
Short name T12
Test name
Test status
Simulation time 65626354450 ps
CPU time 166.41 seconds
Started Jun 24 06:34:51 PM PDT 24
Finished Jun 24 06:37:38 PM PDT 24
Peak memory 209836 kb
Host smart-d1e65446-b8a6-4796-8b8e-0e1916036657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569370720 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3569370720
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.816463952
Short name T41
Test name
Test status
Simulation time 114165589230 ps
CPU time 71.28 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:35:24 PM PDT 24
Peak memory 218004 kb
Host smart-84fb4c2d-2a56-4b18-860e-dcf0f80dd4c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816463952 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.816463952
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2057395652
Short name T49
Test name
Test status
Simulation time 79898441801 ps
CPU time 198.29 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:38:31 PM PDT 24
Peak memory 201580 kb
Host smart-9f678f25-6ec6-43be-b26b-f546e726a04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057395652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.2057395652
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2300134060
Short name T15
Test name
Test status
Simulation time 2510024940 ps
CPU time 6.97 seconds
Started Jun 24 06:34:46 PM PDT 24
Finished Jun 24 06:34:54 PM PDT 24
Peak memory 201320 kb
Host smart-cb50152a-14b1-4654-a061-242a17bbb9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300134060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2300134060
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1241617710
Short name T123
Test name
Test status
Simulation time 242584995258 ps
CPU time 56.96 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:35:28 PM PDT 24
Peak memory 209912 kb
Host smart-ded857be-ea16-479a-b7e9-7e6d8c1f552e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241617710 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1241617710
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.439467742
Short name T279
Test name
Test status
Simulation time 42400768447 ps
CPU time 111.96 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:45:49 PM PDT 24
Peak memory 201240 kb
Host smart-90c76a30-91a9-428a-9e63-bf947d877a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439467742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.439467742
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1938547467
Short name T56
Test name
Test status
Simulation time 39366457540 ps
CPU time 48.16 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:33:19 PM PDT 24
Peak memory 201396 kb
Host smart-f834a208-b90d-48eb-b1e6-99acc0fba532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938547467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1938547467
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2650005189
Short name T47
Test name
Test status
Simulation time 35989775130 ps
CPU time 95.35 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:35:38 PM PDT 24
Peak memory 201600 kb
Host smart-64a9889b-a501-422c-af2a-f88bd0d697af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650005189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.2650005189
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1658132772
Short name T10
Test name
Test status
Simulation time 187953772765 ps
CPU time 106.34 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:34:38 PM PDT 24
Peak memory 213036 kb
Host smart-359afccf-cd89-43af-93ac-f9d122de96fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658132772 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.1658132772
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.700942255
Short name T151
Test name
Test status
Simulation time 34697894994 ps
CPU time 84.55 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:36:15 PM PDT 24
Peak memory 213764 kb
Host smart-5d00317a-6d26-4956-ad34-6e85de298fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700942255 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.700942255
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.481042502
Short name T146
Test name
Test status
Simulation time 512086357376 ps
CPU time 44.3 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 209680 kb
Host smart-8fcbd8dd-6420-49f3-af14-0343c1d2861a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481042502 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.481042502
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1512970481
Short name T92
Test name
Test status
Simulation time 141586285933 ps
CPU time 92.33 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:35:35 PM PDT 24
Peak memory 209804 kb
Host smart-087d0d1e-9133-4cd5-b013-dee3bf985600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512970481 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1512970481
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2576815827
Short name T188
Test name
Test status
Simulation time 57677332299 ps
CPU time 62.16 seconds
Started Jun 24 06:34:23 PM PDT 24
Finished Jun 24 06:35:29 PM PDT 24
Peak memory 209840 kb
Host smart-9d5a4369-7314-4c7f-9dd4-1df53076f707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576815827 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2576815827
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2038479805
Short name T276
Test name
Test status
Simulation time 42108387587 ps
CPU time 50.26 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:33:26 PM PDT 24
Peak memory 220804 kb
Host smart-04e1a9e2-5420-4103-a2dd-9703b55b055f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038479805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2038479805
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1947275295
Short name T91
Test name
Test status
Simulation time 5591213142 ps
CPU time 2.27 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:33:04 PM PDT 24
Peak memory 201372 kb
Host smart-67c28e69-b494-4cc2-91cf-be1882fb7001
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947275295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.1947275295
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1801390890
Short name T88
Test name
Test status
Simulation time 340984190109 ps
CPU time 109.73 seconds
Started Jun 24 06:34:33 PM PDT 24
Finished Jun 24 06:36:24 PM PDT 24
Peak memory 217664 kb
Host smart-6a5e4b25-e2ff-4e2c-a556-55e8710c7282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801390890 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.1801390890
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1286390327
Short name T242
Test name
Test status
Simulation time 37936075981 ps
CPU time 73.31 seconds
Started Jun 24 06:35:17 PM PDT 24
Finished Jun 24 06:36:34 PM PDT 24
Peak memory 201760 kb
Host smart-0941796d-7491-49b1-a750-44827fe51bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286390327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.1286390327
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3958101975
Short name T148
Test name
Test status
Simulation time 5160157469 ps
CPU time 11.31 seconds
Started Jun 24 06:34:23 PM PDT 24
Finished Jun 24 06:34:39 PM PDT 24
Peak memory 201268 kb
Host smart-685c0833-12b0-4138-ac98-8f8bc9fde6b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958101975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3958101975
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2425859035
Short name T28
Test name
Test status
Simulation time 2050591979 ps
CPU time 3.3 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:17 PM PDT 24
Peak memory 201028 kb
Host smart-1397c529-1ff5-4084-89d3-2980f17a12d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425859035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2425859035
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1849707146
Short name T111
Test name
Test status
Simulation time 115127305559 ps
CPU time 95.46 seconds
Started Jun 24 06:33:15 PM PDT 24
Finished Jun 24 06:34:51 PM PDT 24
Peak memory 201560 kb
Host smart-c081c66f-2a6b-4a53-babc-30e872043d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849707146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1849707146
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2815646842
Short name T3
Test name
Test status
Simulation time 3930764812 ps
CPU time 3 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201228 kb
Host smart-0519f37b-28f6-46e0-b173-94d0f2dbffd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815646842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.2815646842
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3830509982
Short name T247
Test name
Test status
Simulation time 66049796156 ps
CPU time 80.15 seconds
Started Jun 24 06:35:01 PM PDT 24
Finished Jun 24 06:36:22 PM PDT 24
Peak memory 201636 kb
Host smart-7399df92-bb1a-4925-83d3-c988d378d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830509982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.3830509982
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3422945185
Short name T288
Test name
Test status
Simulation time 2328770663 ps
CPU time 4.44 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 209436 kb
Host smart-e7c554cf-5b13-4bb0-a939-dc3a83317779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422945185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3422945185
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2982276063
Short name T114
Test name
Test status
Simulation time 107349020517 ps
CPU time 269.41 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:37:53 PM PDT 24
Peak memory 201792 kb
Host smart-f4cf352d-5bb3-47a6-81c9-a3f976a6e09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982276063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2982276063
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3713016803
Short name T153
Test name
Test status
Simulation time 3759692020 ps
CPU time 2.42 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201236 kb
Host smart-94d12f6e-6d4e-450f-9548-73dc9dec9770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713016803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.3713016803
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3136655658
Short name T152
Test name
Test status
Simulation time 73533415738 ps
CPU time 53.05 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:35:19 PM PDT 24
Peak memory 209816 kb
Host smart-17542cb3-0f74-4432-81e1-85ea777c703a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136655658 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3136655658
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.809791662
Short name T145
Test name
Test status
Simulation time 4379382027 ps
CPU time 11.48 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:22 PM PDT 24
Peak memory 201216 kb
Host smart-0139d1a8-f384-4750-821e-0c0162cfe315
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809791662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.809791662
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3570375605
Short name T161
Test name
Test status
Simulation time 23434975284 ps
CPU time 57.72 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:34:31 PM PDT 24
Peak memory 209808 kb
Host smart-fd28b983-0bc8-444a-a139-f499b56b54e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570375605 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3570375605
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1923016383
Short name T38
Test name
Test status
Simulation time 5740851313 ps
CPU time 3.57 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:18 PM PDT 24
Peak memory 201200 kb
Host smart-b9e8c154-d237-469f-9360-4f3b7064ef02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923016383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1923016383
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2429864714
Short name T264
Test name
Test status
Simulation time 110318635698 ps
CPU time 290.39 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:39:29 PM PDT 24
Peak memory 201528 kb
Host smart-048959bd-cf96-40de-a1c0-1108be6d5524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429864714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2429864714
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3823710560
Short name T39
Test name
Test status
Simulation time 64662296892 ps
CPU time 74.83 seconds
Started Jun 24 06:32:56 PM PDT 24
Finished Jun 24 06:34:14 PM PDT 24
Peak memory 209860 kb
Host smart-5ac6ef04-687e-4217-a3ca-a4462d343330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823710560 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3823710560
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.4038112187
Short name T109
Test name
Test status
Simulation time 166356798265 ps
CPU time 95.44 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:34:59 PM PDT 24
Peak memory 217940 kb
Host smart-699e0419-3feb-4ff5-bb84-479fc059d5b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038112187 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.4038112187
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.4078408505
Short name T359
Test name
Test status
Simulation time 108369543621 ps
CPU time 114.65 seconds
Started Jun 24 06:33:31 PM PDT 24
Finished Jun 24 06:35:27 PM PDT 24
Peak memory 201580 kb
Host smart-01f05aa3-a524-4508-8e52-cdab57674063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078408505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.4078408505
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1221523625
Short name T392
Test name
Test status
Simulation time 2033478953 ps
CPU time 1.99 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201440 kb
Host smart-ad6acc42-d769-4427-8f5d-7d8bfd389bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221523625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1221523625
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1465061275
Short name T218
Test name
Test status
Simulation time 107882552965 ps
CPU time 287.11 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:37:40 PM PDT 24
Peak memory 201492 kb
Host smart-da951ace-a156-4844-863f-03c4dde14c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465061275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1465061275
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2365858160
Short name T85
Test name
Test status
Simulation time 76614749025 ps
CPU time 28.8 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:48 PM PDT 24
Peak memory 201516 kb
Host smart-ad25c76a-681f-4827-8160-69a4cdca0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365858160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.2365858160
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1549687704
Short name T35
Test name
Test status
Simulation time 95465521279 ps
CPU time 64.01 seconds
Started Jun 24 06:34:58 PM PDT 24
Finished Jun 24 06:36:03 PM PDT 24
Peak memory 201440 kb
Host smart-4289c597-1c7f-49d6-a7f6-4d177f18ad9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549687704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1549687704
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2186393421
Short name T252
Test name
Test status
Simulation time 155154798351 ps
CPU time 289.57 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:37:41 PM PDT 24
Peak memory 201576 kb
Host smart-9eddd417-4e6e-43f7-8bd6-f82c0e1a0776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186393421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2186393421
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3560986534
Short name T361
Test name
Test status
Simulation time 36540287432 ps
CPU time 28.44 seconds
Started Jun 24 06:33:11 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201508 kb
Host smart-feaec4a3-ad86-40ae-8238-ec8deda61d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560986534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.3560986534
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3573987835
Short name T347
Test name
Test status
Simulation time 106499337228 ps
CPU time 261.47 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:38:46 PM PDT 24
Peak memory 201536 kb
Host smart-80103a51-d0b4-482b-a3eb-218fa26ba078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573987835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.3573987835
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1276263522
Short name T329
Test name
Test status
Simulation time 50889391507 ps
CPU time 135.68 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:46:04 PM PDT 24
Peak memory 201268 kb
Host smart-07da244e-bcc0-425c-9036-3c0cf6d5ed5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276263522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.1276263522
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1979580855
Short name T859
Test name
Test status
Simulation time 2037122036 ps
CPU time 7.21 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:14 PM PDT 24
Peak memory 201424 kb
Host smart-8e47c434-d20a-4c54-8e42-b7626ec3fa1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979580855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1979580855
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4155651736
Short name T81
Test name
Test status
Simulation time 1519243319774 ps
CPU time 193.18 seconds
Started Jun 24 06:33:17 PM PDT 24
Finished Jun 24 06:36:32 PM PDT 24
Peak memory 210000 kb
Host smart-4ee62ceb-4b91-4b05-a735-cea43f83de6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155651736 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.4155651736
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.1330835431
Short name T105
Test name
Test status
Simulation time 70933213539 ps
CPU time 46.08 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201512 kb
Host smart-ad9ae611-8c0c-4fa5-9572-4c0ecff3070b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330835431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.1330835431
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2559986300
Short name T358
Test name
Test status
Simulation time 65948440001 ps
CPU time 44.43 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:35:59 PM PDT 24
Peak memory 201724 kb
Host smart-e0850739-a097-4565-81c6-2a4cd90434ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559986300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.2559986300
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3311651541
Short name T82
Test name
Test status
Simulation time 37596221888 ps
CPU time 90.94 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:34:25 PM PDT 24
Peak memory 201516 kb
Host smart-4cd5c203-8d54-4048-9ee3-6d16425eda91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311651541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3311651541
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4273647802
Short name T349
Test name
Test status
Simulation time 142660170223 ps
CPU time 101.03 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:36:56 PM PDT 24
Peak memory 201516 kb
Host smart-6ea959d2-ce9f-44b7-823f-dfd54ef9cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273647802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.4273647802
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4120236892
Short name T57
Test name
Test status
Simulation time 42383026626 ps
CPU time 52.92 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:33:10 PM PDT 24
Peak memory 201376 kb
Host smart-b74d3966-06af-4b5b-9bbf-9cded23e5fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120236892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4120236892
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3329586012
Short name T102
Test name
Test status
Simulation time 55446020881 ps
CPU time 8.49 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:40 PM PDT 24
Peak memory 201608 kb
Host smart-8f94d905-e06e-4150-9645-81abcb78eb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329586012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3329586012
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.816292868
Short name T280
Test name
Test status
Simulation time 24326873798 ps
CPU time 5.17 seconds
Started Jun 24 05:44:21 PM PDT 24
Finished Jun 24 05:44:27 PM PDT 24
Peak memory 201256 kb
Host smart-588a1b08-66a5-4c3a-b4e2-44d63f99c4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816292868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_tl_intg_err.816292868
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.3105679804
Short name T365
Test name
Test status
Simulation time 174268106251 ps
CPU time 221.94 seconds
Started Jun 24 06:32:57 PM PDT 24
Finished Jun 24 06:36:41 PM PDT 24
Peak memory 201568 kb
Host smart-1d39ce08-2e4f-4222-8799-7aa626fd2900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105679804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.3105679804
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.638248060
Short name T765
Test name
Test status
Simulation time 543656245531 ps
CPU time 67.98 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:34:30 PM PDT 24
Peak memory 209716 kb
Host smart-71d4e9ff-089b-48fe-9ac4-c8f5b4e015c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638248060 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.638248060
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1211099985
Short name T602
Test name
Test status
Simulation time 92034023411 ps
CPU time 218.3 seconds
Started Jun 24 06:33:23 PM PDT 24
Finished Jun 24 06:37:02 PM PDT 24
Peak memory 201572 kb
Host smart-ec8eb59a-9eb3-4cd9-b9ef-01d6d7268d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211099985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1211099985
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2581566284
Short name T230
Test name
Test status
Simulation time 113722120213 ps
CPU time 67.46 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201628 kb
Host smart-e0ba1f6b-438a-4632-8705-b0c72be00c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581566284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2581566284
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2126243308
Short name T322
Test name
Test status
Simulation time 73525844582 ps
CPU time 91.05 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 209880 kb
Host smart-5c16a314-32de-4740-8cc8-bc98c25928c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126243308 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2126243308
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2831605572
Short name T325
Test name
Test status
Simulation time 225890603105 ps
CPU time 296.59 seconds
Started Jun 24 06:34:00 PM PDT 24
Finished Jun 24 06:38:58 PM PDT 24
Peak memory 209824 kb
Host smart-48b3340a-a5a6-4f18-a11e-3f723d29fe7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831605572 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.2831605572
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.654208771
Short name T199
Test name
Test status
Simulation time 153744540257 ps
CPU time 328.38 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:39:54 PM PDT 24
Peak memory 201524 kb
Host smart-d1921d65-59dc-475a-8792-9dbe6c99630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654208771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.654208771
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.153780765
Short name T362
Test name
Test status
Simulation time 150270315454 ps
CPU time 389.96 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:41:09 PM PDT 24
Peak memory 201520 kb
Host smart-a5e9e741-65ec-4925-9960-be484e78e5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153780765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.153780765
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4132854001
Short name T372
Test name
Test status
Simulation time 589377325831 ps
CPU time 107.66 seconds
Started Jun 24 06:34:58 PM PDT 24
Finished Jun 24 06:36:46 PM PDT 24
Peak memory 201236 kb
Host smart-b15ce936-b0d6-4967-a87a-de434b70892e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132854001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.4132854001
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2424821597
Short name T356
Test name
Test status
Simulation time 84705940686 ps
CPU time 73.65 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:36:29 PM PDT 24
Peak memory 201572 kb
Host smart-d092fa8d-e977-4aff-9e8c-8ddcdf676423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424821597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2424821597
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2757478174
Short name T344
Test name
Test status
Simulation time 182306512672 ps
CPU time 112.31 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:37:06 PM PDT 24
Peak memory 201504 kb
Host smart-193d99c2-7d66-498c-b218-73715b222ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757478174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.2757478174
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2069196987
Short name T369
Test name
Test status
Simulation time 50302496346 ps
CPU time 128.47 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:37:27 PM PDT 24
Peak memory 201608 kb
Host smart-ebc537a5-0fef-43e9-afb3-95d7e15d9461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069196987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.2069196987
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3957240066
Short name T363
Test name
Test status
Simulation time 95292333663 ps
CPU time 66.2 seconds
Started Jun 24 06:32:44 PM PDT 24
Finished Jun 24 06:33:52 PM PDT 24
Peak memory 201536 kb
Host smart-d8c42418-2021-41a8-b56f-107d53790668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957240066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.3957240066
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3700336803
Short name T265
Test name
Test status
Simulation time 58373602450 ps
CPU time 37.64 seconds
Started Jun 24 06:35:14 PM PDT 24
Finished Jun 24 06:35:54 PM PDT 24
Peak memory 201576 kb
Host smart-28e64a06-e0ab-414c-861b-9bc2af22ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700336803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.3700336803
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.339816107
Short name T268
Test name
Test status
Simulation time 154286103714 ps
CPU time 96.8 seconds
Started Jun 24 06:35:17 PM PDT 24
Finished Jun 24 06:36:57 PM PDT 24
Peak memory 201728 kb
Host smart-adf857ea-5cc1-458a-b2ba-e4f177f5150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339816107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi
th_pre_cond.339816107
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1737780262
Short name T26
Test name
Test status
Simulation time 5441821784 ps
CPU time 4.89 seconds
Started Jun 24 05:44:17 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201460 kb
Host smart-655d6b43-5575-4417-957a-77c672ba415f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737780262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1737780262
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1747640585
Short name T328
Test name
Test status
Simulation time 2278832815 ps
CPU time 5.19 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:44:00 PM PDT 24
Peak memory 201028 kb
Host smart-a8869b7b-2eef-4599-9434-2152682419d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747640585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1747640585
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.164154088
Short name T839
Test name
Test status
Simulation time 6272389281 ps
CPU time 1.83 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:12 PM PDT 24
Peak memory 201100 kb
Host smart-ed823b38-373c-4ac2-b2cc-88c00c8c3872
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164154088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_hw_reset.164154088
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.139299917
Short name T285
Test name
Test status
Simulation time 2095764843 ps
CPU time 2.92 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 200948 kb
Host smart-45c8125c-8a8a-4c7f-9523-e64b40b1d9be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139299917 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.139299917
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1816659824
Short name T337
Test name
Test status
Simulation time 2078052091 ps
CPU time 2.36 seconds
Started Jun 24 05:44:00 PM PDT 24
Finished Jun 24 05:44:04 PM PDT 24
Peak memory 200924 kb
Host smart-39369d2c-8196-4629-802d-135e127d2013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816659824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1816659824
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1468199952
Short name T819
Test name
Test status
Simulation time 2015684047 ps
CPU time 5.96 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 200588 kb
Host smart-24d5e497-9ab5-44d6-8ec7-ccb9ec602310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468199952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1468199952
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2963253396
Short name T828
Test name
Test status
Simulation time 9949814873 ps
CPU time 7.7 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201268 kb
Host smart-3098e8a6-71dd-41b5-8520-85d3ff607924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963253396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2963253396
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3905421717
Short name T849
Test name
Test status
Simulation time 2038447254 ps
CPU time 5.77 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 200996 kb
Host smart-aa92ce9b-4b30-40b0-a775-15c6cf629802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905421717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3905421717
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.125633818
Short name T351
Test name
Test status
Simulation time 22238319971 ps
CPU time 23.31 seconds
Started Jun 24 05:43:54 PM PDT 24
Finished Jun 24 05:44:20 PM PDT 24
Peak memory 201244 kb
Host smart-9a6abe2a-5569-4d50-bc8b-98b4585f1fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125633818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.125633818
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3141372480
Short name T876
Test name
Test status
Simulation time 2544848087 ps
CPU time 5.57 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 201284 kb
Host smart-df514fdb-30dd-45b4-83c0-98b8879f33b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141372480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3141372480
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.237316601
Short name T336
Test name
Test status
Simulation time 5239860408 ps
CPU time 7.37 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:44:01 PM PDT 24
Peak memory 201272 kb
Host smart-494a4855-bb0c-4e48-a96d-0297d7c2f63b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237316601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.237316601
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3333521708
Short name T32
Test name
Test status
Simulation time 4055017804 ps
CPU time 3.11 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:18 PM PDT 24
Peak memory 200984 kb
Host smart-72a2eb9f-0606-4f76-b635-43f360cc7cf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333521708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3333521708
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2937123999
Short name T856
Test name
Test status
Simulation time 2072738516 ps
CPU time 6.49 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201028 kb
Host smart-ba474dd3-5a4f-49dd-984d-a49079474f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937123999 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2937123999
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1057718199
Short name T901
Test name
Test status
Simulation time 2057469276 ps
CPU time 1.53 seconds
Started Jun 24 05:43:56 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 201180 kb
Host smart-1b4628ac-cc04-49c6-8dd2-0ac354883072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057718199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.1057718199
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3507466866
Short name T814
Test name
Test status
Simulation time 2028811044 ps
CPU time 2.41 seconds
Started Jun 24 05:44:07 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 200860 kb
Host smart-9aff8c67-fecc-42af-9925-e346f7be2b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507466866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.3507466866
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4073793662
Short name T897
Test name
Test status
Simulation time 10927179462 ps
CPU time 10.14 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:44:03 PM PDT 24
Peak memory 201220 kb
Host smart-71bceebb-b0a3-42c7-9b5e-b7427e0e2ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073793662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.4073793662
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2988428512
Short name T875
Test name
Test status
Simulation time 2234111658 ps
CPU time 2.92 seconds
Started Jun 24 05:44:01 PM PDT 24
Finished Jun 24 05:44:06 PM PDT 24
Peak memory 201328 kb
Host smart-fe9ccfb7-8ce1-4dbe-a02d-4670086a4be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988428512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2988428512
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3985545122
Short name T894
Test name
Test status
Simulation time 42530611602 ps
CPU time 27.81 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201252 kb
Host smart-0184204e-766f-4c27-ba5b-218e433e4251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985545122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.3985545122
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1556893630
Short name T283
Test name
Test status
Simulation time 2130698815 ps
CPU time 2.32 seconds
Started Jun 24 05:43:58 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 200996 kb
Host smart-579f3b4c-5b42-4bbd-875f-69f74f9b6649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556893630 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1556893630
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.64978536
Short name T330
Test name
Test status
Simulation time 2042620189 ps
CPU time 4.28 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:44:00 PM PDT 24
Peak memory 200988 kb
Host smart-6e80986c-cb53-4ebc-b68a-e2a83d56351f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64978536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw
.64978536
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.698895013
Short name T900
Test name
Test status
Simulation time 2065998431 ps
CPU time 1.26 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:17 PM PDT 24
Peak memory 200644 kb
Host smart-31d785d3-2114-477b-8147-a3602eea17a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698895013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_tes
t.698895013
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2019998384
Short name T870
Test name
Test status
Simulation time 9951408518 ps
CPU time 25.11 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:42 PM PDT 24
Peak memory 201264 kb
Host smart-fb082d63-c187-449b-8f99-2802a4c70352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019998384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2019998384
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.155125806
Short name T282
Test name
Test status
Simulation time 2495154151 ps
CPU time 2.2 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:09 PM PDT 24
Peak memory 201248 kb
Host smart-ef465061-d713-4a56-acaa-4425e27663c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155125806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.155125806
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1793782929
Short name T292
Test name
Test status
Simulation time 22277802273 ps
CPU time 16.43 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:27 PM PDT 24
Peak memory 201248 kb
Host smart-f478bb08-d94c-4516-9c46-49f6ee0ec0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793782929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1793782929
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1680369484
Short name T892
Test name
Test status
Simulation time 2105059786 ps
CPU time 3.53 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:17 PM PDT 24
Peak memory 200996 kb
Host smart-eadb37e0-31a8-46f0-9f3d-a98b07fcabb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680369484 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1680369484
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1697184561
Short name T902
Test name
Test status
Simulation time 2061355926 ps
CPU time 4.86 seconds
Started Jun 24 05:44:28 PM PDT 24
Finished Jun 24 05:44:34 PM PDT 24
Peak memory 201036 kb
Host smart-0ac2e15e-539b-440d-8714-6c01cb0657b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697184561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1697184561
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4291064336
Short name T830
Test name
Test status
Simulation time 2024757393 ps
CPU time 3.31 seconds
Started Jun 24 05:44:21 PM PDT 24
Finished Jun 24 05:44:25 PM PDT 24
Peak memory 200644 kb
Host smart-6e0f9610-2fbe-4af6-909f-77430452e59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291064336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.4291064336
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.88146024
Short name T881
Test name
Test status
Simulation time 3324905881 ps
CPU time 3.15 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 209400 kb
Host smart-39b4e519-abb1-4b2f-ba16-90dc0cd59fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88146024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors
.88146024
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3116022562
Short name T827
Test name
Test status
Simulation time 22198432727 ps
CPU time 61.86 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:45:16 PM PDT 24
Peak memory 201304 kb
Host smart-243f3026-b289-4ea0-8a44-bb5da764eecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116022562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3116022562
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1456026298
Short name T895
Test name
Test status
Simulation time 2077932917 ps
CPU time 3.62 seconds
Started Jun 24 05:44:16 PM PDT 24
Finished Jun 24 05:44:22 PM PDT 24
Peak memory 200948 kb
Host smart-8cd3709d-0674-46ad-b7f4-1b82cfb927b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456026298 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1456026298
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3659803325
Short name T899
Test name
Test status
Simulation time 2096133863 ps
CPU time 2.29 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 200940 kb
Host smart-8ae5b333-867e-402a-9157-3b10c9f86559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659803325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.3659803325
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3026674030
Short name T801
Test name
Test status
Simulation time 2015837691 ps
CPU time 3.06 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 200672 kb
Host smart-5a1a46db-ba03-4de5-ba24-c7252e62f21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026674030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3026674030
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2788081212
Short name T880
Test name
Test status
Simulation time 9026561570 ps
CPU time 9.62 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:20 PM PDT 24
Peak memory 201300 kb
Host smart-ffd6a0a6-e6ea-4336-b2d2-c96561e559a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788081212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2788081212
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.283693995
Short name T841
Test name
Test status
Simulation time 2218996193 ps
CPU time 4.88 seconds
Started Jun 24 05:44:18 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201184 kb
Host smart-45b6bc5a-4ca0-4ca3-be5c-5eff2bd80689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283693995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.283693995
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1930448281
Short name T844
Test name
Test status
Simulation time 43297698669 ps
CPU time 9.18 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:27 PM PDT 24
Peak memory 201260 kb
Host smart-a03d0c42-d364-460f-80e5-695c66cc8882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930448281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.1930448281
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3005495255
Short name T820
Test name
Test status
Simulation time 2356596149 ps
CPU time 1.75 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 201120 kb
Host smart-67f0bc48-3126-4caf-8c3f-a9e4d7343e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005495255 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3005495255
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1944925463
Short name T866
Test name
Test status
Simulation time 2031726465 ps
CPU time 5.9 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:23 PM PDT 24
Peak memory 200984 kb
Host smart-7c3d8fe5-370f-4d54-ad98-8ff7ee232eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944925463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.1944925463
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4203646780
Short name T825
Test name
Test status
Simulation time 2009660002 ps
CPU time 5.38 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:11 PM PDT 24
Peak memory 200644 kb
Host smart-89c95392-06b8-4e12-8616-68125b11496b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203646780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.4203646780
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2032240647
Short name T823
Test name
Test status
Simulation time 4156898547 ps
CPU time 3.69 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:20 PM PDT 24
Peak memory 201284 kb
Host smart-3114ea97-12d2-4c81-a80e-4ff45cd9f9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032240647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2032240647
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.135059451
Short name T878
Test name
Test status
Simulation time 2125253531 ps
CPU time 3.43 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:20 PM PDT 24
Peak memory 201124 kb
Host smart-052d091f-4d92-4926-b7e2-448d49ab33c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135059451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.135059451
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4104640060
Short name T33
Test name
Test status
Simulation time 22174795720 ps
CPU time 55.82 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:45:07 PM PDT 24
Peak memory 201252 kb
Host smart-4cc42e61-2fea-4a3b-a178-80deaca8b47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104640060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.4104640060
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.926653360
Short name T284
Test name
Test status
Simulation time 2118791531 ps
CPU time 1.57 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 201092 kb
Host smart-e69298a7-8222-4cbf-8d97-476b93590824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926653360 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.926653360
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4155248395
Short name T848
Test name
Test status
Simulation time 2054407830 ps
CPU time 2.12 seconds
Started Jun 24 05:44:20 PM PDT 24
Finished Jun 24 05:44:23 PM PDT 24
Peak memory 200936 kb
Host smart-30454882-d481-4ac7-8c48-6b3a670cdc7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155248395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.4155248395
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.792069787
Short name T909
Test name
Test status
Simulation time 2046165305 ps
CPU time 1.46 seconds
Started Jun 24 05:43:56 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 200668 kb
Host smart-dbe9f7e7-56d1-478b-8c58-f1385c9acf89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792069787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_tes
t.792069787
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.521654580
Short name T342
Test name
Test status
Simulation time 8914544364 ps
CPU time 41.46 seconds
Started Jun 24 05:44:00 PM PDT 24
Finished Jun 24 05:44:43 PM PDT 24
Peak memory 201292 kb
Host smart-16105073-49ec-4f07-af5b-383a7eebfea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521654580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.521654580
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1902961978
Short name T352
Test name
Test status
Simulation time 22225287796 ps
CPU time 59.9 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:45:11 PM PDT 24
Peak memory 201512 kb
Host smart-809117c1-d555-44b4-963f-dba65d1786d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902961978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1902961978
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3124567356
Short name T862
Test name
Test status
Simulation time 2254155138 ps
CPU time 1.16 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:19 PM PDT 24
Peak memory 201060 kb
Host smart-d6350c80-5544-40c5-96b7-13a3007d0322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124567356 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3124567356
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3947153254
Short name T903
Test name
Test status
Simulation time 2063905679 ps
CPU time 6.06 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 201032 kb
Host smart-802ad37f-eb08-46ef-b57c-4b4afab39808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947153254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.3947153254
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1956721462
Short name T860
Test name
Test status
Simulation time 2039763485 ps
CPU time 1.88 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 200644 kb
Host smart-e04b7d22-26d7-4db6-834e-0d70be4bf564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956721462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.1956721462
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2422738571
Short name T872
Test name
Test status
Simulation time 7726705369 ps
CPU time 15.69 seconds
Started Jun 24 05:44:05 PM PDT 24
Finished Jun 24 05:44:22 PM PDT 24
Peak memory 201536 kb
Host smart-0f92ec9c-dc72-42ac-a6e1-3ee3184acfb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422738571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2422738571
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.4024969144
Short name T869
Test name
Test status
Simulation time 2327987851 ps
CPU time 2.54 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:18 PM PDT 24
Peak memory 201152 kb
Host smart-120c726a-07de-469d-b542-9a2fb844f875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024969144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.4024969144
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4186986223
Short name T896
Test name
Test status
Simulation time 2071934499 ps
CPU time 3.22 seconds
Started Jun 24 05:44:31 PM PDT 24
Finished Jun 24 05:44:37 PM PDT 24
Peak memory 201000 kb
Host smart-3b2a5f3e-ec40-41a4-bcd4-66b69d327ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186986223 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4186986223
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2386383887
Short name T873
Test name
Test status
Simulation time 2042240904 ps
CPU time 2.21 seconds
Started Jun 24 05:44:37 PM PDT 24
Finished Jun 24 05:44:42 PM PDT 24
Peak memory 200940 kb
Host smart-730e1c0b-f3c5-4df9-9461-f9f1686b470f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386383887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2386383887
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2023359003
Short name T850
Test name
Test status
Simulation time 2087987259 ps
CPU time 1.04 seconds
Started Jun 24 05:44:07 PM PDT 24
Finished Jun 24 05:44:09 PM PDT 24
Peak memory 200616 kb
Host smart-5e375a54-b526-4242-8ace-3a29073a072b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023359003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2023359003
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1089790565
Short name T286
Test name
Test status
Simulation time 5019653091 ps
CPU time 5.09 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 201252 kb
Host smart-605829a4-cac0-4978-9c7a-8f162470af68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089790565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.1089790565
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2424431734
Short name T832
Test name
Test status
Simulation time 2145158946 ps
CPU time 3.45 seconds
Started Jun 24 05:44:29 PM PDT 24
Finished Jun 24 05:44:35 PM PDT 24
Peak memory 201116 kb
Host smart-9acf9ea0-0433-44e6-983f-07c02c266507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424431734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2424431734
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.991801635
Short name T824
Test name
Test status
Simulation time 22180689657 ps
CPU time 60.74 seconds
Started Jun 24 05:44:22 PM PDT 24
Finished Jun 24 05:45:24 PM PDT 24
Peak memory 201252 kb
Host smart-6658836e-949b-4c8a-89fe-2912c9176b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991801635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_tl_intg_err.991801635
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3417420894
Short name T877
Test name
Test status
Simulation time 2218809347 ps
CPU time 2.51 seconds
Started Jun 24 05:44:22 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 201140 kb
Host smart-7a00e646-845d-45f6-a1fe-426aeace66b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417420894 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3417420894
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.118308009
Short name T864
Test name
Test status
Simulation time 2019525674 ps
CPU time 5.68 seconds
Started Jun 24 05:44:19 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 200612 kb
Host smart-2348777f-26e3-4610-90b9-cd231c89872b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118308009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.118308009
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1708244568
Short name T27
Test name
Test status
Simulation time 4534291247 ps
CPU time 11.66 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:30 PM PDT 24
Peak memory 201208 kb
Host smart-6b20a8b5-53c8-46b2-8137-406c41915928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708244568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1708244568
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.880901575
Short name T291
Test name
Test status
Simulation time 2060263641 ps
CPU time 6.26 seconds
Started Jun 24 05:44:28 PM PDT 24
Finished Jun 24 05:44:37 PM PDT 24
Peak memory 201088 kb
Host smart-33c86167-ae61-45c0-9e6d-c41ca6eccb6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880901575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.880901575
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3550516197
Short name T353
Test name
Test status
Simulation time 42433867307 ps
CPU time 81.79 seconds
Started Jun 24 05:44:17 PM PDT 24
Finished Jun 24 05:45:41 PM PDT 24
Peak memory 201252 kb
Host smart-888690d1-79b0-4316-a1c4-3e09eade4e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550516197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3550516197
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.564055613
Short name T854
Test name
Test status
Simulation time 2079943134 ps
CPU time 6.06 seconds
Started Jun 24 05:44:18 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 201000 kb
Host smart-146566a1-cbe4-45ff-b810-3a5f2f685795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564055613 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.564055613
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2256037085
Short name T865
Test name
Test status
Simulation time 2062040793 ps
CPU time 2.43 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:20 PM PDT 24
Peak memory 201036 kb
Host smart-904adb9a-f1ff-4324-92de-a9fcf3a1d33b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256037085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2256037085
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2532694603
Short name T798
Test name
Test status
Simulation time 2013785579 ps
CPU time 3.14 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 200652 kb
Host smart-e315e545-2192-40f1-8c51-ec057718025c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532694603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2532694603
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2936505499
Short name T889
Test name
Test status
Simulation time 8423126485 ps
CPU time 10 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:25 PM PDT 24
Peak memory 201192 kb
Host smart-28a2413d-4eb5-4a30-a059-730c751f2f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936505499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2936505499
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3244307680
Short name T290
Test name
Test status
Simulation time 2038019608 ps
CPU time 3.57 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 201052 kb
Host smart-de7914ed-0129-4dd1-ae12-39265046debd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244307680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3244307680
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2941020978
Short name T912
Test name
Test status
Simulation time 43513841784 ps
CPU time 20.04 seconds
Started Jun 24 05:44:30 PM PDT 24
Finished Jun 24 05:44:53 PM PDT 24
Peak memory 201304 kb
Host smart-fccf7444-c30f-41c7-9ec2-343e5c9d9213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941020978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.2941020978
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2600418495
Short name T867
Test name
Test status
Simulation time 2238717848 ps
CPU time 2.66 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:18 PM PDT 24
Peak memory 201044 kb
Host smart-612d724c-9819-48ac-bd61-801088aefbd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600418495 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2600418495
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1975668648
Short name T905
Test name
Test status
Simulation time 2043171943 ps
CPU time 3.16 seconds
Started Jun 24 05:44:08 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 200932 kb
Host smart-edd532e1-f199-47bc-b38f-c3ed745b63f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975668648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1975668648
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2636567605
Short name T838
Test name
Test status
Simulation time 2046264830 ps
CPU time 1.88 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:19 PM PDT 24
Peak memory 200640 kb
Host smart-18663584-8982-4127-a626-ac53038f0ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636567605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2636567605
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.770638697
Short name T842
Test name
Test status
Simulation time 9482872490 ps
CPU time 22.93 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:44:34 PM PDT 24
Peak memory 201160 kb
Host smart-20845c02-67d7-491e-92f0-0d3dccc9c72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770638697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.sysrst_ctrl_same_csr_outstanding.770638697
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3430865817
Short name T833
Test name
Test status
Simulation time 2096239199 ps
CPU time 2.92 seconds
Started Jun 24 05:44:29 PM PDT 24
Finished Jun 24 05:44:35 PM PDT 24
Peak memory 201108 kb
Host smart-c5bef9c2-1cac-42ab-9d6e-9d07ba31b17b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430865817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3430865817
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2666526613
Short name T891
Test name
Test status
Simulation time 42545723319 ps
CPU time 28.8 seconds
Started Jun 24 05:44:29 PM PDT 24
Finished Jun 24 05:45:01 PM PDT 24
Peak memory 201284 kb
Host smart-74412d09-908b-4c2a-8b52-d0ccd434e95a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666526613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2666526613
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3390154266
Short name T335
Test name
Test status
Simulation time 2925820692 ps
CPU time 5.6 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:44:01 PM PDT 24
Peak memory 201540 kb
Host smart-a9288415-3dd1-48b2-9bf4-f7bc7631992e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390154266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3390154266
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.514921887
Short name T331
Test name
Test status
Simulation time 73396553386 ps
CPU time 317.89 seconds
Started Jun 24 05:43:57 PM PDT 24
Finished Jun 24 05:49:16 PM PDT 24
Peak memory 201028 kb
Host smart-1093a509-52aa-4a4d-9a1a-497458171d92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514921887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.514921887
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4149144559
Short name T855
Test name
Test status
Simulation time 6038300233 ps
CPU time 8.19 seconds
Started Jun 24 05:44:01 PM PDT 24
Finished Jun 24 05:44:11 PM PDT 24
Peak memory 201160 kb
Host smart-786d9a46-20f3-4609-905c-01b5eedb5c9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149144559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.4149144559
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1539803294
Short name T294
Test name
Test status
Simulation time 2084931785 ps
CPU time 3.99 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 200980 kb
Host smart-d2a09e38-c744-469b-9a24-cf309b0f8b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539803294 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1539803294
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3610805339
Short name T910
Test name
Test status
Simulation time 2087768716 ps
CPU time 1.48 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 200940 kb
Host smart-a9dfd06c-5f0c-43f9-9d6e-3399193c6dfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610805339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3610805339
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3812768234
Short name T799
Test name
Test status
Simulation time 2015880333 ps
CPU time 5.45 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 200848 kb
Host smart-b8bb132e-ff52-414b-bc75-c47e44e54c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812768234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3812768234
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1681150683
Short name T25
Test name
Test status
Simulation time 4306457000 ps
CPU time 6.46 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 201124 kb
Host smart-203d6a06-6a45-40a1-ab92-58faabe67cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681150683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1681150683
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3004691484
Short name T289
Test name
Test status
Simulation time 2090048333 ps
CPU time 2.83 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:43:58 PM PDT 24
Peak memory 201060 kb
Host smart-d53e2fb0-bb8a-46e5-8789-c039b8a55208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004691484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.3004691484
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1160429592
Short name T293
Test name
Test status
Simulation time 22198938910 ps
CPU time 58.78 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:44:49 PM PDT 24
Peak memory 201284 kb
Host smart-4dc29f35-7101-4ca5-8175-cb6ac0da5449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160429592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1160429592
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1674620331
Short name T812
Test name
Test status
Simulation time 2031423015 ps
CPU time 1.84 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:30 PM PDT 24
Peak memory 200644 kb
Host smart-2c9a2b59-2cdb-4022-8396-963733e0f973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674620331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.1674620331
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1312610454
Short name T805
Test name
Test status
Simulation time 2023718666 ps
CPU time 1.83 seconds
Started Jun 24 05:44:31 PM PDT 24
Finished Jun 24 05:44:40 PM PDT 24
Peak memory 200856 kb
Host smart-2c0c8356-068b-436e-acbd-6864b5d68fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312610454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1312610454
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.569037653
Short name T821
Test name
Test status
Simulation time 2052754494 ps
CPU time 1.49 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 200648 kb
Host smart-f9cbfad6-0e3b-4a67-945f-92f2b16a7e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569037653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_tes
t.569037653
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3801322074
Short name T879
Test name
Test status
Simulation time 2055635298 ps
CPU time 1.75 seconds
Started Jun 24 05:44:23 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 200636 kb
Host smart-cab7295c-d5bb-4522-bc6a-05f4e4c65ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801322074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3801322074
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1049135621
Short name T885
Test name
Test status
Simulation time 2014673029 ps
CPU time 5.63 seconds
Started Jun 24 05:44:28 PM PDT 24
Finished Jun 24 05:44:36 PM PDT 24
Peak memory 200820 kb
Host smart-50e47df8-7f3d-43dd-bc4b-c58c43e50b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049135621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1049135621
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2370116484
Short name T829
Test name
Test status
Simulation time 2039971475 ps
CPU time 1.84 seconds
Started Jun 24 05:44:17 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 200552 kb
Host smart-a455f50f-97a4-4a15-8246-37e454094aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370116484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2370116484
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2728510269
Short name T795
Test name
Test status
Simulation time 2021331591 ps
CPU time 3.06 seconds
Started Jun 24 05:44:08 PM PDT 24
Finished Jun 24 05:44:12 PM PDT 24
Peak memory 200604 kb
Host smart-87180700-263a-4fac-b5d1-90b91d838cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728510269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.2728510269
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3339115090
Short name T898
Test name
Test status
Simulation time 2012526756 ps
CPU time 5.84 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:34 PM PDT 24
Peak memory 200620 kb
Host smart-85facc39-797b-4034-ae6f-d13373cbb68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339115090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3339115090
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.331956461
Short name T843
Test name
Test status
Simulation time 2034293705 ps
CPU time 2.05 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:14 PM PDT 24
Peak memory 200636 kb
Host smart-182448b8-874d-4b0d-92e2-bb7c4ec05bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331956461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.331956461
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3581399798
Short name T816
Test name
Test status
Simulation time 2041592520 ps
CPU time 1.75 seconds
Started Jun 24 05:44:17 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 200832 kb
Host smart-6ad2381a-ddb9-4a33-9731-6c361c18793b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581399798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.3581399798
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1099859839
Short name T815
Test name
Test status
Simulation time 3013345710 ps
CPU time 12.44 seconds
Started Jun 24 05:43:51 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 201212 kb
Host smart-4af235bf-d1c1-45c3-b3b0-c184ffcae892
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099859839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1099859839
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2811946459
Short name T887
Test name
Test status
Simulation time 68773803291 ps
CPU time 78.43 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:45:10 PM PDT 24
Peak memory 201236 kb
Host smart-0dadb44b-31c8-49bb-b4fc-65f18ab1f932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811946459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.2811946459
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.88180222
Short name T851
Test name
Test status
Simulation time 4011982020 ps
CPU time 11.24 seconds
Started Jun 24 05:43:54 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 201100 kb
Host smart-962464fe-2de8-4980-a13e-e7642d4da149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88180222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_c
sr_hw_reset.88180222
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2836465142
Short name T846
Test name
Test status
Simulation time 2136674771 ps
CPU time 6.45 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 200992 kb
Host smart-6f475be1-cd8e-4fee-b290-e8c1d3cb87c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836465142 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2836465142
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1575165904
Short name T808
Test name
Test status
Simulation time 2038488597 ps
CPU time 5.63 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 200940 kb
Host smart-9f952bd2-2cf4-436e-9af0-9809ff40e4a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575165904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1575165904
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2938015663
Short name T908
Test name
Test status
Simulation time 2036832301 ps
CPU time 1.95 seconds
Started Jun 24 05:43:59 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 200644 kb
Host smart-64d3de3f-5b7d-4220-b8f8-72c6d774c882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938015663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.2938015663
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4287462506
Short name T340
Test name
Test status
Simulation time 5020245261 ps
CPU time 3.9 seconds
Started Jun 24 05:44:00 PM PDT 24
Finished Jun 24 05:44:05 PM PDT 24
Peak memory 201392 kb
Host smart-c423e11a-439e-470a-ab98-6a77b4966fa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287462506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.4287462506
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3709317632
Short name T287
Test name
Test status
Simulation time 2096191822 ps
CPU time 4.09 seconds
Started Jun 24 05:44:01 PM PDT 24
Finished Jun 24 05:44:07 PM PDT 24
Peak memory 201060 kb
Host smart-97c34c6e-a453-4bd1-bca6-f6139df83174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709317632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3709317632
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3997380737
Short name T857
Test name
Test status
Simulation time 42376791074 ps
CPU time 99.6 seconds
Started Jun 24 05:43:53 PM PDT 24
Finished Jun 24 05:45:36 PM PDT 24
Peak memory 201252 kb
Host smart-efd05c1a-3442-4de8-bdb8-e6c395681143
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997380737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3997380737
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3666689374
Short name T802
Test name
Test status
Simulation time 2028300372 ps
CPU time 1.99 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:31 PM PDT 24
Peak memory 200856 kb
Host smart-a4c506cc-6ddb-494b-8211-b74af339df29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666689374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3666689374
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.376077119
Short name T835
Test name
Test status
Simulation time 2026055491 ps
CPU time 1.95 seconds
Started Jun 24 05:44:21 PM PDT 24
Finished Jun 24 05:44:24 PM PDT 24
Peak memory 200644 kb
Host smart-094959d0-b0cf-469c-84eb-de572bb9dfaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376077119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.376077119
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3598538992
Short name T874
Test name
Test status
Simulation time 2042518869 ps
CPU time 1.72 seconds
Started Jun 24 05:44:29 PM PDT 24
Finished Jun 24 05:44:33 PM PDT 24
Peak memory 200852 kb
Host smart-22ca918f-55c4-4d11-abc3-d6e491490336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598538992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3598538992
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1180091222
Short name T852
Test name
Test status
Simulation time 2011637429 ps
CPU time 5.47 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:22 PM PDT 24
Peak memory 200856 kb
Host smart-f95e6bb6-da67-4d4a-96da-45743afa0b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180091222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1180091222
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.820418392
Short name T853
Test name
Test status
Simulation time 2010225095 ps
CPU time 5.63 seconds
Started Jun 24 05:44:25 PM PDT 24
Finished Jun 24 05:44:32 PM PDT 24
Peak memory 200640 kb
Host smart-d5688e3a-a18c-4f52-8216-652dede61366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820418392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.820418392
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.603833108
Short name T883
Test name
Test status
Simulation time 2011787034 ps
CPU time 5.99 seconds
Started Jun 24 05:44:16 PM PDT 24
Finished Jun 24 05:44:25 PM PDT 24
Peak memory 200648 kb
Host smart-7ecf6104-df05-4189-a9af-5dad1dc10683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603833108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_tes
t.603833108
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2981048866
Short name T907
Test name
Test status
Simulation time 2033529189 ps
CPU time 1.95 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 200648 kb
Host smart-43aa2dd2-0fd8-47c7-af65-71fccf584eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981048866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.2981048866
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1294323154
Short name T834
Test name
Test status
Simulation time 2040825755 ps
CPU time 1.9 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:19 PM PDT 24
Peak memory 200644 kb
Host smart-a297db1a-a242-4e56-a56f-6cf7d3caaa51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294323154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1294323154
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1142934264
Short name T804
Test name
Test status
Simulation time 2028485364 ps
CPU time 1.97 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:31 PM PDT 24
Peak memory 200636 kb
Host smart-f43b75a2-09f7-4b89-8200-e8e12d9db781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142934264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1142934264
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1867398151
Short name T794
Test name
Test status
Simulation time 2035708640 ps
CPU time 2.02 seconds
Started Jun 24 05:44:16 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 200648 kb
Host smart-0d616b87-0dfe-4c28-8e6e-7b674d48ef88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867398151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.1867398151
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2034498251
Short name T863
Test name
Test status
Simulation time 3213822690 ps
CPU time 5.44 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 201264 kb
Host smart-a5f327fa-ab02-42d4-ad29-90d99524e379
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034498251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.2034498251
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2156864571
Short name T333
Test name
Test status
Simulation time 40483460371 ps
CPU time 185.55 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:47:22 PM PDT 24
Peak memory 201304 kb
Host smart-f2117f4e-1607-465f-86ea-cd8422ea11c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156864571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2156864571
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.596612206
Short name T326
Test name
Test status
Simulation time 6018658702 ps
CPU time 8.66 seconds
Started Jun 24 05:43:58 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 201024 kb
Host smart-709abd05-3179-4e3c-938a-007854534e6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596612206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.596612206
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.574723361
Short name T822
Test name
Test status
Simulation time 2048100103 ps
CPU time 3.64 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 201092 kb
Host smart-d276eceb-a34b-4744-9422-e7c353084c12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574723361 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.574723361
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3916783514
Short name T332
Test name
Test status
Simulation time 2080586179 ps
CPU time 2.17 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 201028 kb
Host smart-5b6e47e2-b800-4ed0-b15b-90836cf7c956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916783514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3916783514
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1716457403
Short name T813
Test name
Test status
Simulation time 2042585689 ps
CPU time 1.94 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 200856 kb
Host smart-2da5a432-f03d-44da-ad16-7c4b2fde6a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716457403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1716457403
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2203348680
Short name T845
Test name
Test status
Simulation time 7600265671 ps
CPU time 5.88 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:44:00 PM PDT 24
Peak memory 201240 kb
Host smart-e6bddafc-0d87-4f2e-b875-476713de4a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203348680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2203348680
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3056778593
Short name T904
Test name
Test status
Simulation time 2117802850 ps
CPU time 7.61 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 209284 kb
Host smart-c0009477-f1a1-4130-a996-38cfb63e4d54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056778593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.3056778593
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1692775572
Short name T847
Test name
Test status
Simulation time 42364621498 ps
CPU time 109.54 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:45:46 PM PDT 24
Peak memory 201196 kb
Host smart-0063664e-c125-42c2-b298-80a05cd2b65e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692775572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.1692775572
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3999445353
Short name T884
Test name
Test status
Simulation time 2010205710 ps
CPU time 5.61 seconds
Started Jun 24 05:44:25 PM PDT 24
Finished Jun 24 05:44:32 PM PDT 24
Peak memory 200864 kb
Host smart-12da418a-1a3d-4ec1-a4a8-e1af96a2d5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999445353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3999445353
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3583071198
Short name T797
Test name
Test status
Simulation time 2032837644 ps
CPU time 1.97 seconds
Started Jun 24 05:44:08 PM PDT 24
Finished Jun 24 05:44:11 PM PDT 24
Peak memory 200596 kb
Host smart-a580450b-97ce-498b-9563-047c35e565dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583071198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3583071198
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3686965218
Short name T817
Test name
Test status
Simulation time 2016365406 ps
CPU time 5.96 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:34 PM PDT 24
Peak memory 200856 kb
Host smart-85cf36ea-4fdb-4c1e-8af0-e7d60aa1cd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686965218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.3686965218
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2222045548
Short name T868
Test name
Test status
Simulation time 2044943181 ps
CPU time 1.81 seconds
Started Jun 24 05:44:24 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 200628 kb
Host smart-724e75b7-852c-4659-b7ac-91c44bf35ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222045548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.2222045548
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3571482435
Short name T807
Test name
Test status
Simulation time 2015286887 ps
CPU time 5.48 seconds
Started Jun 24 05:44:20 PM PDT 24
Finished Jun 24 05:44:26 PM PDT 24
Peak memory 200644 kb
Host smart-e95c3531-a843-4dcf-988f-951302d90c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571482435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3571482435
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1391496222
Short name T886
Test name
Test status
Simulation time 2021473641 ps
CPU time 3.11 seconds
Started Jun 24 05:44:28 PM PDT 24
Finished Jun 24 05:44:33 PM PDT 24
Peak memory 200640 kb
Host smart-ef1fb881-cbd9-415c-8dae-b09f8971a370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391496222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1391496222
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.841261754
Short name T893
Test name
Test status
Simulation time 2021735460 ps
CPU time 3.05 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 200648 kb
Host smart-508ea882-f038-470f-80e9-7d787ba45bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841261754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.841261754
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1105352025
Short name T826
Test name
Test status
Simulation time 2022137509 ps
CPU time 3.34 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 200860 kb
Host smart-a029be18-3886-4403-a221-af4f6f1f47eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105352025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.1105352025
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.522836580
Short name T800
Test name
Test status
Simulation time 2019395369 ps
CPU time 2.53 seconds
Started Jun 24 05:44:27 PM PDT 24
Finished Jun 24 05:44:32 PM PDT 24
Peak memory 200816 kb
Host smart-17f5a7d5-c599-41ca-ba22-471e71acadfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522836580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_tes
t.522836580
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2637869642
Short name T803
Test name
Test status
Simulation time 2010271476 ps
CPU time 5.86 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:22 PM PDT 24
Peak memory 200616 kb
Host smart-ef3d716f-bbad-4da1-aa2e-6eec29983bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637869642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2637869642
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1306706986
Short name T831
Test name
Test status
Simulation time 2187424917 ps
CPU time 2.56 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 201276 kb
Host smart-2ff16b00-8a83-4257-b31e-b693b8ff5a4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306706986 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1306706986
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.553794968
Short name T339
Test name
Test status
Simulation time 2038650122 ps
CPU time 5.82 seconds
Started Jun 24 05:43:58 PM PDT 24
Finished Jun 24 05:44:05 PM PDT 24
Peak memory 200872 kb
Host smart-116b98bb-c154-443e-b8bf-ac8de79c8271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553794968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw
.553794968
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.197429677
Short name T861
Test name
Test status
Simulation time 2013155261 ps
CPU time 5.71 seconds
Started Jun 24 05:44:08 PM PDT 24
Finished Jun 24 05:44:14 PM PDT 24
Peak memory 200652 kb
Host smart-59677738-b108-49d4-b83b-63f8316a258a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197429677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.197429677
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2446001459
Short name T810
Test name
Test status
Simulation time 5318833325 ps
CPU time 12.8 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 201100 kb
Host smart-a6f99789-20f2-4ffa-8a43-03d5e489a941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446001459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2446001459
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2401622466
Short name T274
Test name
Test status
Simulation time 2041678004 ps
CPU time 7.01 seconds
Started Jun 24 05:44:05 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 209320 kb
Host smart-b3e80f5d-c7fd-4519-9a28-4f7829b10b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401622466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2401622466
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2663747948
Short name T796
Test name
Test status
Simulation time 2061552625 ps
CPU time 3.67 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:18 PM PDT 24
Peak memory 200996 kb
Host smart-00c65a4f-827d-4dda-b15f-cf8f6cca01e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663747948 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2663747948
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.658005673
Short name T334
Test name
Test status
Simulation time 2129450430 ps
CPU time 2.25 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:50 PM PDT 24
Peak memory 201036 kb
Host smart-a269a0c1-1631-47b1-b194-174102866043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658005673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.658005673
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.94374687
Short name T836
Test name
Test status
Simulation time 2035338662 ps
CPU time 1.83 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 200816 kb
Host smart-c907df6a-7f59-4a6f-a4d3-687f0ac2983f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94374687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.94374687
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3475382232
Short name T837
Test name
Test status
Simulation time 5128108658 ps
CPU time 13.32 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:44:07 PM PDT 24
Peak memory 201216 kb
Host smart-0d816151-0721-439e-92e4-4628edb2a295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475382232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3475382232
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2295012233
Short name T888
Test name
Test status
Simulation time 22370683806 ps
CPU time 19.6 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 201256 kb
Host smart-95c66456-9d09-4cdf-a64b-afca21cdff6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295012233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.2295012233
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1580996063
Short name T806
Test name
Test status
Simulation time 2076624575 ps
CPU time 6.11 seconds
Started Jun 24 05:44:03 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 200996 kb
Host smart-439ff05e-6de5-43fe-a86f-70d813739d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580996063 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1580996063
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2693879902
Short name T338
Test name
Test status
Simulation time 2083798342 ps
CPU time 3.49 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 201008 kb
Host smart-eb98f637-4b17-4da2-911a-17e7c830c744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693879902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2693879902
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1998923335
Short name T882
Test name
Test status
Simulation time 2069699987 ps
CPU time 1.32 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 200640 kb
Host smart-3476560b-fdcd-4e81-a69b-0cf37cd22323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998923335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1998923335
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.966920301
Short name T818
Test name
Test status
Simulation time 5344008185 ps
CPU time 5.54 seconds
Started Jun 24 05:43:53 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 201276 kb
Host smart-6319a5b6-0f7c-4569-8de2-e8c84d44d2c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966920301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
sysrst_ctrl_same_csr_outstanding.966920301
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.936557580
Short name T275
Test name
Test status
Simulation time 2085626408 ps
CPU time 4.91 seconds
Started Jun 24 05:43:54 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 201036 kb
Host smart-c28a0e86-bfd4-4451-af5e-0823e7e324c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936557580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.936557580
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1816270729
Short name T911
Test name
Test status
Simulation time 42608998165 ps
CPU time 20.11 seconds
Started Jun 24 05:44:14 PM PDT 24
Finished Jun 24 05:44:37 PM PDT 24
Peak memory 201280 kb
Host smart-8ef99693-0bc9-4feb-8f78-86d36ad8c8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816270729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1816270729
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.503526980
Short name T811
Test name
Test status
Simulation time 2076203079 ps
CPU time 5.89 seconds
Started Jun 24 05:44:22 PM PDT 24
Finished Jun 24 05:44:29 PM PDT 24
Peak memory 200980 kb
Host smart-4b757596-3c61-4a44-a201-23362ab7b90c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503526980 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.503526980
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3169188057
Short name T31
Test name
Test status
Simulation time 2046988095 ps
CPU time 3.12 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:10 PM PDT 24
Peak memory 200936 kb
Host smart-9388087f-03c8-4d27-b7eb-fdc238a667c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169188057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3169188057
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.655285788
Short name T906
Test name
Test status
Simulation time 2039737529 ps
CPU time 1.84 seconds
Started Jun 24 05:43:57 PM PDT 24
Finished Jun 24 05:44:00 PM PDT 24
Peak memory 200644 kb
Host smart-cf4445f5-41b4-482c-b12b-864095978bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655285788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.655285788
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2733057219
Short name T341
Test name
Test status
Simulation time 4615995834 ps
CPU time 2.63 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 201100 kb
Host smart-ee71243d-1231-4ab6-b5d6-088a74d0775e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733057219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.2733057219
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3413019605
Short name T840
Test name
Test status
Simulation time 2050487998 ps
CPU time 7.78 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 209296 kb
Host smart-972df8d0-71f6-4c2a-ae55-2029902531e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413019605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3413019605
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.187211270
Short name T890
Test name
Test status
Simulation time 42949393276 ps
CPU time 30.28 seconds
Started Jun 24 05:43:59 PM PDT 24
Finished Jun 24 05:44:31 PM PDT 24
Peak memory 201304 kb
Host smart-72f8a6df-e015-45e7-a1d3-0ffc93a9d356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187211270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_tl_intg_err.187211270
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1902316468
Short name T858
Test name
Test status
Simulation time 2114369201 ps
CPU time 6.07 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:21 PM PDT 24
Peak memory 201072 kb
Host smart-6d424ccd-5562-4ec0-9f66-d0dfee1f2e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902316468 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1902316468
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.4068616588
Short name T327
Test name
Test status
Simulation time 2151341625 ps
CPU time 1.67 seconds
Started Jun 24 05:44:10 PM PDT 24
Finished Jun 24 05:44:12 PM PDT 24
Peak memory 201000 kb
Host smart-dc6a3f67-d9f3-498d-84b5-b429f9fa0e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068616588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.4068616588
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4207285319
Short name T871
Test name
Test status
Simulation time 2010512564 ps
CPU time 5.64 seconds
Started Jun 24 05:43:57 PM PDT 24
Finished Jun 24 05:44:04 PM PDT 24
Peak memory 200532 kb
Host smart-b0ce6388-3750-4faa-a96e-af2eb665ad81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207285319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.4207285319
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2099566458
Short name T809
Test name
Test status
Simulation time 8574267173 ps
CPU time 30.51 seconds
Started Jun 24 05:44:01 PM PDT 24
Finished Jun 24 05:44:33 PM PDT 24
Peak memory 201300 kb
Host smart-2d63aa10-870d-4d18-b900-2aea7fa80f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099566458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.2099566458
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2356427951
Short name T913
Test name
Test status
Simulation time 2121541228 ps
CPU time 4.29 seconds
Started Jun 24 05:43:59 PM PDT 24
Finished Jun 24 05:44:05 PM PDT 24
Peak memory 201064 kb
Host smart-d11f8d18-2812-4d75-bc8a-494cb10405dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356427951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2356427951
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1473748172
Short name T914
Test name
Test status
Simulation time 42474306560 ps
CPU time 103.01 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:45:38 PM PDT 24
Peak memory 201276 kb
Host smart-f3889e42-958e-4e9e-96a2-142ef1339c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473748172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.1473748172
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3353246893
Short name T479
Test name
Test status
Simulation time 2018556601 ps
CPU time 3.51 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 201236 kb
Host smart-ed5a35d8-1b5e-408c-b991-157b3a1221fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353246893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3353246893
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.878316755
Short name T432
Test name
Test status
Simulation time 3325829956 ps
CPU time 2.71 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:23 PM PDT 24
Peak memory 201312 kb
Host smart-1e4503fa-4f84-4d6e-9a06-42be7dfce48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878316755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.878316755
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3181825126
Short name T575
Test name
Test status
Simulation time 86008226972 ps
CPU time 102.64 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:34:02 PM PDT 24
Peak memory 201428 kb
Host smart-844d1cee-e61d-4d6f-9dee-1fb0a1132a17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181825126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3181825126
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4264180023
Short name T716
Test name
Test status
Simulation time 2403855632 ps
CPU time 6.95 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:25 PM PDT 24
Peak memory 201240 kb
Host smart-7da1d355-4d6b-4df6-a423-bf1ec5b8b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264180023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.4264180023
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1596823294
Short name T503
Test name
Test status
Simulation time 2381180561 ps
CPU time 3.45 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:20 PM PDT 24
Peak memory 201232 kb
Host smart-ca0b1985-f8e4-4a33-8d07-a534d9bfbe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596823294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1596823294
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.436803554
Short name T98
Test name
Test status
Simulation time 28855583205 ps
CPU time 18.03 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:33 PM PDT 24
Peak memory 201532 kb
Host smart-2218b795-ccfb-43e7-b7e1-9243f0a0ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436803554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wit
h_pre_cond.436803554
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1242484020
Short name T549
Test name
Test status
Simulation time 2814467016 ps
CPU time 2.67 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 201216 kb
Host smart-ea4a36d1-eaa7-4f00-b6a5-13b5f136bfcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242484020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.1242484020
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1645895670
Short name T736
Test name
Test status
Simulation time 2900460394 ps
CPU time 6.59 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:25 PM PDT 24
Peak memory 201256 kb
Host smart-7da8f787-c52a-4023-bf63-12bc262a3d35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645895670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1645895670
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1538357663
Short name T310
Test name
Test status
Simulation time 2634943497 ps
CPU time 2.12 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 201220 kb
Host smart-002f9651-134b-45a4-9f00-5d7fe0ec1ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538357663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1538357663
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2405663473
Short name T64
Test name
Test status
Simulation time 2462145131 ps
CPU time 6.8 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 201184 kb
Host smart-cdfcaa25-b765-4665-80ba-6c5b0fc95cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405663473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2405663473
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.2425097243
Short name T739
Test name
Test status
Simulation time 2267608366 ps
CPU time 1.99 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 201248 kb
Host smart-1334231b-8a7d-4724-8ef6-909e34d484ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425097243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2425097243
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.4195890171
Short name T559
Test name
Test status
Simulation time 2509359065 ps
CPU time 7.1 seconds
Started Jun 24 06:32:19 PM PDT 24
Finished Jun 24 06:32:28 PM PDT 24
Peak memory 201304 kb
Host smart-a984209d-8656-4258-a7be-4767539a6dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195890171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.4195890171
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3690115432
Short name T295
Test name
Test status
Simulation time 22018075790 ps
CPU time 52.32 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:33:11 PM PDT 24
Peak memory 220856 kb
Host smart-2034508f-3769-45d3-98ce-35ed201ba732
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690115432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3690115432
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2004013131
Short name T195
Test name
Test status
Simulation time 2128310861 ps
CPU time 2 seconds
Started Jun 24 06:32:19 PM PDT 24
Finished Jun 24 06:32:23 PM PDT 24
Peak memory 201148 kb
Host smart-b126206a-6fe0-45f0-b46c-1e7225d2aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004013131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2004013131
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3913328862
Short name T200
Test name
Test status
Simulation time 10094798747 ps
CPU time 6.69 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:24 PM PDT 24
Peak memory 201212 kb
Host smart-b177adfe-c95a-4c5a-bb92-8d38e0c29317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913328862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3913328862
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.61394602
Short name T136
Test name
Test status
Simulation time 8475766824 ps
CPU time 1.14 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:20 PM PDT 24
Peak memory 201244 kb
Host smart-c4532ffa-0f64-4e54-82dc-3c120e8bcbab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61394602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_ultra_low_pwr.61394602
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3552300144
Short name T534
Test name
Test status
Simulation time 3775371613 ps
CPU time 1.19 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:33 PM PDT 24
Peak memory 201320 kb
Host smart-ca26b732-eb2e-4fde-8489-56dae67f36c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552300144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3552300144
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.1934101296
Short name T193
Test name
Test status
Simulation time 71769543060 ps
CPU time 42.06 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:33:13 PM PDT 24
Peak memory 201448 kb
Host smart-3fa35dd8-ff1c-4ea7-a57e-ff0d9960513f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934101296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.1934101296
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3485436396
Short name T94
Test name
Test status
Simulation time 2229102756 ps
CPU time 3.46 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:35 PM PDT 24
Peak memory 201240 kb
Host smart-49e58df4-c336-4fe9-b659-b7b8bc38b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485436396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3485436396
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3615735673
Short name T713
Test name
Test status
Simulation time 2395392487 ps
CPU time 2.18 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:32 PM PDT 24
Peak memory 201252 kb
Host smart-70d590cb-fbd6-49d1-b6cf-7a30e64194ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615735673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3615735673
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2308001030
Short name T501
Test name
Test status
Simulation time 3716500341 ps
CPU time 8.23 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201220 kb
Host smart-c6bfd7fb-5d28-4d60-aafa-5e3bb1b36b21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308001030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2308001030
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3669817991
Short name T224
Test name
Test status
Simulation time 3296476990 ps
CPU time 4.98 seconds
Started Jun 24 06:32:32 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201280 kb
Host smart-c2adf26b-02d2-4420-8343-a2036d5ffe6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669817991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3669817991
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1115010610
Short name T475
Test name
Test status
Simulation time 2638152819 ps
CPU time 1.72 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:32 PM PDT 24
Peak memory 201268 kb
Host smart-21b76ee1-3719-423e-8ca4-84d37127a137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115010610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1115010610
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2887833853
Short name T118
Test name
Test status
Simulation time 2434648873 ps
CPU time 7.64 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201268 kb
Host smart-c5f51e0f-ac6e-499f-b725-9f12211897d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887833853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2887833853
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1072960108
Short name T727
Test name
Test status
Simulation time 2213625809 ps
CPU time 2.11 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:34 PM PDT 24
Peak memory 201180 kb
Host smart-b8894f2f-d5df-4d02-acf8-502b933dd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072960108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1072960108
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3712045570
Short name T661
Test name
Test status
Simulation time 2509122938 ps
CPU time 6.94 seconds
Started Jun 24 06:32:28 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 201320 kb
Host smart-71472671-7077-4662-8fe8-eecf32c280df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712045570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3712045570
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2854000258
Short name T278
Test name
Test status
Simulation time 22069294592 ps
CPU time 15.29 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:46 PM PDT 24
Peak memory 220776 kb
Host smart-5df1278e-a770-424f-be83-06378140881d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854000258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2854000258
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.1464224334
Short name T597
Test name
Test status
Simulation time 2112431830 ps
CPU time 5.86 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:35 PM PDT 24
Peak memory 201148 kb
Host smart-f8fe94af-4782-4645-a1bc-62dadfccdb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464224334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1464224334
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.2219124462
Short name T130
Test name
Test status
Simulation time 1197240537300 ps
CPU time 324.69 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:37:58 PM PDT 24
Peak memory 201200 kb
Host smart-4b15f64e-4189-46af-a1dc-5c73dcd75478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219124462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.2219124462
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.643605921
Short name T323
Test name
Test status
Simulation time 59415792840 ps
CPU time 63.85 seconds
Started Jun 24 06:32:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 211720 kb
Host smart-d679d6d2-cc46-4fb0-8227-11027cca601b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643605921 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.643605921
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1580257392
Short name T469
Test name
Test status
Simulation time 3211743393 ps
CPU time 6.15 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 201268 kb
Host smart-8b22d2c8-dbc5-484e-a53d-f5cad7a171b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580257392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1580257392
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.47254279
Short name T583
Test name
Test status
Simulation time 2009742683 ps
CPU time 4.64 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:58 PM PDT 24
Peak memory 201264 kb
Host smart-7d65e144-f71f-497a-9127-bcf0da1ed7ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47254279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test
.47254279
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2036202449
Short name T495
Test name
Test status
Simulation time 3667575206 ps
CPU time 10.07 seconds
Started Jun 24 06:32:47 PM PDT 24
Finished Jun 24 06:32:58 PM PDT 24
Peak memory 201296 kb
Host smart-e2c2a75c-f767-4adc-bd72-145470b356d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036202449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
036202449
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.4153936506
Short name T251
Test name
Test status
Simulation time 73690447311 ps
CPU time 55.37 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:33:57 PM PDT 24
Peak memory 201632 kb
Host smart-e6fb270a-0a42-428a-8d1d-2f63f8254ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153936506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.4153936506
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1104163152
Short name T737
Test name
Test status
Simulation time 24833743583 ps
CPU time 64.5 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201588 kb
Host smart-d9088a2d-bd14-4c24-9261-8f1d84ceb261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104163152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1104163152
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2418338205
Short name T489
Test name
Test status
Simulation time 2521114656 ps
CPU time 6.87 seconds
Started Jun 24 06:32:57 PM PDT 24
Finished Jun 24 06:33:06 PM PDT 24
Peak memory 201192 kb
Host smart-c84cca03-9d20-4ab8-b44f-99b537a6301f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418338205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2418338205
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.679488141
Short name T159
Test name
Test status
Simulation time 3555155241 ps
CPU time 5.36 seconds
Started Jun 24 06:32:53 PM PDT 24
Finished Jun 24 06:33:01 PM PDT 24
Peak memory 200396 kb
Host smart-1f7e218d-f307-4ace-ad01-21e8c52f2b3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679488141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.679488141
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3881038138
Short name T485
Test name
Test status
Simulation time 2612492467 ps
CPU time 5.43 seconds
Started Jun 24 06:32:58 PM PDT 24
Finished Jun 24 06:33:05 PM PDT 24
Peak memory 201212 kb
Host smart-7a399155-8848-435d-81e5-fe8d78842bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881038138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3881038138
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1466814514
Short name T505
Test name
Test status
Simulation time 2470257375 ps
CPU time 2.2 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:56 PM PDT 24
Peak memory 201260 kb
Host smart-d4d9b46a-8fd3-4129-8fe4-a03bd2e6d6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466814514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1466814514
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3321553715
Short name T175
Test name
Test status
Simulation time 2202387053 ps
CPU time 3.19 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:55 PM PDT 24
Peak memory 201232 kb
Host smart-8dcaf3fc-2927-4793-9278-d3ac79849837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321553715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3321553715
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.4035939986
Short name T23
Test name
Test status
Simulation time 2522435890 ps
CPU time 2.4 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:32:54 PM PDT 24
Peak memory 201324 kb
Host smart-994441d3-ef84-4f49-a978-e300794de341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035939986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.4035939986
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3723088860
Short name T511
Test name
Test status
Simulation time 2117068961 ps
CPU time 3.11 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201164 kb
Host smart-b5ed5b9d-d527-4073-91a0-b716e89b485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723088860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3723088860
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2367201715
Short name T789
Test name
Test status
Simulation time 10002083591 ps
CPU time 13.34 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:33:06 PM PDT 24
Peak memory 201280 kb
Host smart-a6b0d2bb-fa6c-4120-b8a9-2f14954bdf68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367201715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2367201715
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1638201375
Short name T396
Test name
Test status
Simulation time 2045472367 ps
CPU time 1.34 seconds
Started Jun 24 06:32:54 PM PDT 24
Finished Jun 24 06:32:59 PM PDT 24
Peak memory 201236 kb
Host smart-0f2fd116-8eea-45c2-959e-491115261a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638201375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1638201375
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1036160675
Short name T303
Test name
Test status
Simulation time 3604410599 ps
CPU time 2.1 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201332 kb
Host smart-4793a6fe-f381-40e9-a19b-d0d3b3038d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036160675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1
036160675
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3735984338
Short name T256
Test name
Test status
Simulation time 74495580792 ps
CPU time 15.1 seconds
Started Jun 24 06:32:53 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201428 kb
Host smart-2d4a696f-fe19-479d-9146-9fca823ef985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735984338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.3735984338
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2005343516
Short name T269
Test name
Test status
Simulation time 25330929205 ps
CPU time 60.34 seconds
Started Jun 24 06:32:55 PM PDT 24
Finished Jun 24 06:33:58 PM PDT 24
Peak memory 201544 kb
Host smart-3c8c551f-7714-4042-80f7-f58a82f0a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005343516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.2005343516
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1259978755
Short name T529
Test name
Test status
Simulation time 4106328259 ps
CPU time 2.81 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:56 PM PDT 24
Peak memory 201232 kb
Host smart-79877ebe-c961-46e8-9404-f50ea67fb717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259978755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.1259978755
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1260811556
Short name T756
Test name
Test status
Simulation time 3127728028 ps
CPU time 4.52 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:55 PM PDT 24
Peak memory 201212 kb
Host smart-da8ad0e3-df74-4e39-a540-fdb5dbe4a58f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260811556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1260811556
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2644565979
Short name T608
Test name
Test status
Simulation time 2607663630 ps
CPU time 7.15 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:33:01 PM PDT 24
Peak memory 201252 kb
Host smart-1f85a2ca-4523-48dc-9bb1-11e593a5047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644565979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2644565979
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3990914962
Short name T474
Test name
Test status
Simulation time 2452600867 ps
CPU time 7.35 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:33:00 PM PDT 24
Peak memory 201256 kb
Host smart-58363df2-7ca1-4f5c-a15d-15682b587c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990914962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3990914962
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.4232902797
Short name T419
Test name
Test status
Simulation time 2251382863 ps
CPU time 6.12 seconds
Started Jun 24 06:32:48 PM PDT 24
Finished Jun 24 06:32:55 PM PDT 24
Peak memory 201216 kb
Host smart-5ab6f803-ca9d-4a9e-bc64-b155d7ff1a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232902797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.4232902797
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2808719269
Short name T313
Test name
Test status
Simulation time 2533222204 ps
CPU time 2.36 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201316 kb
Host smart-e5749dab-a748-4646-8add-80a80b66da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808719269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2808719269
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.3605195225
Short name T398
Test name
Test status
Simulation time 2118056222 ps
CPU time 3.45 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:32:58 PM PDT 24
Peak memory 201168 kb
Host smart-fc9ea6e6-843e-474c-87a1-e4b1c7514b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605195225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3605195225
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.7944928
Short name T454
Test name
Test status
Simulation time 154271033436 ps
CPU time 42.07 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201484 kb
Host smart-852f692f-656d-484a-92de-02be8202aa6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7944928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stre
ss_all.7944928
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3482600968
Short name T127
Test name
Test status
Simulation time 5671968385 ps
CPU time 7.72 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:33:02 PM PDT 24
Peak memory 201236 kb
Host smart-d93bb10f-7926-4dfb-9346-5103983b0415
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482600968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.3482600968
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1243971203
Short name T257
Test name
Test status
Simulation time 2014045373 ps
CPU time 6.05 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:33:00 PM PDT 24
Peak memory 201252 kb
Host smart-57bc1707-eb6f-4734-8df2-bac989707477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243971203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1243971203
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1637099422
Short name T53
Test name
Test status
Simulation time 3517650249 ps
CPU time 2.77 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201304 kb
Host smart-5db6152d-3337-4153-b18f-507813a9c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637099422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
637099422
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.332846622
Short name T567
Test name
Test status
Simulation time 91560730908 ps
CPU time 111.3 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201644 kb
Host smart-73da6441-6607-4efe-bed6-66970ede3954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332846622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_combo_detect.332846622
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.4153919583
Short name T134
Test name
Test status
Simulation time 3702675125 ps
CPU time 5.47 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:33:00 PM PDT 24
Peak memory 201212 kb
Host smart-ceeb2a2d-ca14-46cf-baa1-1153e06dc9a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153919583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.4153919583
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2017656787
Short name T634
Test name
Test status
Simulation time 2979389660 ps
CPU time 8.17 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:33:00 PM PDT 24
Peak memory 201228 kb
Host smart-0c3d59bb-f1c8-4e56-9a6c-91106ed194ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017656787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2017656787
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1645031064
Short name T787
Test name
Test status
Simulation time 2616848832 ps
CPU time 3.91 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201236 kb
Host smart-13c96639-4807-4a58-ad06-4ebd31088ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645031064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1645031064
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.518777939
Short name T582
Test name
Test status
Simulation time 2473552279 ps
CPU time 8.04 seconds
Started Jun 24 06:32:53 PM PDT 24
Finished Jun 24 06:33:04 PM PDT 24
Peak memory 200448 kb
Host smart-83de88aa-67b9-4c65-bbd0-662488fd397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518777939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.518777939
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.703582274
Short name T133
Test name
Test status
Simulation time 2169866930 ps
CPU time 6.17 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:33:01 PM PDT 24
Peak memory 201236 kb
Host smart-0f7087a6-b5b0-4863-a7aa-a807d0a23050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703582274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.703582274
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1750067534
Short name T445
Test name
Test status
Simulation time 2513323220 ps
CPU time 3.93 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:04 PM PDT 24
Peak memory 201328 kb
Host smart-bfffcfaf-0473-4532-9daa-793b43008091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750067534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1750067534
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.3531829007
Short name T135
Test name
Test status
Simulation time 2110080308 ps
CPU time 6.01 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:32:58 PM PDT 24
Peak memory 201180 kb
Host smart-49555690-c887-4135-be5e-5a490ff8d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531829007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.3531829007
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.650822459
Short name T628
Test name
Test status
Simulation time 11234825792 ps
CPU time 28.76 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201232 kb
Host smart-427271e5-ae0b-4985-bca3-eaae6db430fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650822459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.650822459
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3707368727
Short name T62
Test name
Test status
Simulation time 3800680533 ps
CPU time 6.96 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201264 kb
Host smart-7c1c0bcf-972d-49b4-bd0a-42d5edf87e0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707368727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.3707368727
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1049097221
Short name T718
Test name
Test status
Simulation time 2011787968 ps
CPU time 4.69 seconds
Started Jun 24 06:32:57 PM PDT 24
Finished Jun 24 06:33:04 PM PDT 24
Peak memory 201268 kb
Host smart-9660dbcd-5f43-43b9-aa47-7f246b6e4f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049097221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1049097221
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.4218058705
Short name T719
Test name
Test status
Simulation time 3501654301 ps
CPU time 3.07 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:03 PM PDT 24
Peak memory 201344 kb
Host smart-b33ce546-c041-4681-b49f-d8660dc92aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218058705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.4
218058705
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1897294540
Short name T465
Test name
Test status
Simulation time 204007452607 ps
CPU time 51.82 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:33:53 PM PDT 24
Peak memory 201432 kb
Host smart-e323b9bc-23a7-411f-9c6f-43da564dbb2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897294540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1897294540
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3508605528
Short name T521
Test name
Test status
Simulation time 38377376096 ps
CPU time 49.87 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 201536 kb
Host smart-6dd388e3-1b20-4f79-8f5c-c64ac4e3e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508605528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.3508605528
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1101829393
Short name T385
Test name
Test status
Simulation time 3770845128 ps
CPU time 2.15 seconds
Started Jun 24 06:32:53 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201236 kb
Host smart-9fed380e-6a87-429b-aed3-c3e5ecdae4cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101829393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1101829393
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1199328044
Short name T156
Test name
Test status
Simulation time 2691982892 ps
CPU time 1.2 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:33:03 PM PDT 24
Peak memory 201240 kb
Host smart-308bec06-7e1a-4548-888d-d6892fb1f78a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199328044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1199328044
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.4095089587
Short name T470
Test name
Test status
Simulation time 2635022742 ps
CPU time 1.83 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:32:56 PM PDT 24
Peak memory 201248 kb
Host smart-e3e5782c-1600-4851-ac5d-aa17e476e833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095089587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.4095089587
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1377588041
Short name T588
Test name
Test status
Simulation time 2482614018 ps
CPU time 1.72 seconds
Started Jun 24 06:32:57 PM PDT 24
Finished Jun 24 06:33:01 PM PDT 24
Peak memory 201264 kb
Host smart-e62152dd-b15c-428c-a764-a4b013712b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377588041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1377588041
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1785449003
Short name T776
Test name
Test status
Simulation time 2051337503 ps
CPU time 5.83 seconds
Started Jun 24 06:32:58 PM PDT 24
Finished Jun 24 06:33:05 PM PDT 24
Peak memory 201172 kb
Host smart-3df556e6-abc6-44d1-a04c-327f32f6cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785449003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1785449003
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1766285091
Short name T410
Test name
Test status
Simulation time 2511389371 ps
CPU time 7.08 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:08 PM PDT 24
Peak memory 201328 kb
Host smart-b7de70f5-8255-4066-a49c-2764cdbf37f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766285091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1766285091
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.35795762
Short name T472
Test name
Test status
Simulation time 2109475339 ps
CPU time 6.23 seconds
Started Jun 24 06:32:58 PM PDT 24
Finished Jun 24 06:33:06 PM PDT 24
Peak memory 201168 kb
Host smart-6c26912b-2e9d-4488-8a58-1cdc5b2e46c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35795762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.35795762
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1009392773
Short name T122
Test name
Test status
Simulation time 85885954867 ps
CPU time 57.73 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:58 PM PDT 24
Peak memory 209852 kb
Host smart-2026ca2f-d5f7-462f-aa86-b7059317350c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009392773 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1009392773
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3245952503
Short name T126
Test name
Test status
Simulation time 5437975577 ps
CPU time 1.38 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:02 PM PDT 24
Peak memory 201212 kb
Host smart-c86a3974-cf73-4589-aa0f-5d8147edbcd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245952503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3245952503
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.4068502354
Short name T642
Test name
Test status
Simulation time 2014432200 ps
CPU time 3.06 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201256 kb
Host smart-61331873-673f-4143-a3ca-839cc82d01aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068502354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.4068502354
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3523360135
Short name T605
Test name
Test status
Simulation time 3835314958 ps
CPU time 1.82 seconds
Started Jun 24 06:33:08 PM PDT 24
Finished Jun 24 06:33:10 PM PDT 24
Peak memory 201300 kb
Host smart-e9f3ddf7-d10a-4068-8684-6594fb2004c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523360135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.3
523360135
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1261813139
Short name T770
Test name
Test status
Simulation time 86741095021 ps
CPU time 113.77 seconds
Started Jun 24 06:33:08 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 201520 kb
Host smart-b19951df-2bb4-49bf-ab2d-97b32b24fc39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261813139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1261813139
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3239634874
Short name T14
Test name
Test status
Simulation time 25514220825 ps
CPU time 6.07 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:13 PM PDT 24
Peak memory 201600 kb
Host smart-25268b68-ff54-4aff-ae21-02d2d34fa507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239634874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.3239634874
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3460476818
Short name T771
Test name
Test status
Simulation time 2891567185 ps
CPU time 4.06 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:11 PM PDT 24
Peak memory 201148 kb
Host smart-8abf2a11-bc9d-4ee2-b0c6-04d255197793
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460476818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3460476818
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.1592174484
Short name T767
Test name
Test status
Simulation time 6449695333 ps
CPU time 2.53 seconds
Started Jun 24 06:33:01 PM PDT 24
Finished Jun 24 06:33:05 PM PDT 24
Peak memory 201240 kb
Host smart-b90e1506-7d99-40a0-8468-837116f1611f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592174484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.1592174484
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1217994966
Short name T741
Test name
Test status
Simulation time 2618845351 ps
CPU time 4.03 seconds
Started Jun 24 06:33:00 PM PDT 24
Finished Jun 24 06:33:05 PM PDT 24
Peak memory 201248 kb
Host smart-400e47c8-9ff6-474d-80ff-a15fbcdb5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217994966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1217994966
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1036885210
Short name T777
Test name
Test status
Simulation time 2468213525 ps
CPU time 6.65 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201256 kb
Host smart-8b655038-b350-4824-a91b-4d38364c7439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036885210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1036885210
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3592124994
Short name T381
Test name
Test status
Simulation time 2254173335 ps
CPU time 2.05 seconds
Started Jun 24 06:33:07 PM PDT 24
Finished Jun 24 06:33:10 PM PDT 24
Peak memory 201260 kb
Host smart-a4ee3123-94a3-4ccd-8b0c-f2065d1ff943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592124994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3592124994
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1390876377
Short name T562
Test name
Test status
Simulation time 2517690676 ps
CPU time 3.95 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:11 PM PDT 24
Peak memory 201324 kb
Host smart-11d56e62-2c6f-4cf2-b0e4-ec914f41892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390876377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1390876377
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.2515651088
Short name T666
Test name
Test status
Simulation time 2112209236 ps
CPU time 6.07 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:07 PM PDT 24
Peak memory 201140 kb
Host smart-16347edd-c268-4d61-8d78-15853c3968ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515651088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2515651088
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.896031237
Short name T755
Test name
Test status
Simulation time 6755185760 ps
CPU time 3.44 seconds
Started Jun 24 06:33:08 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201220 kb
Host smart-fd046296-910b-44a9-8bcc-18a575cd6964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896031237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_st
ress_all.896031237
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4279748185
Short name T208
Test name
Test status
Simulation time 387451590846 ps
CPU time 136.22 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:35:23 PM PDT 24
Peak memory 210932 kb
Host smart-0e99e1c6-fc8d-460f-993b-ca1c61df3620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279748185 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.4279748185
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.173518395
Short name T781
Test name
Test status
Simulation time 2719446634 ps
CPU time 1.25 seconds
Started Jun 24 06:32:59 PM PDT 24
Finished Jun 24 06:33:02 PM PDT 24
Peak memory 201244 kb
Host smart-d1e54265-2c54-456f-828b-e2cbb23b072b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173518395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ultra_low_pwr.173518395
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.334956451
Short name T700
Test name
Test status
Simulation time 2034820129 ps
CPU time 1.83 seconds
Started Jun 24 06:33:15 PM PDT 24
Finished Jun 24 06:33:18 PM PDT 24
Peak memory 201184 kb
Host smart-cc94a610-7ae5-4d9a-8111-a2752f6f3e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334956451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.334956451
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3716411470
Short name T760
Test name
Test status
Simulation time 3499497539 ps
CPU time 4.74 seconds
Started Jun 24 06:33:10 PM PDT 24
Finished Jun 24 06:33:16 PM PDT 24
Peak memory 201320 kb
Host smart-a36775fe-702a-4b33-bd83-072c6cf720cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716411470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
716411470
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.916827893
Short name T113
Test name
Test status
Simulation time 64254083570 ps
CPU time 53.14 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201300 kb
Host smart-a12e9cf1-c729-491a-a8c5-1a26e5a85093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916827893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.916827893
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3404531606
Short name T302
Test name
Test status
Simulation time 3896205957 ps
CPU time 2.83 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:13 PM PDT 24
Peak memory 201228 kb
Host smart-a069f3cf-8902-4da4-8499-02451f2b6847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404531606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3404531606
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3775963191
Short name T189
Test name
Test status
Simulation time 3090892641 ps
CPU time 3.58 seconds
Started Jun 24 06:33:12 PM PDT 24
Finished Jun 24 06:33:16 PM PDT 24
Peak memory 201264 kb
Host smart-574afa52-83c1-4b2e-97b6-1218d38374b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775963191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3775963191
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1022919629
Short name T438
Test name
Test status
Simulation time 2608183526 ps
CPU time 7.62 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:15 PM PDT 24
Peak memory 201256 kb
Host smart-805af2e4-43f2-4508-8121-b41a041c5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022919629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1022919629
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.3839280770
Short name T664
Test name
Test status
Simulation time 2516239492 ps
CPU time 1.4 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201220 kb
Host smart-d00bf69a-188d-4b86-bf26-3082b0a5dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839280770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.3839280770
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3020958829
Short name T19
Test name
Test status
Simulation time 2035124157 ps
CPU time 5.29 seconds
Started Jun 24 06:33:08 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201164 kb
Host smart-0980881b-87d0-4e2d-a7b1-1bf8403798a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020958829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3020958829
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2015807554
Short name T383
Test name
Test status
Simulation time 2552856160 ps
CPU time 1.79 seconds
Started Jun 24 06:33:05 PM PDT 24
Finished Jun 24 06:33:08 PM PDT 24
Peak memory 201308 kb
Host smart-036c6642-ba17-4aee-9617-cd15fe091b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015807554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2015807554
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.1069436334
Short name T712
Test name
Test status
Simulation time 2108148067 ps
CPU time 6.07 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:16 PM PDT 24
Peak memory 201136 kb
Host smart-2035f58c-b5b2-46c7-b2d1-235974a644de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069436334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1069436334
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3472872882
Short name T226
Test name
Test status
Simulation time 16926035309 ps
CPU time 36.25 seconds
Started Jun 24 06:33:17 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201372 kb
Host smart-5e321b24-6299-4989-b030-5cb6f79829cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472872882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3472872882
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3183647975
Short name T121
Test name
Test status
Simulation time 35509414465 ps
CPU time 73.1 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:34:24 PM PDT 24
Peak memory 217840 kb
Host smart-5e658d3d-96f4-4d3f-b21e-815074c3d3d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183647975 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3183647975
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2808880533
Short name T680
Test name
Test status
Simulation time 5313964050 ps
CPU time 2.16 seconds
Started Jun 24 06:33:10 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201240 kb
Host smart-3b8683e0-bf9a-4b2e-ae83-50e67cf5dba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808880533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2808880533
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.804217508
Short name T551
Test name
Test status
Simulation time 2024535530 ps
CPU time 3.04 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201000 kb
Host smart-dae9cc41-f65e-42b4-9f09-046fac887e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804217508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.804217508
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2064469134
Short name T706
Test name
Test status
Simulation time 3438068690 ps
CPU time 7.13 seconds
Started Jun 24 06:33:06 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201308 kb
Host smart-2723d8c4-4c87-4a7a-8895-b3a97b44c14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064469134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2
064469134
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2778085989
Short name T108
Test name
Test status
Simulation time 71572246124 ps
CPU time 89.34 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:34:40 PM PDT 24
Peak memory 201520 kb
Host smart-305fa438-4d70-4e36-88b0-a8d7ddb718d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778085989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.2778085989
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.25212467
Short name T412
Test name
Test status
Simulation time 2848247969 ps
CPU time 1.81 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201224 kb
Host smart-161caa63-a1d7-48e7-aacc-445beeeaef5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25212467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_ec_pwr_on_rst.25212467
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3759227584
Short name T448
Test name
Test status
Simulation time 2767128350 ps
CPU time 1.11 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201256 kb
Host smart-b93f6dae-cda9-4573-9a89-0c2964b57b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759227584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3759227584
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.1953433724
Short name T724
Test name
Test status
Simulation time 2472420886 ps
CPU time 2.26 seconds
Started Jun 24 06:33:15 PM PDT 24
Finished Jun 24 06:33:18 PM PDT 24
Peak memory 201192 kb
Host smart-f26000d2-7b2a-4b4c-9cc5-4eb884dbceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953433724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.1953433724
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.4012223983
Short name T729
Test name
Test status
Simulation time 2117424550 ps
CPU time 5.88 seconds
Started Jun 24 06:33:17 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201336 kb
Host smart-65882d5b-8b2c-4583-bcdd-918d247bb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012223983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.4012223983
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.386518599
Short name T216
Test name
Test status
Simulation time 2511331594 ps
CPU time 6.73 seconds
Started Jun 24 06:33:11 PM PDT 24
Finished Jun 24 06:33:19 PM PDT 24
Peak memory 201308 kb
Host smart-66fe6ea0-daba-454d-850f-33e6f7095cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386518599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.386518599
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.851966600
Short name T427
Test name
Test status
Simulation time 2109110294 ps
CPU time 5.6 seconds
Started Jun 24 06:33:12 PM PDT 24
Finished Jun 24 06:33:18 PM PDT 24
Peak memory 201156 kb
Host smart-58c72d68-26e1-46b7-b3b7-b0f65367cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851966600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.851966600
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1486049600
Short name T137
Test name
Test status
Simulation time 8432329679 ps
CPU time 6.4 seconds
Started Jun 24 06:33:17 PM PDT 24
Finished Jun 24 06:33:25 PM PDT 24
Peak memory 201364 kb
Host smart-9075857c-dffa-40f5-a904-897ec8c15b38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486049600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1486049600
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2269964508
Short name T693
Test name
Test status
Simulation time 2018315901 ps
CPU time 3.12 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:27 PM PDT 24
Peak memory 201252 kb
Host smart-80315894-b7d6-44ae-a33d-a5e4b581a951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269964508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2269964508
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.526866386
Short name T213
Test name
Test status
Simulation time 3139425067 ps
CPU time 1.67 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201316 kb
Host smart-50b4e8ac-3697-4291-82ea-62b158930163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526866386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.526866386
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.649067960
Short name T214
Test name
Test status
Simulation time 63458875889 ps
CPU time 168.15 seconds
Started Jun 24 06:33:18 PM PDT 24
Finished Jun 24 06:36:07 PM PDT 24
Peak memory 201484 kb
Host smart-916376f4-7629-4fa0-b0a4-cb83ae01952b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649067960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.649067960
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2371645312
Short name T190
Test name
Test status
Simulation time 112341445839 ps
CPU time 273.46 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:37:56 PM PDT 24
Peak memory 201528 kb
Host smart-df0dcfe4-3595-4e29-8970-cc5b6569c441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371645312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.2371645312
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1212185315
Short name T141
Test name
Test status
Simulation time 3640974338 ps
CPU time 9.85 seconds
Started Jun 24 06:33:08 PM PDT 24
Finished Jun 24 06:33:19 PM PDT 24
Peak memory 201228 kb
Host smart-9e39216e-62dc-4b92-ac32-580fac657c88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212185315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1212185315
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1277524795
Short name T240
Test name
Test status
Simulation time 4167581675 ps
CPU time 3.21 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:27 PM PDT 24
Peak memory 201232 kb
Host smart-77087059-1197-4d88-8e26-e402c91a0b46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277524795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1277524795
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.41685826
Short name T413
Test name
Test status
Simulation time 2643562824 ps
CPU time 2.02 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:13 PM PDT 24
Peak memory 201216 kb
Host smart-521ce444-f39d-4195-b307-7d8ec617bbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41685826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.41685826
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.117240776
Short name T763
Test name
Test status
Simulation time 2464003482 ps
CPU time 7.25 seconds
Started Jun 24 06:33:12 PM PDT 24
Finished Jun 24 06:33:20 PM PDT 24
Peak memory 201248 kb
Host smart-c39b46fc-8577-421e-a009-03532a49f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117240776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.117240776
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1818533058
Short name T506
Test name
Test status
Simulation time 2190189091 ps
CPU time 3.48 seconds
Started Jun 24 06:33:10 PM PDT 24
Finished Jun 24 06:33:15 PM PDT 24
Peak memory 201228 kb
Host smart-bf8af43d-ca23-4a10-8da1-2f1a0efcb53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818533058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1818533058
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2350863034
Short name T408
Test name
Test status
Simulation time 2535190307 ps
CPU time 2.07 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:13 PM PDT 24
Peak memory 201344 kb
Host smart-96b93248-e1ae-4e39-b6b8-83dcc1c135cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350863034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2350863034
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.1097368636
Short name T426
Test name
Test status
Simulation time 2128216112 ps
CPU time 1.88 seconds
Started Jun 24 06:33:09 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201204 kb
Host smart-308ab252-80b9-4cf8-a3b8-548b0f09a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097368636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1097368636
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.1595769897
Short name T638
Test name
Test status
Simulation time 135144386802 ps
CPU time 9.19 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:33:32 PM PDT 24
Peak memory 201228 kb
Host smart-768b9ff4-098f-463a-b517-24fcf67b9c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595769897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.1595769897
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3332397522
Short name T569
Test name
Test status
Simulation time 2463925068 ps
CPU time 2.01 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201260 kb
Host smart-38fbcdf0-0edc-4c95-b714-5f81893aa0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332397522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3332397522
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.448752274
Short name T415
Test name
Test status
Simulation time 2023141106 ps
CPU time 3 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201272 kb
Host smart-a39dfc04-bb5d-4931-b817-549abb235a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448752274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.448752274
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.358012175
Short name T615
Test name
Test status
Simulation time 262892909106 ps
CPU time 333.99 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:39:04 PM PDT 24
Peak memory 201232 kb
Host smart-a365fe40-67cb-425e-ae6c-6d4be8656d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358012175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.358012175
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1421186362
Short name T254
Test name
Test status
Simulation time 134886784960 ps
CPU time 70.69 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:34:41 PM PDT 24
Peak memory 201440 kb
Host smart-e3a7d0a6-1eeb-47b5-96fc-015debb077e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421186362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1421186362
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2729438910
Short name T502
Test name
Test status
Simulation time 27112168875 ps
CPU time 17.14 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:39 PM PDT 24
Peak memory 201620 kb
Host smart-a1eca68a-c42b-45ee-b098-1cc380b10251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729438910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.2729438910
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1713024329
Short name T620
Test name
Test status
Simulation time 2849723528 ps
CPU time 2.32 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201192 kb
Host smart-12f550a3-f87c-4ef9-8a75-bf713912a631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713024329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.1713024329
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.94854141
Short name T43
Test name
Test status
Simulation time 586643113457 ps
CPU time 61.22 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201268 kb
Host smart-12c79158-6847-4526-8cf6-5fe88dce65ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94854141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl
_edge_detect.94854141
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2163620211
Short name T543
Test name
Test status
Simulation time 2608213531 ps
CPU time 6.89 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:30 PM PDT 24
Peak memory 201248 kb
Host smart-93bcdad6-9c9d-4b8e-bdca-c9c7c2b3f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163620211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2163620211
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2495127841
Short name T67
Test name
Test status
Simulation time 2471441482 ps
CPU time 2.37 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201220 kb
Host smart-1ebcf3bc-8861-4d4c-b4b6-eae29ec07bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495127841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2495127841
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3243566597
Short name T236
Test name
Test status
Simulation time 2191932583 ps
CPU time 6.58 seconds
Started Jun 24 06:33:17 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201228 kb
Host smart-d24dc40b-3cc6-402c-8e76-817f089046e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243566597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3243566597
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.4210854660
Short name T528
Test name
Test status
Simulation time 2533915423 ps
CPU time 2.44 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201312 kb
Host smart-e2fe0646-809b-4a16-b26a-f7353b2eb1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210854660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.4210854660
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2071218608
Short name T211
Test name
Test status
Simulation time 2123106724 ps
CPU time 2.17 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201164 kb
Host smart-a93eafee-fe3e-410f-bda4-271f56b2584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071218608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2071218608
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3501147178
Short name T103
Test name
Test status
Simulation time 53794803129 ps
CPU time 32.09 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:52 PM PDT 24
Peak memory 217900 kb
Host smart-13525726-373c-4d46-8170-7a7177fa4cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501147178 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3501147178
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2451509109
Short name T125
Test name
Test status
Simulation time 10134207432 ps
CPU time 0.99 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201240 kb
Host smart-a44fd15a-c387-4ad9-8fb3-3832eb2fd126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451509109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2451509109
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.836712641
Short name T658
Test name
Test status
Simulation time 2018937667 ps
CPU time 3.09 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:33:25 PM PDT 24
Peak memory 201244 kb
Host smart-8fc5f04f-6f27-43da-bbe0-e4dbdef684c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836712641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.836712641
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3822633339
Short name T595
Test name
Test status
Simulation time 3432714064 ps
CPU time 2.29 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201344 kb
Host smart-00e3bb81-2d0f-4617-bfe6-3abed9eda0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822633339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
822633339
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.756870203
Short name T617
Test name
Test status
Simulation time 92727040444 ps
CPU time 29.17 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:33:52 PM PDT 24
Peak memory 201452 kb
Host smart-88af6e3d-b9ce-45f6-a680-a51d35f73108
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756870203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_combo_detect.756870203
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.279371036
Short name T165
Test name
Test status
Simulation time 3185222660 ps
CPU time 1.05 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:22 PM PDT 24
Peak memory 201260 kb
Host smart-b504c124-2b8e-40d9-a27d-1b1110d8eddd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279371036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.279371036
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.783940662
Short name T73
Test name
Test status
Simulation time 2375436747 ps
CPU time 6.75 seconds
Started Jun 24 06:33:18 PM PDT 24
Finished Jun 24 06:33:26 PM PDT 24
Peak memory 201240 kb
Host smart-c1181ee5-6341-4e6c-a252-660b2d7cd618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783940662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.783940662
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3450874987
Short name T446
Test name
Test status
Simulation time 2612167079 ps
CPU time 5.57 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:33:28 PM PDT 24
Peak memory 201240 kb
Host smart-558600c5-3c20-4c81-b619-82354df9ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450874987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3450874987
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3293543933
Short name T20
Test name
Test status
Simulation time 2466202918 ps
CPU time 6.55 seconds
Started Jun 24 06:33:23 PM PDT 24
Finished Jun 24 06:33:30 PM PDT 24
Peak memory 201432 kb
Host smart-14f8440a-31db-4293-a306-0808f5258968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293543933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3293543933
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.158291217
Short name T235
Test name
Test status
Simulation time 2098996097 ps
CPU time 5.4 seconds
Started Jun 24 06:33:18 PM PDT 24
Finished Jun 24 06:33:25 PM PDT 24
Peak memory 201116 kb
Host smart-de61d834-4352-456b-a6f7-7eacd7950998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158291217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.158291217
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.939688770
Short name T481
Test name
Test status
Simulation time 2515319334 ps
CPU time 7.22 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:29 PM PDT 24
Peak memory 201320 kb
Host smart-e666b1b3-a53a-4b86-91b7-88ae6630a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939688770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.939688770
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3245847877
Short name T691
Test name
Test status
Simulation time 2176768838 ps
CPU time 1.04 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201208 kb
Host smart-81b598e0-2c0d-49ea-8f55-ab3c6cf192cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245847877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3245847877
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.105179802
Short name T568
Test name
Test status
Simulation time 6484599203 ps
CPU time 5.26 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:29 PM PDT 24
Peak memory 201232 kb
Host smart-91a58a33-6b99-4b3a-87f6-d82fb326e1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105179802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_st
ress_all.105179802
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2112754497
Short name T93
Test name
Test status
Simulation time 6014168489 ps
CPU time 7.94 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:28 PM PDT 24
Peak memory 201220 kb
Host smart-d37b1c88-b028-4d8d-957d-f92154995e4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112754497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2112754497
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1173925186
Short name T555
Test name
Test status
Simulation time 2011799182 ps
CPU time 5.36 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201268 kb
Host smart-9f90a6d4-7dfb-41fa-8803-ef73abdab276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173925186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1173925186
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1254747777
Short name T50
Test name
Test status
Simulation time 3406149709 ps
CPU time 9.05 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201284 kb
Host smart-11239a8a-798c-4d6f-9f43-1a59e633b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254747777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1254747777
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.138904451
Short name T255
Test name
Test status
Simulation time 122949496738 ps
CPU time 154.54 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:35:04 PM PDT 24
Peak memory 201492 kb
Host smart-8bb5041f-6d1e-4192-a922-05ea667705d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138904451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.138904451
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2482496048
Short name T697
Test name
Test status
Simulation time 2434814101 ps
CPU time 6.34 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201240 kb
Host smart-cf89a43b-2830-4ec6-8bb4-009974886b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482496048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2482496048
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.518802405
Short name T613
Test name
Test status
Simulation time 2538331991 ps
CPU time 6.84 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201128 kb
Host smart-5eedf267-ab0c-421f-a6e3-ec65bc550371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518802405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.518802405
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2915878719
Short name T245
Test name
Test status
Simulation time 116807926340 ps
CPU time 44.86 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:33:19 PM PDT 24
Peak memory 201800 kb
Host smart-aeeb4190-5052-4e51-99c1-295e91cbc9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915878719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2915878719
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3648358172
Short name T428
Test name
Test status
Simulation time 3617715076 ps
CPU time 2.77 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:35 PM PDT 24
Peak memory 201216 kb
Host smart-a344975f-97c4-447e-8fa9-83c71b0cc6eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648358172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.3648358172
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.82924983
Short name T782
Test name
Test status
Simulation time 3192393365 ps
CPU time 2.19 seconds
Started Jun 24 06:32:32 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 201216 kb
Host smart-a3385772-9948-4981-8016-2b68f95d5a1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82924983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
edge_detect.82924983
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1854340089
Short name T766
Test name
Test status
Simulation time 2608482523 ps
CPU time 6.87 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201232 kb
Host smart-56e7105c-83ef-4d69-b5d6-2009759fd982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854340089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1854340089
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2332427046
Short name T738
Test name
Test status
Simulation time 2483253461 ps
CPU time 3.18 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:33 PM PDT 24
Peak memory 201244 kb
Host smart-b3cc925b-22af-442f-8e87-84f46f83b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332427046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2332427046
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2846102547
Short name T726
Test name
Test status
Simulation time 2019587739 ps
CPU time 3.22 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:35 PM PDT 24
Peak memory 201196 kb
Host smart-7ece3acb-dc09-44e8-8f29-22b239669779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846102547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2846102547
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1055471601
Short name T518
Test name
Test status
Simulation time 2512815646 ps
CPU time 7.02 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201204 kb
Host smart-fdf1c8e8-7314-479e-b7ac-0af61bdc1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055471601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1055471601
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.344525266
Short name T277
Test name
Test status
Simulation time 42324841131 ps
CPU time 13.7 seconds
Started Jun 24 06:32:28 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 220876 kb
Host smart-16408220-eacb-40ba-ab44-6d9a4f08d6c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344525266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.344525266
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.478297363
Short name T387
Test name
Test status
Simulation time 2130962583 ps
CPU time 2.09 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201356 kb
Host smart-d0163165-99ad-42d2-8ce6-a5a77590285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478297363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.478297363
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.864958080
Short name T174
Test name
Test status
Simulation time 100741150901 ps
CPU time 62.26 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201560 kb
Host smart-d95c702a-1410-4cbd-a5c7-4ba622fb9af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864958080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.864958080
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.770429977
Short name T564
Test name
Test status
Simulation time 6894717435 ps
CPU time 7.12 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201296 kb
Host smart-a285f534-27d0-4e2a-8733-3a88b56aa527
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770429977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.770429977
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3692648813
Short name T166
Test name
Test status
Simulation time 2014012213 ps
CPU time 5.6 seconds
Started Jun 24 06:33:33 PM PDT 24
Finished Jun 24 06:33:39 PM PDT 24
Peak memory 201240 kb
Host smart-7998c5f3-f2dd-4453-99ba-05ed320bedca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692648813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3692648813
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1051115810
Short name T679
Test name
Test status
Simulation time 3571084758 ps
CPU time 2.98 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201248 kb
Host smart-3c3fe0c0-503a-4c0d-9e81-863991390889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051115810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1
051115810
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1770973585
Short name T655
Test name
Test status
Simulation time 151745666068 ps
CPU time 97.17 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201448 kb
Host smart-fe8b6c8d-de7c-4928-bd52-25288d241e63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770973585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1770973585
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2560272390
Short name T523
Test name
Test status
Simulation time 22352713480 ps
CPU time 14.6 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201596 kb
Host smart-4191659b-1e33-482d-bf4c-ba756aa0e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560272390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2560272390
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4047443382
Short name T665
Test name
Test status
Simulation time 4384672158 ps
CPU time 2.15 seconds
Started Jun 24 06:33:21 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201232 kb
Host smart-3129cded-013a-4351-bbd7-acbcd3a26dc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047443382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.4047443382
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1442440803
Short name T44
Test name
Test status
Simulation time 2845747110 ps
CPU time 7.11 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:28 PM PDT 24
Peak memory 201228 kb
Host smart-178e57b0-8b2a-49c9-860c-3a4a64d2e950
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442440803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.1442440803
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2670307392
Short name T526
Test name
Test status
Simulation time 2609385693 ps
CPU time 6.88 seconds
Started Jun 24 06:33:22 PM PDT 24
Finished Jun 24 06:33:30 PM PDT 24
Peak memory 201248 kb
Host smart-82e1e403-7869-45e9-9785-8cefc40cd897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670307392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2670307392
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2073717162
Short name T681
Test name
Test status
Simulation time 2456482863 ps
CPU time 6.75 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:37 PM PDT 24
Peak memory 201192 kb
Host smart-2d4ae4e3-1a0c-49da-bc40-5d8a8729c0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073717162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.2073717162
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1375278288
Short name T547
Test name
Test status
Simulation time 2130004835 ps
CPU time 1.83 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201164 kb
Host smart-ef5c0aa8-a13f-428a-a548-0b21757bb260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375278288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1375278288
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.156649359
Short name T380
Test name
Test status
Simulation time 2511522746 ps
CPU time 6.63 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:28 PM PDT 24
Peak memory 201324 kb
Host smart-4a3876df-7421-4977-b4c2-27386c7560e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156649359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.156649359
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1234800639
Short name T517
Test name
Test status
Simulation time 2108060825 ps
CPU time 6.04 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:26 PM PDT 24
Peak memory 201172 kb
Host smart-89c983a8-a5d8-47f3-b8b1-f48d749bd929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234800639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1234800639
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1772295320
Short name T227
Test name
Test status
Simulation time 10131412962 ps
CPU time 2.81 seconds
Started Jun 24 06:33:20 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 201284 kb
Host smart-11a3b3aa-c2e8-44bf-a449-026335b0bdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772295320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1772295320
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1964568301
Short name T60
Test name
Test status
Simulation time 2473739351 ps
CPU time 5.92 seconds
Started Jun 24 06:33:19 PM PDT 24
Finished Jun 24 06:33:27 PM PDT 24
Peak memory 201272 kb
Host smart-0f6a19ad-e6c0-48a7-b585-897e7b26cb22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964568301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1964568301
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.195328662
Short name T704
Test name
Test status
Simulation time 2014741724 ps
CPU time 5.87 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:37 PM PDT 24
Peak memory 201232 kb
Host smart-016380bf-13d0-48d0-a7aa-bd76c956669f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195328662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_tes
t.195328662
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1294510688
Short name T594
Test name
Test status
Simulation time 3381536864 ps
CPU time 2.72 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201328 kb
Host smart-accc4294-92a5-4a49-9329-48b19822eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294510688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
294510688
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3888024030
Short name T606
Test name
Test status
Simulation time 66103872351 ps
CPU time 53.44 seconds
Started Jun 24 06:33:27 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201492 kb
Host smart-b6d82406-0ef1-4a18-ad21-4930f9b66502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888024030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3888024030
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2164647644
Short name T451
Test name
Test status
Simulation time 3634141429 ps
CPU time 9.69 seconds
Started Jun 24 06:33:33 PM PDT 24
Finished Jun 24 06:33:44 PM PDT 24
Peak memory 201232 kb
Host smart-c17ea4db-c522-49ef-bd20-68670d10558a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164647644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.2164647644
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.1488111827
Short name T45
Test name
Test status
Simulation time 4290167937 ps
CPU time 4.77 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:36 PM PDT 24
Peak memory 201256 kb
Host smart-7187d76e-fc55-4a84-866e-28b3154e3767
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488111827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.1488111827
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.556923483
Short name T69
Test name
Test status
Simulation time 2635596244 ps
CPU time 2.31 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:33:36 PM PDT 24
Peak memory 201252 kb
Host smart-184fc6a9-bd0a-43ff-84ff-a9fcfb471a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556923483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.556923483
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.1942913637
Short name T779
Test name
Test status
Simulation time 2486101138 ps
CPU time 4.1 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201264 kb
Host smart-fac4221b-c994-42d8-8a80-77155eb47707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942913637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1942913637
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2369492250
Short name T513
Test name
Test status
Simulation time 2092967434 ps
CPU time 3.04 seconds
Started Jun 24 06:33:30 PM PDT 24
Finished Jun 24 06:33:35 PM PDT 24
Peak memory 200972 kb
Host smart-ccd52a18-2408-4075-ba34-b4200b246a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369492250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2369492250
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.237370366
Short name T504
Test name
Test status
Simulation time 2512088583 ps
CPU time 7.89 seconds
Started Jun 24 06:33:27 PM PDT 24
Finished Jun 24 06:33:36 PM PDT 24
Peak memory 201320 kb
Host smart-7a06d85e-b3aa-4911-83e3-64ab11efbcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237370366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.237370366
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1735531278
Short name T636
Test name
Test status
Simulation time 2128004615 ps
CPU time 1.92 seconds
Started Jun 24 06:33:31 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201152 kb
Host smart-8c819c1f-4083-4af3-ba22-53b19985a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735531278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1735531278
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1189584902
Short name T417
Test name
Test status
Simulation time 8327300428 ps
CPU time 6 seconds
Started Jun 24 06:33:27 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201232 kb
Host smart-c50d1569-6c73-4af7-96c4-4777f26380cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189584902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1189584902
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.637234112
Short name T304
Test name
Test status
Simulation time 19240593193 ps
CPU time 52.43 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:34:26 PM PDT 24
Peak memory 210548 kb
Host smart-1db94e91-cab9-4a0b-b994-6caeeb70222d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637234112 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.637234112
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.475321806
Short name T75
Test name
Test status
Simulation time 9597288361 ps
CPU time 3.47 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201264 kb
Host smart-753d3d2d-e9fc-4c97-b3c2-f4b578364b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475321806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.475321806
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2159041837
Short name T420
Test name
Test status
Simulation time 2009214989 ps
CPU time 5.74 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201188 kb
Host smart-56afc238-4d1b-46c2-b2f4-bc83e074230b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159041837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2159041837
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2353183159
Short name T499
Test name
Test status
Simulation time 3669998382 ps
CPU time 8.78 seconds
Started Jun 24 06:33:31 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201332 kb
Host smart-3659a864-2d68-431b-a80f-82eb96ef1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353183159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
353183159
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1316617523
Short name T343
Test name
Test status
Simulation time 108788522504 ps
CPU time 65.85 seconds
Started Jun 24 06:33:27 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201416 kb
Host smart-f35ea4ff-318e-4c22-a074-13743f842771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316617523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1316617523
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.628254301
Short name T360
Test name
Test status
Simulation time 126712557815 ps
CPU time 304.15 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:38:35 PM PDT 24
Peak memory 201592 kb
Host smart-b1c35dbe-08ba-4977-84e3-2b8abbbd40e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628254301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_wi
th_pre_cond.628254301
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2813441165
Short name T560
Test name
Test status
Simulation time 2853681427 ps
CPU time 1.4 seconds
Started Jun 24 06:33:30 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201232 kb
Host smart-dd4ad06e-93b2-438b-8fb6-3dd79af33728
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813441165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.2813441165
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.880543348
Short name T757
Test name
Test status
Simulation time 612378289815 ps
CPU time 375.74 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:39:46 PM PDT 24
Peak memory 201216 kb
Host smart-3790cb36-4a7c-4e05-8235-d7b6c010421e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880543348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr
l_edge_detect.880543348
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1633851262
Short name T179
Test name
Test status
Simulation time 2614942853 ps
CPU time 7.47 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:33:40 PM PDT 24
Peak memory 201216 kb
Host smart-0f29b44d-8386-4c49-bde3-1717673cba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633851262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1633851262
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.51230216
Short name T297
Test name
Test status
Simulation time 2443513527 ps
CPU time 3.58 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:35 PM PDT 24
Peak memory 201252 kb
Host smart-5a7f29a8-dad7-466c-ad77-7f6fbda6fca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51230216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.51230216
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1784393391
Short name T791
Test name
Test status
Simulation time 2213328375 ps
CPU time 6.16 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:36 PM PDT 24
Peak memory 201236 kb
Host smart-b08ce4a8-31c4-4132-a2d9-54b7dd4c233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784393391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1784393391
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1511629679
Short name T314
Test name
Test status
Simulation time 2525649558 ps
CPU time 2.6 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201324 kb
Host smart-cf662aaf-525b-4d86-a8c5-0aeac846cdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511629679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1511629679
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1304469949
Short name T728
Test name
Test status
Simulation time 2112899510 ps
CPU time 5.49 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:36 PM PDT 24
Peak memory 201180 kb
Host smart-8ee4c93b-6cfb-4164-bdf5-b887b56d805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304469949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1304469949
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.4094395659
Short name T2
Test name
Test status
Simulation time 123904476300 ps
CPU time 72.05 seconds
Started Jun 24 06:33:33 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201540 kb
Host smart-0ad4514c-9609-4c8d-a8e4-8e87e77cac35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094395659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.4094395659
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3317056674
Short name T138
Test name
Test status
Simulation time 8457519948 ps
CPU time 2.32 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:31 PM PDT 24
Peak memory 201228 kb
Host smart-a46d6007-dcff-4bde-9aea-9dbc0df936b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317056674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3317056674
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2486512607
Short name T405
Test name
Test status
Simulation time 2033053716 ps
CPU time 1.86 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201264 kb
Host smart-4ac5c8e0-0d2c-4e3d-a705-fc9dddb06844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486512607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2486512607
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2134201858
Short name T645
Test name
Test status
Simulation time 3213157055 ps
CPU time 8.42 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:39 PM PDT 24
Peak memory 201332 kb
Host smart-7c8b10d5-3c56-4542-af0d-a01a3d61d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134201858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
134201858
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.49221776
Short name T346
Test name
Test status
Simulation time 187191624727 ps
CPU time 476.21 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 201564 kb
Host smart-c29e4b3a-a53f-4dd7-88d3-5cb313ddf7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49221776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_wit
h_pre_cond.49221776
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2794991087
Short name T140
Test name
Test status
Simulation time 5110750798 ps
CPU time 13.37 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:42 PM PDT 24
Peak memory 201236 kb
Host smart-46a0be95-63ab-4427-923b-241e4615058d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794991087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2794991087
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3681653953
Short name T46
Test name
Test status
Simulation time 2358388615 ps
CPU time 2.06 seconds
Started Jun 24 06:33:30 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201240 kb
Host smart-0aa78e64-a13e-4283-bf61-29ce70d1dd1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681653953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3681653953
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1201386517
Short name T522
Test name
Test status
Simulation time 2611973724 ps
CPU time 7.31 seconds
Started Jun 24 06:33:30 PM PDT 24
Finished Jun 24 06:33:39 PM PDT 24
Peak memory 201068 kb
Host smart-8603fa5b-4904-4889-bc90-a035210105d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201386517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1201386517
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.4099987077
Short name T710
Test name
Test status
Simulation time 2455716906 ps
CPU time 3.91 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201248 kb
Host smart-4adf6bfd-3ad0-42e0-aa79-ca30dd65727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099987077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4099987077
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2486025573
Short name T734
Test name
Test status
Simulation time 2103541497 ps
CPU time 3.49 seconds
Started Jun 24 06:33:29 PM PDT 24
Finished Jun 24 06:33:34 PM PDT 24
Peak memory 201172 kb
Host smart-7679cf45-561a-4223-b15e-92b234715982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486025573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2486025573
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2896727961
Short name T637
Test name
Test status
Simulation time 2514494642 ps
CPU time 3.81 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 201312 kb
Host smart-62dcd1c1-393e-4415-b986-c204fd7111f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896727961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2896727961
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3270012873
Short name T397
Test name
Test status
Simulation time 2110320742 ps
CPU time 6.39 seconds
Started Jun 24 06:33:30 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201160 kb
Host smart-7db02173-35e8-4369-8be9-65ad30f3fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270012873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3270012873
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1603538861
Short name T106
Test name
Test status
Simulation time 139687323940 ps
CPU time 172.44 seconds
Started Jun 24 06:33:31 PM PDT 24
Finished Jun 24 06:36:25 PM PDT 24
Peak memory 201548 kb
Host smart-20a212e2-f693-46dd-819e-d800594f499f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603538861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1603538861
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1780043526
Short name T321
Test name
Test status
Simulation time 24428119148 ps
CPU time 2.74 seconds
Started Jun 24 06:33:31 PM PDT 24
Finished Jun 24 06:33:35 PM PDT 24
Peak memory 201268 kb
Host smart-11005c1a-5f05-478a-8674-97d32fc66ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780043526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1780043526
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3585547109
Short name T378
Test name
Test status
Simulation time 2012198966 ps
CPU time 5.99 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:33:42 PM PDT 24
Peak memory 201252 kb
Host smart-c742eee3-688f-4597-81bb-43494d19b886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585547109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3585547109
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.622152858
Short name T752
Test name
Test status
Simulation time 59334848637 ps
CPU time 36.13 seconds
Started Jun 24 06:33:40 PM PDT 24
Finished Jun 24 06:34:17 PM PDT 24
Peak memory 201268 kb
Host smart-9848b420-8931-443f-a3e8-60d06f51226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622152858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.622152858
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3094140145
Short name T694
Test name
Test status
Simulation time 63195507558 ps
CPU time 44.84 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:34:24 PM PDT 24
Peak memory 201584 kb
Host smart-ba225279-2d79-4650-a499-3a1c9651fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094140145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3094140145
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.861290225
Short name T473
Test name
Test status
Simulation time 2937575158 ps
CPU time 8.09 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:45 PM PDT 24
Peak memory 201228 kb
Host smart-446e7f4e-8683-4493-ac24-d41bbf042403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861290225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.861290225
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3636899954
Short name T519
Test name
Test status
Simulation time 2613324155 ps
CPU time 7.55 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:33:44 PM PDT 24
Peak memory 201240 kb
Host smart-4082853f-faa0-41c9-8640-e83e6dfced7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636899954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3636899954
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3215409453
Short name T377
Test name
Test status
Simulation time 2457002502 ps
CPU time 3.88 seconds
Started Jun 24 06:33:27 PM PDT 24
Finished Jun 24 06:33:31 PM PDT 24
Peak memory 201264 kb
Host smart-769676c6-80f3-479c-9f17-fd0bd6228463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215409453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3215409453
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.967809176
Short name T439
Test name
Test status
Simulation time 2284624157 ps
CPU time 1.41 seconds
Started Jun 24 06:33:32 PM PDT 24
Finished Jun 24 06:33:35 PM PDT 24
Peak memory 201252 kb
Host smart-23751a6c-7b46-4502-ad1f-e99293bf9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967809176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.967809176
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.666820722
Short name T457
Test name
Test status
Simulation time 2521721920 ps
CPU time 2.6 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201304 kb
Host smart-44618ca7-d588-4e66-ae41-3873311af8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666820722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.666820722
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1905815083
Short name T394
Test name
Test status
Simulation time 2109994026 ps
CPU time 5.57 seconds
Started Jun 24 06:33:28 PM PDT 24
Finished Jun 24 06:33:35 PM PDT 24
Peak memory 201172 kb
Host smart-95ef1269-8cbf-4547-bcac-bcf77b8d05f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905815083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1905815083
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1902130193
Short name T139
Test name
Test status
Simulation time 602862816606 ps
CPU time 370.95 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:39:47 PM PDT 24
Peak memory 201236 kb
Host smart-b7029aa2-f70e-4062-aa0c-e395837841a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902130193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1902130193
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.89520631
Short name T267
Test name
Test status
Simulation time 65445748119 ps
CPU time 155.85 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:36:15 PM PDT 24
Peak memory 211496 kb
Host smart-43f869bc-f72f-404e-ad7b-16628cb73ed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89520631 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.89520631
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3666217884
Short name T7
Test name
Test status
Simulation time 222899736204 ps
CPU time 62.86 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:34:41 PM PDT 24
Peak memory 201200 kb
Host smart-81efecaf-5f6d-422d-a5f4-6cfc492ab21b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666217884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.3666217884
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2082532530
Short name T695
Test name
Test status
Simulation time 2034326406 ps
CPU time 1.92 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201236 kb
Host smart-cd5ab27d-83eb-46a3-82ab-7df665b15707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082532530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2082532530
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4281109794
Short name T124
Test name
Test status
Simulation time 3613649783 ps
CPU time 2.87 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:33:42 PM PDT 24
Peak memory 201316 kb
Host smart-80eb4b1e-449a-41e5-bceb-501120686880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281109794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4
281109794
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.3731533072
Short name T37
Test name
Test status
Simulation time 52180813689 ps
CPU time 40.79 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:34:19 PM PDT 24
Peak memory 201508 kb
Host smart-182794e2-bfbc-4a3a-aafa-58ea352b8880
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731533072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.3731533072
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.291171538
Short name T86
Test name
Test status
Simulation time 61029195738 ps
CPU time 151.32 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:36:11 PM PDT 24
Peak memory 201508 kb
Host smart-e9cfc352-1d9d-4291-a841-babfca0f4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291171538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.291171538
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.380523785
Short name T177
Test name
Test status
Simulation time 2752180123 ps
CPU time 1.78 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201428 kb
Host smart-c15201f4-5b63-415c-a14d-e4e1421cd43a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380523785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ec_pwr_on_rst.380523785
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2294845768
Short name T533
Test name
Test status
Simulation time 2929652565 ps
CPU time 7.54 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:33:46 PM PDT 24
Peak memory 201236 kb
Host smart-819f2555-5780-4f60-8774-8d9debcee4b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294845768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2294845768
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.505391812
Short name T55
Test name
Test status
Simulation time 2635696100 ps
CPU time 2.3 seconds
Started Jun 24 06:33:41 PM PDT 24
Finished Jun 24 06:33:44 PM PDT 24
Peak memory 201256 kb
Host smart-ccd8eb88-1862-49e1-9487-d8d178fe4761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505391812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.505391812
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1377379840
Short name T436
Test name
Test status
Simulation time 2486253409 ps
CPU time 2.19 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201260 kb
Host smart-30c8209c-607e-4e0f-a48a-2c4039615ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377379840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1377379840
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3793885306
Short name T16
Test name
Test status
Simulation time 2121804513 ps
CPU time 6.54 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:33:45 PM PDT 24
Peak memory 201368 kb
Host smart-b46e71d1-60a5-4215-a52a-465b5eb2aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793885306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3793885306
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2411115864
Short name T117
Test name
Test status
Simulation time 2523677900 ps
CPU time 2.22 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:39 PM PDT 24
Peak memory 201308 kb
Host smart-18226cb9-6553-487b-93d3-b66614c09ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411115864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2411115864
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.601530794
Short name T400
Test name
Test status
Simulation time 2136459058 ps
CPU time 1.84 seconds
Started Jun 24 06:33:40 PM PDT 24
Finished Jun 24 06:33:43 PM PDT 24
Peak memory 201176 kb
Host smart-2d672068-cd0c-4d93-beae-1bbe1f1c9642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601530794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.601530794
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1927393477
Short name T652
Test name
Test status
Simulation time 6719406045 ps
CPU time 18.1 seconds
Started Jun 24 06:33:35 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201232 kb
Host smart-281b2de3-64da-40f8-9efa-db8221fcf843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927393477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1927393477
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2321548715
Short name T306
Test name
Test status
Simulation time 75598570038 ps
CPU time 90.12 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:35:09 PM PDT 24
Peak memory 209828 kb
Host smart-fafb0aa1-e0dd-4f26-a386-cb01efab42f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321548715 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2321548715
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1938450187
Short name T29
Test name
Test status
Simulation time 3668849010 ps
CPU time 2.15 seconds
Started Jun 24 06:33:38 PM PDT 24
Finished Jun 24 06:33:41 PM PDT 24
Peak memory 201272 kb
Host smart-45f243d1-5f8f-4af1-a8f1-a552dd3af7c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938450187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.1938450187
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.3964319948
Short name T768
Test name
Test status
Simulation time 2030007632 ps
CPU time 1.87 seconds
Started Jun 24 06:33:48 PM PDT 24
Finished Jun 24 06:33:52 PM PDT 24
Peak memory 201236 kb
Host smart-8b812d3d-ac14-4c69-b3d8-673d32cfd7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964319948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.3964319948
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2853077007
Short name T411
Test name
Test status
Simulation time 3429913687 ps
CPU time 9.08 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:46 PM PDT 24
Peak memory 201312 kb
Host smart-83c50364-fcfb-4ea6-b2cc-35cd9671c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853077007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
853077007
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3867202200
Short name T99
Test name
Test status
Simulation time 141227127122 ps
CPU time 357.5 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 201500 kb
Host smart-afd41911-3333-42be-bf7c-6ada64ee59f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867202200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3867202200
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1608071401
Short name T788
Test name
Test status
Simulation time 23611639992 ps
CPU time 16.24 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201616 kb
Host smart-d8706b2c-bd7d-40c3-ac73-0a2a0de6e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608071401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1608071401
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.692066801
Short name T648
Test name
Test status
Simulation time 3437903001 ps
CPU time 5.03 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:33:43 PM PDT 24
Peak memory 201224 kb
Host smart-3854664a-11bb-49c5-a5b4-25147a31abe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692066801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.692066801
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1917656043
Short name T154
Test name
Test status
Simulation time 2393971711 ps
CPU time 6.45 seconds
Started Jun 24 06:35:09 PM PDT 24
Finished Jun 24 06:35:17 PM PDT 24
Peak memory 200204 kb
Host smart-c480b08e-c63d-4e30-ba7d-4440f0e1ea5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917656043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.1917656043
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3894925408
Short name T423
Test name
Test status
Simulation time 2611947712 ps
CPU time 7.11 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:44 PM PDT 24
Peak memory 201228 kb
Host smart-9de03c4f-1776-4715-989d-3f7e0db9fad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894925408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3894925408
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1635025981
Short name T548
Test name
Test status
Simulation time 2477111924 ps
CPU time 7.82 seconds
Started Jun 24 06:35:20 PM PDT 24
Finished Jun 24 06:35:30 PM PDT 24
Peak memory 200988 kb
Host smart-d8cadc99-2de2-4460-8cae-c6d7f2c43400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635025981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1635025981
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3059932102
Short name T656
Test name
Test status
Simulation time 2039654833 ps
CPU time 6.07 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:43 PM PDT 24
Peak memory 201168 kb
Host smart-b4c7edcc-f575-4dd8-9b12-2a7ea34930cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059932102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3059932102
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.4046191593
Short name T531
Test name
Test status
Simulation time 2512907031 ps
CPU time 5.41 seconds
Started Jun 24 06:33:37 PM PDT 24
Finished Jun 24 06:33:44 PM PDT 24
Peak memory 201312 kb
Host smart-6598b38f-d392-473c-ad60-afdb07271049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046191593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.4046191593
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3426293579
Short name T386
Test name
Test status
Simulation time 2125953040 ps
CPU time 2.04 seconds
Started Jun 24 06:33:40 PM PDT 24
Finished Jun 24 06:33:43 PM PDT 24
Peak memory 201176 kb
Host smart-0ec01254-b4ea-4a98-99d4-2796754629bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426293579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3426293579
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3595937913
Short name T370
Test name
Test status
Simulation time 9621125628 ps
CPU time 25.51 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:34:12 PM PDT 24
Peak memory 201316 kb
Host smart-8df96373-e23b-4333-94e9-16f5d38249b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595937913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3595937913
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3459052764
Short name T147
Test name
Test status
Simulation time 184316621958 ps
CPU time 288.73 seconds
Started Jun 24 06:33:44 PM PDT 24
Finished Jun 24 06:38:34 PM PDT 24
Peak memory 209900 kb
Host smart-8584dd90-9dce-499b-af82-1ca7f01fb142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459052764 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3459052764
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2805227479
Short name T696
Test name
Test status
Simulation time 3548696178 ps
CPU time 1.5 seconds
Started Jun 24 06:33:36 PM PDT 24
Finished Jun 24 06:33:38 PM PDT 24
Peak memory 201236 kb
Host smart-b2586270-a7b8-499e-94aa-8a8c29667a1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805227479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2805227479
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.456040427
Short name T758
Test name
Test status
Simulation time 2029401075 ps
CPU time 2.44 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:33:52 PM PDT 24
Peak memory 201244 kb
Host smart-52460846-162f-4ed5-ae89-ebcec14b7097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456040427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.456040427
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2269613050
Short name T206
Test name
Test status
Simulation time 3630475745 ps
CPU time 4.32 seconds
Started Jun 24 06:33:48 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201340 kb
Host smart-53ecc8ed-d396-4251-8296-1ab5d76c5db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269613050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
269613050
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1854689581
Short name T674
Test name
Test status
Simulation time 145273345130 ps
CPU time 91.03 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:35:19 PM PDT 24
Peak memory 201508 kb
Host smart-e08ad3ff-86a0-41bb-af7a-4a3040b301f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854689581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1854689581
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1474264700
Short name T36
Test name
Test status
Simulation time 85174499099 ps
CPU time 59.98 seconds
Started Jun 24 06:33:49 PM PDT 24
Finished Jun 24 06:34:50 PM PDT 24
Peak memory 201504 kb
Host smart-43925342-ab50-4e04-8a91-58e433898657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474264700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.1474264700
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2530267165
Short name T58
Test name
Test status
Simulation time 2724605099 ps
CPU time 2.07 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:33:49 PM PDT 24
Peak memory 201256 kb
Host smart-14afe0cf-380d-4b40-a326-5ad5f1a7580b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530267165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2530267165
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3799752014
Short name T601
Test name
Test status
Simulation time 2618063115 ps
CPU time 3.94 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201224 kb
Host smart-af3d0f2b-03ed-4086-9435-dc76d5f26c55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799752014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.3799752014
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.869541212
Short name T391
Test name
Test status
Simulation time 2685556601 ps
CPU time 1.32 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:33:48 PM PDT 24
Peak memory 201232 kb
Host smart-e85e4f2b-9743-4af5-ad83-12435f9c274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869541212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.869541212
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3506159063
Short name T22
Test name
Test status
Simulation time 2451543629 ps
CPU time 6.2 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:33:56 PM PDT 24
Peak memory 201148 kb
Host smart-af8d0350-e7ea-4b51-892c-3762bb40c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506159063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3506159063
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1995701874
Short name T644
Test name
Test status
Simulation time 2095728682 ps
CPU time 6 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:55 PM PDT 24
Peak memory 201164 kb
Host smart-24504e06-a0f8-4b2e-a296-d42efff2f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995701874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1995701874
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3522564576
Short name T557
Test name
Test status
Simulation time 2519881266 ps
CPU time 3.57 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:51 PM PDT 24
Peak memory 201324 kb
Host smart-45127e28-a8e3-48ef-a860-3d1771d325fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522564576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3522564576
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.144213283
Short name T701
Test name
Test status
Simulation time 2123393549 ps
CPU time 3.11 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:51 PM PDT 24
Peak memory 201132 kb
Host smart-74872c21-546e-42bd-b947-9bc6858acea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144213283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.144213283
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.4064393617
Short name T364
Test name
Test status
Simulation time 239077505606 ps
CPU time 125.23 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:35:52 PM PDT 24
Peak memory 201564 kb
Host smart-b314aa05-757c-42c5-8b4b-2de62b36cb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064393617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.4064393617
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.4114250646
Short name T89
Test name
Test status
Simulation time 189829200640 ps
CPU time 85.51 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:35:14 PM PDT 24
Peak memory 209804 kb
Host smart-ef441771-306e-49e2-90d8-f1aef9925506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114250646 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.4114250646
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.3228129003
Short name T612
Test name
Test status
Simulation time 2021046918 ps
CPU time 3.12 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:01 PM PDT 24
Peak memory 201244 kb
Host smart-bd861825-9dfa-4c9f-9b0d-f507ddcd1b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228129003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.3228129003
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4075957987
Short name T449
Test name
Test status
Simulation time 3238887948 ps
CPU time 7.34 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:33:54 PM PDT 24
Peak memory 201308 kb
Host smart-7f266bfd-a0a2-435d-99bb-97476ff375a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075957987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.4
075957987
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3975098108
Short name T487
Test name
Test status
Simulation time 162548828007 ps
CPU time 439.37 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:41:07 PM PDT 24
Peak memory 201468 kb
Host smart-c304dc03-98fa-407c-ade7-96c705ca6d0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975098108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.3975098108
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.680415526
Short name T461
Test name
Test status
Simulation time 2990839551 ps
CPU time 4.1 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:53 PM PDT 24
Peak memory 201196 kb
Host smart-1f45504f-9822-4907-93c1-b645ebcd593c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680415526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.680415526
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1489881455
Short name T238
Test name
Test status
Simulation time 4540206985 ps
CPU time 3.35 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:51 PM PDT 24
Peak memory 201224 kb
Host smart-593794cc-803f-49ab-b50f-60ffd6075fa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489881455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1489881455
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2056556115
Short name T486
Test name
Test status
Simulation time 2623835786 ps
CPU time 2.29 seconds
Started Jun 24 06:33:45 PM PDT 24
Finished Jun 24 06:33:50 PM PDT 24
Peak memory 201260 kb
Host smart-1c2e4432-e7d3-424f-b387-3c8bda9b3296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056556115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2056556115
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.3082403394
Short name T676
Test name
Test status
Simulation time 2503310861 ps
CPU time 1.41 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:50 PM PDT 24
Peak memory 201268 kb
Host smart-c9b05b96-c4ca-494d-babb-7b0bb50a3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082403394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3082403394
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.211772782
Short name T429
Test name
Test status
Simulation time 2115693981 ps
CPU time 5.98 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:33:55 PM PDT 24
Peak memory 201176 kb
Host smart-e5b21e44-64d3-4f07-b9e9-8cdd856002ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211772782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.211772782
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1645397228
Short name T172
Test name
Test status
Simulation time 2514395467 ps
CPU time 3.92 seconds
Started Jun 24 06:33:43 PM PDT 24
Finished Jun 24 06:33:49 PM PDT 24
Peak memory 201324 kb
Host smart-3437acaf-f977-4ac9-8aaf-f80fd8357dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645397228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1645397228
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.739662251
Short name T677
Test name
Test status
Simulation time 2110699304 ps
CPU time 5.87 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:33:55 PM PDT 24
Peak memory 201180 kb
Host smart-19a27012-ab6f-4991-8953-8a402198ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739662251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.739662251
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3655041167
Short name T207
Test name
Test status
Simulation time 91066456586 ps
CPU time 85.95 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:35:15 PM PDT 24
Peak memory 201444 kb
Host smart-154d0c40-c106-45af-8d26-748d4f38cc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655041167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3655041167
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2159473414
Short name T273
Test name
Test status
Simulation time 54423120489 ps
CPU time 30.52 seconds
Started Jun 24 06:33:46 PM PDT 24
Finished Jun 24 06:34:20 PM PDT 24
Peak memory 209868 kb
Host smart-b7a48e18-18de-4a05-bef5-ddc1b078e849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159473414 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2159473414
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.482284121
Short name T618
Test name
Test status
Simulation time 4986505476 ps
CPU time 3.36 seconds
Started Jun 24 06:33:47 PM PDT 24
Finished Jun 24 06:33:53 PM PDT 24
Peak memory 201036 kb
Host smart-de2bb757-204e-4ec4-b5cd-d6b9aa02e88c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482284121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ultra_low_pwr.482284121
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4058290854
Short name T747
Test name
Test status
Simulation time 2039775756 ps
CPU time 1.87 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 201252 kb
Host smart-a5c11605-d316-4363-8f59-17e02ad324e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058290854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4058290854
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1870972537
Short name T384
Test name
Test status
Simulation time 3275390883 ps
CPU time 8.96 seconds
Started Jun 24 06:33:54 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201316 kb
Host smart-f0194c0b-ccbc-4db0-a828-603a2d80749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870972537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
870972537
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.4137588879
Short name T266
Test name
Test status
Simulation time 82639146773 ps
CPU time 204.32 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:37:21 PM PDT 24
Peak memory 201432 kb
Host smart-c5016f01-076a-42bd-bd9d-fcc3b6693f73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137588879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.4137588879
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3563973870
Short name T355
Test name
Test status
Simulation time 132151116337 ps
CPU time 34.55 seconds
Started Jun 24 06:33:54 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201484 kb
Host smart-3281f272-7d79-467e-b24b-823853adf165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563973870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3563973870
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4057077653
Short name T714
Test name
Test status
Simulation time 4272292894 ps
CPU time 2.44 seconds
Started Jun 24 06:33:52 PM PDT 24
Finished Jun 24 06:33:55 PM PDT 24
Peak memory 201212 kb
Host smart-e87bb217-8bb0-4caf-86b7-2df3ec8acf3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057077653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.4057077653
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.14129743
Short name T220
Test name
Test status
Simulation time 3721230667 ps
CPU time 8.73 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201072 kb
Host smart-1f8ddc3f-c94a-4d66-85ed-56b7af1bd0ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14129743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl
_edge_detect.14129743
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1013823059
Short name T229
Test name
Test status
Simulation time 2609026994 ps
CPU time 7.37 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201176 kb
Host smart-8274f782-af17-4970-8d8a-fd715fb16723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013823059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1013823059
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3134405220
Short name T558
Test name
Test status
Simulation time 2467506624 ps
CPU time 4.37 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:03 PM PDT 24
Peak memory 201172 kb
Host smart-52c0587b-ca6d-4de0-b753-2890d71cd6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134405220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3134405220
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1803950737
Short name T452
Test name
Test status
Simulation time 2055537887 ps
CPU time 6.15 seconds
Started Jun 24 06:33:54 PM PDT 24
Finished Jun 24 06:34:01 PM PDT 24
Peak memory 201168 kb
Host smart-2bfe5043-e9aa-4f5f-bd5a-0f75a4cf1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803950737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1803950737
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3179330733
Short name T442
Test name
Test status
Simulation time 2523604396 ps
CPU time 3.48 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:33:58 PM PDT 24
Peak memory 201320 kb
Host smart-cf0054d8-9330-4746-ab31-8b25cb267459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179330733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3179330733
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3038165038
Short name T376
Test name
Test status
Simulation time 2120941791 ps
CPU time 3.17 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:01 PM PDT 24
Peak memory 201172 kb
Host smart-49cbcf70-7d49-450c-9092-c32e438e1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038165038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3038165038
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3000508799
Short name T611
Test name
Test status
Simulation time 6867803187 ps
CPU time 4.4 seconds
Started Jun 24 06:33:54 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 201248 kb
Host smart-e212b7b0-853e-4ba3-bd2d-66a37546f105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000508799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3000508799
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3236560466
Short name T87
Test name
Test status
Simulation time 81656603247 ps
CPU time 48.94 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 218020 kb
Host smart-f036d6cb-705a-494c-860c-394ce083d14e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236560466 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3236560466
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3021977074
Short name T675
Test name
Test status
Simulation time 7588837246 ps
CPU time 7.65 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:34:02 PM PDT 24
Peak memory 201256 kb
Host smart-b6cbb0ba-8529-45d8-9215-3b956ba96c95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021977074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.3021977074
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1010385215
Short name T774
Test name
Test status
Simulation time 2032139253 ps
CPU time 1.99 seconds
Started Jun 24 06:32:33 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 201268 kb
Host smart-561479b1-0f9b-4bb6-a29a-545ca5d516e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010385215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1010385215
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.484772612
Short name T709
Test name
Test status
Simulation time 3621228353 ps
CPU time 2.82 seconds
Started Jun 24 06:32:31 PM PDT 24
Finished Jun 24 06:32:34 PM PDT 24
Peak memory 201324 kb
Host smart-4ff54599-ca37-4e8e-8a83-48b963ae8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484772612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.484772612
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1207180106
Short name T181
Test name
Test status
Simulation time 108813645314 ps
CPU time 266.59 seconds
Started Jun 24 06:32:38 PM PDT 24
Finished Jun 24 06:37:06 PM PDT 24
Peak memory 201432 kb
Host smart-2a760ab9-245b-4593-bb66-4f129d4d809a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207180106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1207180106
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4076048294
Short name T466
Test name
Test status
Simulation time 2214189537 ps
CPU time 2.01 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:33 PM PDT 24
Peak memory 201212 kb
Host smart-a002de3e-cb03-4cac-8fd1-031e4eb88e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076048294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.4076048294
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1614969105
Short name T455
Test name
Test status
Simulation time 2522285846 ps
CPU time 2.21 seconds
Started Jun 24 06:32:30 PM PDT 24
Finished Jun 24 06:32:33 PM PDT 24
Peak memory 201248 kb
Host smart-bc4978d7-93ce-4428-a6e4-6b3aa081d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614969105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1614969105
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.603930205
Short name T248
Test name
Test status
Simulation time 129854738844 ps
CPU time 306.44 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:37:48 PM PDT 24
Peak memory 201580 kb
Host smart-4f6db41c-fe9d-45e9-b8ef-1331eaab2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603930205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wit
h_pre_cond.603930205
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2855814174
Short name T182
Test name
Test status
Simulation time 3347208501 ps
CPU time 1.79 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:32:37 PM PDT 24
Peak memory 201120 kb
Host smart-ddf550c8-434c-4072-b481-22e3398bb9bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855814174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2855814174
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2806756003
Short name T510
Test name
Test status
Simulation time 2614325108 ps
CPU time 7.88 seconds
Started Jun 24 06:32:29 PM PDT 24
Finished Jun 24 06:32:37 PM PDT 24
Peak memory 201244 kb
Host smart-72540c3b-50ef-44fb-af59-ca1c33142fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806756003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2806756003
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.4284328634
Short name T219
Test name
Test status
Simulation time 2455258261 ps
CPU time 7.31 seconds
Started Jun 24 06:32:32 PM PDT 24
Finished Jun 24 06:32:40 PM PDT 24
Peak memory 201228 kb
Host smart-58631c87-0e60-47e7-a183-6d85e4d059bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284328634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.4284328634
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1872265999
Short name T546
Test name
Test status
Simulation time 2254766080 ps
CPU time 1.11 seconds
Started Jun 24 06:32:32 PM PDT 24
Finished Jun 24 06:32:34 PM PDT 24
Peak memory 201264 kb
Host smart-848db449-7dba-42d0-a320-6f6fa26b6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872265999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1872265999
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1948982724
Short name T707
Test name
Test status
Simulation time 2514170939 ps
CPU time 6.44 seconds
Started Jun 24 06:32:28 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 201300 kb
Host smart-ac37a3bb-a978-46cc-a75c-02368607a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948982724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1948982724
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.289723880
Short name T296
Test name
Test status
Simulation time 42011691240 ps
CPU time 107.27 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 220564 kb
Host smart-af6d63dc-5b2a-4ed1-a75d-afd7fba1c2e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289723880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.289723880
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.912355665
Short name T659
Test name
Test status
Simulation time 2110405800 ps
CPU time 5.6 seconds
Started Jun 24 06:32:28 PM PDT 24
Finished Jun 24 06:32:34 PM PDT 24
Peak memory 201168 kb
Host smart-3f038f43-d4c9-4817-8793-1a1feed71d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912355665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.912355665
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.1091972394
Short name T158
Test name
Test status
Simulation time 14764437675 ps
CPU time 34.03 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201224 kb
Host smart-6421de1a-4e74-4d09-bd2b-cb074f4454b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091972394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.1091972394
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.815285700
Short name T316
Test name
Test status
Simulation time 4136773594 ps
CPU time 5.71 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:46 PM PDT 24
Peak memory 201232 kb
Host smart-b8d765b7-5eb6-4d4e-b84c-9af1c1bba276
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815285700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ultra_low_pwr.815285700
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2636135795
Short name T539
Test name
Test status
Simulation time 2018550986 ps
CPU time 3.24 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:01 PM PDT 24
Peak memory 201432 kb
Host smart-2e877080-4064-4973-be02-ccfedf8c65de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636135795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2636135795
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2007671817
Short name T144
Test name
Test status
Simulation time 3685355595 ps
CPU time 2.99 seconds
Started Jun 24 06:33:57 PM PDT 24
Finished Jun 24 06:34:02 PM PDT 24
Peak memory 201312 kb
Host smart-240869a4-085a-4e20-b11f-0130d5b61a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007671817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
007671817
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2398154070
Short name T491
Test name
Test status
Simulation time 110868290832 ps
CPU time 262.65 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:38:17 PM PDT 24
Peak memory 201508 kb
Host smart-a46e3e7f-063b-46b8-904d-36edf5047a49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398154070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.2398154070
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1175026115
Short name T367
Test name
Test status
Simulation time 32776972282 ps
CPU time 88.08 seconds
Started Jun 24 06:33:52 PM PDT 24
Finished Jun 24 06:35:21 PM PDT 24
Peak memory 201468 kb
Host smart-0c382bd5-caf0-4975-88f9-ca8d610922be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175026115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1175026115
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1958534474
Short name T552
Test name
Test status
Simulation time 3657262611 ps
CPU time 10.15 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201104 kb
Host smart-6daa4d0d-b4dd-4947-8059-105345d01e92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958534474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.1958534474
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1917934289
Short name T742
Test name
Test status
Simulation time 3309419785 ps
CPU time 2.62 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 200984 kb
Host smart-2a90032b-2bb3-4e28-86ca-969b48e85a99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917934289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1917934289
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3068815506
Short name T390
Test name
Test status
Simulation time 2626450910 ps
CPU time 2.28 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:33:58 PM PDT 24
Peak memory 201256 kb
Host smart-6d6767ae-b88b-4fc0-8d34-5fa44e308794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068815506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3068815506
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.759801167
Short name T554
Test name
Test status
Simulation time 2485259844 ps
CPU time 6.75 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201220 kb
Host smart-651b7f99-b641-43a0-8a98-fe6e45395c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759801167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.759801167
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1582667712
Short name T570
Test name
Test status
Simulation time 2105836894 ps
CPU time 1.93 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:33:56 PM PDT 24
Peak memory 201160 kb
Host smart-6593964b-4c2e-47d0-81d9-94546d272727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582667712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1582667712
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.581324274
Short name T315
Test name
Test status
Simulation time 2577191432 ps
CPU time 1.3 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:33:56 PM PDT 24
Peak memory 201324 kb
Host smart-5e888a5f-a59d-4eda-a026-ab929e31bac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581324274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.581324274
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.312781541
Short name T769
Test name
Test status
Simulation time 2111169018 ps
CPU time 6.04 seconds
Started Jun 24 06:33:52 PM PDT 24
Finished Jun 24 06:33:59 PM PDT 24
Peak memory 201188 kb
Host smart-66ec5d04-153e-49e8-8b7e-b3df60bb5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312781541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.312781541
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2652650047
Short name T480
Test name
Test status
Simulation time 13849318397 ps
CPU time 32.43 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:30 PM PDT 24
Peak memory 201292 kb
Host smart-dd839d31-a758-4ab7-b521-dfafdb8736c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652650047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2652650047
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2497083890
Short name T176
Test name
Test status
Simulation time 419199556582 ps
CPU time 127.38 seconds
Started Jun 24 06:33:54 PM PDT 24
Finished Jun 24 06:36:02 PM PDT 24
Peak memory 209764 kb
Host smart-276c3b9a-a20e-410b-a00f-9e4c4b15d520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497083890 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2497083890
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3074442052
Short name T24
Test name
Test status
Simulation time 3252641996 ps
CPU time 5.36 seconds
Started Jun 24 06:33:58 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201260 kb
Host smart-44d415d6-e4d3-4e66-ab7a-4079d7d1c7c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074442052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.3074442052
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.3628830840
Short name T497
Test name
Test status
Simulation time 2009475190 ps
CPU time 5.71 seconds
Started Jun 24 06:34:06 PM PDT 24
Finished Jun 24 06:34:13 PM PDT 24
Peak memory 201232 kb
Host smart-517e2488-3d0c-4e9b-870d-6d1012c5379a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628830840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.3628830840
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3021675775
Short name T572
Test name
Test status
Simulation time 115086600805 ps
CPU time 220.48 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:37:38 PM PDT 24
Peak memory 201308 kb
Host smart-4da4a088-2fc8-4b70-b168-778e483cfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021675775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
021675775
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2645114989
Short name T775
Test name
Test status
Simulation time 112000025028 ps
CPU time 259.97 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:38:16 PM PDT 24
Peak memory 201428 kb
Host smart-13bb7efc-65cd-496f-a24d-d9519f7d78d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645114989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.2645114989
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1937557216
Short name T97
Test name
Test status
Simulation time 24831974043 ps
CPU time 58.2 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:57 PM PDT 24
Peak memory 201584 kb
Host smart-a1e40c80-32c8-48c9-a62b-cca2adc3ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937557216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.1937557216
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1077465400
Short name T409
Test name
Test status
Simulation time 4071446061 ps
CPU time 3.09 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:01 PM PDT 24
Peak memory 201004 kb
Host smart-2a89768c-873d-48d2-a2a6-8976ae9761ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077465400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.1077465400
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.122052980
Short name T221
Test name
Test status
Simulation time 4877637534 ps
CPU time 13.59 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:12 PM PDT 24
Peak memory 201236 kb
Host smart-d76d7d13-0385-44ad-86cd-556da044892d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122052980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.122052980
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2134734280
Short name T70
Test name
Test status
Simulation time 2610391111 ps
CPU time 5.12 seconds
Started Jun 24 06:33:58 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201268 kb
Host smart-a12f27b7-6842-4118-aa77-95df2ba5adb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134734280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2134734280
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2604412668
Short name T433
Test name
Test status
Simulation time 2460313409 ps
CPU time 4.34 seconds
Started Jun 24 06:33:53 PM PDT 24
Finished Jun 24 06:33:59 PM PDT 24
Peak memory 201252 kb
Host smart-c2ba0b0c-d9d5-4cfa-a2e4-39f3e292ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604412668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2604412668
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2397227272
Short name T516
Test name
Test status
Simulation time 2045655977 ps
CPU time 5.88 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:03 PM PDT 24
Peak memory 201180 kb
Host smart-03ca920f-2c68-45d1-be72-676dc6d7e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397227272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2397227272
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3063622094
Short name T746
Test name
Test status
Simulation time 2509227618 ps
CPU time 6.89 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:03 PM PDT 24
Peak memory 201324 kb
Host smart-c727733e-ec3e-4a34-aa9c-0aee55f2f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063622094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3063622094
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3224208369
Short name T460
Test name
Test status
Simulation time 2108749194 ps
CPU time 5.81 seconds
Started Jun 24 06:33:55 PM PDT 24
Finished Jun 24 06:34:03 PM PDT 24
Peak memory 201152 kb
Host smart-caa1517d-8f3a-498e-8b13-16bed1365dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224208369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3224208369
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3815217270
Short name T443
Test name
Test status
Simulation time 12970516834 ps
CPU time 16.72 seconds
Started Jun 24 06:34:04 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201292 kb
Host smart-78f7393e-3d15-4c66-8b10-e11839215dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815217270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3815217270
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3385070875
Short name T61
Test name
Test status
Simulation time 4258889544 ps
CPU time 6.43 seconds
Started Jun 24 06:33:56 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201232 kb
Host smart-a5eebbe0-2ded-434e-8a1f-687bc0c4f6f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385070875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3385070875
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.4150327064
Short name T748
Test name
Test status
Simulation time 2009994609 ps
CPU time 5.48 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:08 PM PDT 24
Peak memory 201408 kb
Host smart-77ba2274-99b1-4b6a-80bd-54201a478cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150327064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.4150327064
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.805329759
Short name T203
Test name
Test status
Simulation time 3491269838 ps
CPU time 9.19 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:14 PM PDT 24
Peak memory 201236 kb
Host smart-5afb88b5-5166-4123-978e-89e9a20774e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805329759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.805329759
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1219124237
Short name T623
Test name
Test status
Simulation time 158153691145 ps
CPU time 42.55 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201428 kb
Host smart-b208119b-2297-44c0-b0cb-4d748f150cf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219124237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.1219124237
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2390951896
Short name T357
Test name
Test status
Simulation time 84760661738 ps
CPU time 60.7 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:35:05 PM PDT 24
Peak memory 201580 kb
Host smart-60c86cde-70d7-4fcb-a6db-4e17acf7037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390951896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.2390951896
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1551846806
Short name T663
Test name
Test status
Simulation time 4550688854 ps
CPU time 2.37 seconds
Started Jun 24 06:34:05 PM PDT 24
Finished Jun 24 06:34:08 PM PDT 24
Peak memory 201212 kb
Host smart-02066aa0-988f-47c4-9902-5588d3a79e79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551846806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.1551846806
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1414456697
Short name T524
Test name
Test status
Simulation time 3006613358 ps
CPU time 1.42 seconds
Started Jun 24 06:34:00 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201260 kb
Host smart-ee9d5bc7-5e43-426a-aee1-5cebd5d96cc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414456697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1414456697
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3534712647
Short name T530
Test name
Test status
Simulation time 2631477718 ps
CPU time 2.21 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201212 kb
Host smart-90b9183c-7496-4425-8b6f-076be33fa96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534712647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3534712647
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1243038245
Short name T201
Test name
Test status
Simulation time 2455562761 ps
CPU time 3.78 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:08 PM PDT 24
Peak memory 201252 kb
Host smart-1dd534f0-0f41-4829-aaf2-7ed54c8bfa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243038245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1243038245
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1653940613
Short name T703
Test name
Test status
Simulation time 2096372452 ps
CPU time 3.05 seconds
Started Jun 24 06:34:02 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201200 kb
Host smart-76427e08-f039-47ab-a565-8653350ed320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653940613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1653940613
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2811741037
Short name T711
Test name
Test status
Simulation time 2520516539 ps
CPU time 2.32 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201324 kb
Host smart-2f0895de-bd5d-4ebe-bced-11f1430d9eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811741037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2811741037
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.4098144363
Short name T735
Test name
Test status
Simulation time 2126412532 ps
CPU time 1.92 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201356 kb
Host smart-c262c27f-493a-4c6f-84aa-c7efab745b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098144363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.4098144363
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.778748762
Short name T626
Test name
Test status
Simulation time 225971251957 ps
CPU time 231.57 seconds
Started Jun 24 06:34:00 PM PDT 24
Finished Jun 24 06:37:53 PM PDT 24
Peak memory 201280 kb
Host smart-31080d0f-5962-4eb4-9f14-b24005ee5e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778748762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.778748762
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2822148080
Short name T324
Test name
Test status
Simulation time 391973022562 ps
CPU time 94.86 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:35:39 PM PDT 24
Peak memory 209768 kb
Host smart-75b9e89d-94bf-42f5-bb96-e34677358acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822148080 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2822148080
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2467049398
Short name T320
Test name
Test status
Simulation time 4579060171 ps
CPU time 2.59 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:05 PM PDT 24
Peak memory 201236 kb
Host smart-a89078e3-6bb7-46aa-a1f3-359885e804c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467049398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2467049398
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1503913553
Short name T232
Test name
Test status
Simulation time 2014173448 ps
CPU time 5.48 seconds
Started Jun 24 06:34:00 PM PDT 24
Finished Jun 24 06:34:07 PM PDT 24
Peak memory 201260 kb
Host smart-5cc11854-2f6b-4192-b1ec-b7ac526de6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503913553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1503913553
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.4070000107
Short name T225
Test name
Test status
Simulation time 3538847692 ps
CPU time 5.23 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:10 PM PDT 24
Peak memory 201292 kb
Host smart-c4507521-913d-49c6-9b80-66c4a654faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070000107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.4
070000107
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3264119
Short name T643
Test name
Test status
Simulation time 98460148346 ps
CPU time 58.55 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:35:01 PM PDT 24
Peak memory 201508 kb
Host smart-45a9910f-dd36-4fa0-8167-08da47efdace
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl
_combo_detect.3264119
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1117610286
Short name T542
Test name
Test status
Simulation time 2534750241 ps
CPU time 2.03 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:07 PM PDT 24
Peak memory 201164 kb
Host smart-a1029b97-d760-4b83-80c2-0ec6dc05bb64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117610286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1117610286
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1924141538
Short name T72
Test name
Test status
Simulation time 5496903268 ps
CPU time 2.1 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201232 kb
Host smart-39dcba10-e019-41e1-9aab-59cf6e63a961
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924141538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1924141538
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3543450932
Short name T535
Test name
Test status
Simulation time 2618221689 ps
CPU time 4.26 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:08 PM PDT 24
Peak memory 201244 kb
Host smart-6f235e98-4803-44f9-b220-828490fc0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543450932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3543450932
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2716021459
Short name T185
Test name
Test status
Simulation time 2453949537 ps
CPU time 6.68 seconds
Started Jun 24 06:34:06 PM PDT 24
Finished Jun 24 06:34:13 PM PDT 24
Peak memory 201264 kb
Host smart-12c06535-1241-48c4-a003-d15264d80a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716021459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2716021459
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3915992504
Short name T5
Test name
Test status
Simulation time 2050043630 ps
CPU time 1.91 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201164 kb
Host smart-6d2b1288-5e9d-401e-946e-a6d0f3ddc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915992504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3915992504
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1161778917
Short name T688
Test name
Test status
Simulation time 2524685723 ps
CPU time 2.24 seconds
Started Jun 24 06:34:03 PM PDT 24
Finished Jun 24 06:34:07 PM PDT 24
Peak memory 201304 kb
Host smart-9431867b-43a7-4657-9521-0c22e6b7b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161778917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1161778917
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2621465500
Short name T622
Test name
Test status
Simulation time 2112202486 ps
CPU time 6.11 seconds
Started Jun 24 06:34:06 PM PDT 24
Finished Jun 24 06:34:13 PM PDT 24
Peak memory 201144 kb
Host smart-08a58bb7-8c81-4799-9dcf-1a34797d7e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621465500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2621465500
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3784270860
Short name T307
Test name
Test status
Simulation time 15122957028 ps
CPU time 11.24 seconds
Started Jun 24 06:34:02 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201284 kb
Host smart-413598a6-78c7-4179-bf57-73f05431d79b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784270860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3784270860
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.4162499330
Short name T635
Test name
Test status
Simulation time 2040907600 ps
CPU time 1.53 seconds
Started Jun 24 06:34:09 PM PDT 24
Finished Jun 24 06:34:12 PM PDT 24
Peak memory 201212 kb
Host smart-ece16137-199b-44fa-a4a4-7832819139e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162499330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.4162499330
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.757889873
Short name T500
Test name
Test status
Simulation time 3335817595 ps
CPU time 1.24 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201328 kb
Host smart-d08a3cb8-9eee-4b3c-93ff-d9a2ece6ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757889873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.757889873
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1890068838
Short name T783
Test name
Test status
Simulation time 109979143758 ps
CPU time 76.6 seconds
Started Jun 24 06:34:09 PM PDT 24
Finished Jun 24 06:35:27 PM PDT 24
Peak memory 201424 kb
Host smart-5609243b-143e-4818-8785-f5aafe5db7b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890068838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1890068838
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.685252874
Short name T9
Test name
Test status
Simulation time 105031442545 ps
CPU time 264.53 seconds
Started Jun 24 06:34:10 PM PDT 24
Finished Jun 24 06:38:36 PM PDT 24
Peak memory 201616 kb
Host smart-1168b82f-bcf2-4094-95a0-52b47d56bd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685252874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_wi
th_pre_cond.685252874
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.730974206
Short name T624
Test name
Test status
Simulation time 3188173390 ps
CPU time 2.5 seconds
Started Jun 24 06:34:09 PM PDT 24
Finished Jun 24 06:34:13 PM PDT 24
Peak memory 201256 kb
Host smart-b55ad3cc-16ee-46e9-86bb-ac912541e361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730974206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ec_pwr_on_rst.730974206
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1010691344
Short name T68
Test name
Test status
Simulation time 2612321258 ps
CPU time 6.6 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:20 PM PDT 24
Peak memory 201168 kb
Host smart-4d7bec1b-136e-4bfd-9651-5cf615f6503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010691344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1010691344
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2176266890
Short name T515
Test name
Test status
Simulation time 2449995607 ps
CPU time 7.06 seconds
Started Jun 24 06:34:02 PM PDT 24
Finished Jun 24 06:34:11 PM PDT 24
Peak memory 201236 kb
Host smart-7ab3bb1d-7d51-48e1-bfb3-517cc4dc3c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176266890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2176266890
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2525097330
Short name T720
Test name
Test status
Simulation time 2116093272 ps
CPU time 2.29 seconds
Started Jun 24 06:34:02 PM PDT 24
Finished Jun 24 06:34:06 PM PDT 24
Peak memory 201164 kb
Host smart-2b813b2a-f611-4fb9-af57-b684435a114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525097330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2525097330
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.254453474
Short name T393
Test name
Test status
Simulation time 2615138099 ps
CPU time 1.26 seconds
Started Jun 24 06:34:05 PM PDT 24
Finished Jun 24 06:34:08 PM PDT 24
Peak memory 201324 kb
Host smart-aaf69f91-f9e6-4657-8b74-3c01eff82124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254453474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.254453474
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.751415458
Short name T414
Test name
Test status
Simulation time 2126706696 ps
CPU time 1.63 seconds
Started Jun 24 06:34:01 PM PDT 24
Finished Jun 24 06:34:04 PM PDT 24
Peak memory 201168 kb
Host smart-7e9b9279-5666-4337-a8b3-54d636acb86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751415458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.751415458
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.895943718
Short name T169
Test name
Test status
Simulation time 8294803479 ps
CPU time 5.99 seconds
Started Jun 24 06:34:14 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201296 kb
Host smart-a04d9ed2-6475-4c3b-9c98-31c239399210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895943718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_st
ress_all.895943718
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2455781482
Short name T373
Test name
Test status
Simulation time 1867493386319 ps
CPU time 120.9 seconds
Started Jun 24 06:34:09 PM PDT 24
Finished Jun 24 06:36:11 PM PDT 24
Peak memory 201272 kb
Host smart-922315ec-255c-4ccb-a735-c7ea60b23945
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455781482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2455781482
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2975487848
Short name T600
Test name
Test status
Simulation time 2036471275 ps
CPU time 1.93 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:16 PM PDT 24
Peak memory 201244 kb
Host smart-b5c50079-6f75-473c-a568-d23fab0d7b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975487848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2975487848
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3490378408
Short name T772
Test name
Test status
Simulation time 3328650346 ps
CPU time 1.43 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:14 PM PDT 24
Peak memory 201300 kb
Host smart-1234c18d-9f34-431b-b744-9ff879102c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490378408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
490378408
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.393224435
Short name T250
Test name
Test status
Simulation time 82484558733 ps
CPU time 52.97 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:35:05 PM PDT 24
Peak memory 201416 kb
Host smart-e9c3a3c2-1582-49a9-9d8d-90cd27ba9a0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393224435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.393224435
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.766823179
Short name T493
Test name
Test status
Simulation time 33595343897 ps
CPU time 80.92 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:35:35 PM PDT 24
Peak memory 201624 kb
Host smart-85c3be52-4685-4991-8c7a-7a367cb8a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766823179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.766823179
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.92583523
Short name T745
Test name
Test status
Simulation time 3828840281 ps
CPU time 5.15 seconds
Started Jun 24 06:34:10 PM PDT 24
Finished Jun 24 06:34:16 PM PDT 24
Peak memory 201232 kb
Host smart-da9e94e9-a820-4738-835d-dd6d7137570c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92583523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_ec_pwr_on_rst.92583523
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.1113483479
Short name T11
Test name
Test status
Simulation time 3192582829 ps
CPU time 2.59 seconds
Started Jun 24 06:34:10 PM PDT 24
Finished Jun 24 06:34:14 PM PDT 24
Peak memory 201364 kb
Host smart-a90ebf93-0893-4410-bc03-f1c73a7764d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113483479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.1113483479
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1861931363
Short name T312
Test name
Test status
Simulation time 2627039681 ps
CPU time 2.44 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201224 kb
Host smart-f85df52f-3a17-4dfe-aa0f-acc355d45aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861931363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1861931363
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1775751415
Short name T65
Test name
Test status
Simulation time 2467737970 ps
CPU time 2.28 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201260 kb
Host smart-57ff8d85-62bb-40b0-a220-825b8d451ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775751415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1775751415
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1256891862
Short name T317
Test name
Test status
Simulation time 2232617246 ps
CPU time 3.36 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:16 PM PDT 24
Peak memory 201236 kb
Host smart-d0a3ea91-4d39-4397-bc41-c43693680ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256891862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1256891862
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1438364899
Short name T311
Test name
Test status
Simulation time 2526619384 ps
CPU time 2.33 seconds
Started Jun 24 06:34:15 PM PDT 24
Finished Jun 24 06:34:19 PM PDT 24
Peak memory 201312 kb
Host smart-1150a073-ec23-4796-a1b1-3556055ed2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438364899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1438364899
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3553901210
Short name T318
Test name
Test status
Simulation time 2121551998 ps
CPU time 3.38 seconds
Started Jun 24 06:34:10 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201172 kb
Host smart-4fb5677c-23cc-48af-b535-1068d5196484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553901210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3553901210
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2195107536
Short name T388
Test name
Test status
Simulation time 16070125160 ps
CPU time 11.46 seconds
Started Jun 24 06:34:13 PM PDT 24
Finished Jun 24 06:34:26 PM PDT 24
Peak memory 201296 kb
Host smart-cf56e895-7ca3-4611-a2dd-42ffd1c7913b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195107536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2195107536
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2137726568
Short name T78
Test name
Test status
Simulation time 29022561132 ps
CPU time 58.17 seconds
Started Jun 24 06:34:15 PM PDT 24
Finished Jun 24 06:35:14 PM PDT 24
Peak memory 217988 kb
Host smart-8f3c715b-d6a8-4f81-8067-1d1b05e6cec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137726568 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2137726568
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3324674541
Short name T778
Test name
Test status
Simulation time 4418131610 ps
CPU time 1.38 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 201240 kb
Host smart-a049bff4-e20b-488e-97b1-924160415a4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324674541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3324674541
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2403187072
Short name T450
Test name
Test status
Simulation time 2021650884 ps
CPU time 2.51 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:26 PM PDT 24
Peak memory 201252 kb
Host smart-fa701073-1794-4426-aed3-8757ffe55550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403187072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2403187072
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3244448500
Short name T699
Test name
Test status
Simulation time 3731724216 ps
CPU time 2.82 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:30 PM PDT 24
Peak memory 201336 kb
Host smart-969a65c0-3714-42e0-a926-65e48884e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244448500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
244448500
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3196323821
Short name T110
Test name
Test status
Simulation time 25082412684 ps
CPU time 15.39 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:41 PM PDT 24
Peak memory 201432 kb
Host smart-e7a4d343-77fe-4b4d-b0e1-ffc557dd73f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196323821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3196323821
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.784998031
Short name T115
Test name
Test status
Simulation time 2556834968 ps
CPU time 3.57 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:16 PM PDT 24
Peak memory 201228 kb
Host smart-5bee7041-4cdf-4f3e-9795-e7bc79b6e193
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784998031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.784998031
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2693302839
Short name T149
Test name
Test status
Simulation time 3103202898 ps
CPU time 4.24 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:28 PM PDT 24
Peak memory 201240 kb
Host smart-bc238b3b-b169-41eb-941b-cb4aac024fb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693302839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2693302839
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2028149748
Short name T260
Test name
Test status
Simulation time 2610541098 ps
CPU time 7.48 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201428 kb
Host smart-87302b66-10d1-45f3-bca1-558e5f64acb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028149748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2028149748
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2843225872
Short name T298
Test name
Test status
Simulation time 2478169991 ps
CPU time 2.4 seconds
Started Jun 24 06:34:11 PM PDT 24
Finished Jun 24 06:34:16 PM PDT 24
Peak memory 201224 kb
Host smart-dcd0b819-95fa-4281-b882-e7adc2c3c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843225872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2843225872
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1654730597
Short name T702
Test name
Test status
Simulation time 2100594645 ps
CPU time 2.69 seconds
Started Jun 24 06:34:13 PM PDT 24
Finished Jun 24 06:34:17 PM PDT 24
Peak memory 201168 kb
Host smart-6635f1bc-3d7d-4837-a050-d1c9eb58871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654730597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1654730597
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2790354250
Short name T596
Test name
Test status
Simulation time 2513568410 ps
CPU time 7.34 seconds
Started Jun 24 06:34:10 PM PDT 24
Finished Jun 24 06:34:19 PM PDT 24
Peak memory 201316 kb
Host smart-8d7495ae-a654-4d54-ba26-6a782bc172cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790354250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2790354250
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.549006481
Short name T668
Test name
Test status
Simulation time 2109280957 ps
CPU time 5.03 seconds
Started Jun 24 06:34:12 PM PDT 24
Finished Jun 24 06:34:18 PM PDT 24
Peak memory 201172 kb
Host smart-5082dbc7-36b3-4177-9eb3-8ad7fd44c16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549006481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.549006481
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.766777858
Short name T463
Test name
Test status
Simulation time 153074184224 ps
CPU time 371.7 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:40:37 PM PDT 24
Peak memory 201428 kb
Host smart-be8e7ba2-38ed-4112-90cb-d580fe2a5366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766777858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_st
ress_all.766777858
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.106438559
Short name T76
Test name
Test status
Simulation time 4532712302 ps
CPU time 1.45 seconds
Started Jun 24 06:34:18 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201216 kb
Host smart-f63a4b08-30d6-47ae-9b0d-b2c0e68e9d85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106438559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ultra_low_pwr.106438559
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.2557365356
Short name T580
Test name
Test status
Simulation time 2070235119 ps
CPU time 1.44 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:26 PM PDT 24
Peak memory 201264 kb
Host smart-ab7f56f3-cbfc-4275-9e7d-c9fb1607217f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557365356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.2557365356
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3057562634
Short name T30
Test name
Test status
Simulation time 3669759485 ps
CPU time 10.32 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:37 PM PDT 24
Peak memory 201328 kb
Host smart-f5c8e6b3-1de0-4b89-bf38-2a59343b1805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057562634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3
057562634
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2992792200
Short name T715
Test name
Test status
Simulation time 48048331169 ps
CPU time 17.43 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201480 kb
Host smart-f948238f-feec-4096-8fdb-5f3e46620cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992792200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2992792200
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4055209154
Short name T192
Test name
Test status
Simulation time 2918659737 ps
CPU time 2.46 seconds
Started Jun 24 06:34:19 PM PDT 24
Finished Jun 24 06:34:25 PM PDT 24
Peak memory 201232 kb
Host smart-2e06a702-6c6c-4d3b-bbd6-20bafd1a627a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055209154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.4055209154
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3328218139
Short name T453
Test name
Test status
Simulation time 2635089748 ps
CPU time 1.83 seconds
Started Jun 24 06:34:19 PM PDT 24
Finished Jun 24 06:34:23 PM PDT 24
Peak memory 201248 kb
Host smart-84162859-52e4-4d13-81fa-e63f23e39afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328218139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3328218139
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3743147066
Short name T66
Test name
Test status
Simulation time 2466309674 ps
CPU time 6.69 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:32 PM PDT 24
Peak memory 201244 kb
Host smart-0eee799a-3f94-410c-849c-9cd5912d34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743147066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3743147066
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3850225308
Short name T164
Test name
Test status
Simulation time 2117746446 ps
CPU time 6.03 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201176 kb
Host smart-0dece1c8-088c-41ec-bfcf-ee32b62ff2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850225308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3850225308
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2188364237
Short name T730
Test name
Test status
Simulation time 2511134800 ps
CPU time 6.8 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201256 kb
Host smart-5ab140ed-f305-469e-b2c6-5121659ce9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188364237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2188364237
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1554217551
Short name T319
Test name
Test status
Simulation time 2109208273 ps
CPU time 5.99 seconds
Started Jun 24 06:34:23 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201368 kb
Host smart-6de2f370-63d6-48eb-b149-18a5c1dd427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554217551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1554217551
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.807671881
Short name T281
Test name
Test status
Simulation time 227706647439 ps
CPU time 153 seconds
Started Jun 24 06:34:19 PM PDT 24
Finished Jun 24 06:36:56 PM PDT 24
Peak memory 214260 kb
Host smart-065096d8-928f-49db-a63f-341a87681128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807671881 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.807671881
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2864997366
Short name T80
Test name
Test status
Simulation time 8005270176 ps
CPU time 2.23 seconds
Started Jun 24 06:34:19 PM PDT 24
Finished Jun 24 06:34:25 PM PDT 24
Peak memory 201220 kb
Host smart-e2e92062-e5b5-4dac-8b06-8d15cb496603
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864997366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2864997366
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.1195088745
Short name T467
Test name
Test status
Simulation time 2011051164 ps
CPU time 4.08 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201248 kb
Host smart-a55838f2-3ca3-4ec5-8b0a-bb0fdf797782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195088745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.1195088745
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.128997585
Short name T379
Test name
Test status
Simulation time 3522589803 ps
CPU time 7.27 seconds
Started Jun 24 06:34:23 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201336 kb
Host smart-9669097e-463d-4ca2-ac8c-520a1a31bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128997585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.128997585
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.373524928
Short name T537
Test name
Test status
Simulation time 167951405748 ps
CPU time 406.3 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:41:11 PM PDT 24
Peak memory 201504 kb
Host smart-c4bd714c-9cf5-4840-9e08-32c74abe9ce8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373524928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_combo_detect.373524928
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2275354808
Short name T8
Test name
Test status
Simulation time 33249572302 ps
CPU time 16.65 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:40 PM PDT 24
Peak memory 201496 kb
Host smart-46e43e07-ab86-40b5-b1b9-7174d9126f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275354808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2275354808
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.4185409290
Short name T262
Test name
Test status
Simulation time 3668538852 ps
CPU time 9.06 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:34 PM PDT 24
Peak memory 201232 kb
Host smart-1ff26f83-72bb-42cc-b96f-e9561ce494f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185409290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.4185409290
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.175983297
Short name T629
Test name
Test status
Simulation time 3052582267 ps
CPU time 2.69 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201240 kb
Host smart-76d7e3c7-3066-4b60-87a5-3b3af79e861f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175983297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.175983297
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1748833277
Short name T541
Test name
Test status
Simulation time 2612142450 ps
CPU time 6.98 seconds
Started Jun 24 06:34:19 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201196 kb
Host smart-b0888b06-419d-46de-a7e0-d8d03dd0efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748833277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1748833277
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1990468854
Short name T401
Test name
Test status
Simulation time 2482900531 ps
CPU time 1.57 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:26 PM PDT 24
Peak memory 201252 kb
Host smart-bd377568-aeee-439c-beed-2f56efce4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990468854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1990468854
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1459549722
Short name T647
Test name
Test status
Simulation time 2204378874 ps
CPU time 2.11 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:28 PM PDT 24
Peak memory 201228 kb
Host smart-4c734fe2-7684-4b89-88bf-ac742a55a195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459549722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1459549722
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3243282689
Short name T447
Test name
Test status
Simulation time 2509438763 ps
CPU time 7.32 seconds
Started Jun 24 06:34:20 PM PDT 24
Finished Jun 24 06:34:31 PM PDT 24
Peak memory 201320 kb
Host smart-ceec943a-fecd-40b2-8c8f-71740bfbffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243282689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3243282689
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.510901435
Short name T705
Test name
Test status
Simulation time 2133711990 ps
CPU time 1.96 seconds
Started Jun 24 06:34:18 PM PDT 24
Finished Jun 24 06:34:22 PM PDT 24
Peak memory 201156 kb
Host smart-19d0f4de-2c8d-4979-887f-aa894f370ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510901435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.510901435
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1789236454
Short name T484
Test name
Test status
Simulation time 8784759143 ps
CPU time 5.99 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:31 PM PDT 24
Peak memory 201284 kb
Host smart-04a66e0c-a5ec-48fd-ab1e-a7c7f8cb27e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789236454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1789236454
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.731894981
Short name T723
Test name
Test status
Simulation time 12163082067 ps
CPU time 1.8 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:28 PM PDT 24
Peak memory 201176 kb
Host smart-582d7556-dd1b-4b1b-beb3-5eeb427eddf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731894981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.731894981
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2692818549
Short name T142
Test name
Test status
Simulation time 2019794652 ps
CPU time 2.9 seconds
Started Jun 24 06:34:32 PM PDT 24
Finished Jun 24 06:34:36 PM PDT 24
Peak memory 201244 kb
Host smart-ee261083-50c5-4559-a59e-eae70acbca4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692818549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2692818549
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1598064303
Short name T683
Test name
Test status
Simulation time 3384081608 ps
CPU time 9.31 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:36 PM PDT 24
Peak memory 201312 kb
Host smart-f46c6858-8c8d-495b-a408-b9b6373a7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598064303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
598064303
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1458168681
Short name T639
Test name
Test status
Simulation time 59412212680 ps
CPU time 140.33 seconds
Started Jun 24 06:34:36 PM PDT 24
Finished Jun 24 06:36:57 PM PDT 24
Peak memory 201404 kb
Host smart-a07f54f0-a17a-49a9-ba55-e422275d722c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458168681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1458168681
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1035322843
Short name T492
Test name
Test status
Simulation time 85229547438 ps
CPU time 55.9 seconds
Started Jun 24 06:34:31 PM PDT 24
Finished Jun 24 06:35:29 PM PDT 24
Peak memory 201636 kb
Host smart-004c5a2c-528e-42c0-a9f2-d167c660ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035322843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1035322843
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3886014647
Short name T607
Test name
Test status
Simulation time 3418290055 ps
CPU time 2.81 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201248 kb
Host smart-0c01cf2a-35e0-4a1a-86c8-e0e740548502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886014647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3886014647
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.805628262
Short name T508
Test name
Test status
Simulation time 3139503851 ps
CPU time 4.73 seconds
Started Jun 24 06:34:34 PM PDT 24
Finished Jun 24 06:34:40 PM PDT 24
Peak memory 201236 kb
Host smart-34ec2094-b563-4134-bc4a-ce646ac5a744
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805628262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.805628262
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3841992671
Short name T646
Test name
Test status
Simulation time 2653535185 ps
CPU time 1.79 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201248 kb
Host smart-198e6e82-70e2-4ea6-95bc-b2fdc7846d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841992671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3841992671
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.940398566
Short name T692
Test name
Test status
Simulation time 2468429280 ps
CPU time 6.94 seconds
Started Jun 24 06:34:23 PM PDT 24
Finished Jun 24 06:34:34 PM PDT 24
Peak memory 201260 kb
Host smart-70f3a965-8c96-4051-ad9a-a4bcd11c7a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940398566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.940398566
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.598453131
Short name T610
Test name
Test status
Simulation time 2191329285 ps
CPU time 6.35 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201252 kb
Host smart-0db54847-93d2-4840-a4a9-d2a9a4f0b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598453131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.598453131
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2004012075
Short name T132
Test name
Test status
Simulation time 2516141561 ps
CPU time 4.35 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:31 PM PDT 24
Peak memory 201324 kb
Host smart-4a0ba279-bf6d-4f41-8a28-56d0ee266dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004012075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.2004012075
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3460628785
Short name T180
Test name
Test status
Simulation time 2120308648 ps
CPU time 3 seconds
Started Jun 24 06:34:21 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201172 kb
Host smart-e42cdab1-79e6-4823-944d-3c820572dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460628785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3460628785
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.4215700510
Short name T682
Test name
Test status
Simulation time 8623079406 ps
CPU time 12.12 seconds
Started Jun 24 06:34:32 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201228 kb
Host smart-a823e8ee-8ad5-49bd-bdb8-c65e9b699bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215700510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.4215700510
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1496086262
Short name T63
Test name
Test status
Simulation time 3227073252 ps
CPU time 2.15 seconds
Started Jun 24 06:34:22 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 201264 kb
Host smart-cbd592bf-039b-4b55-b36e-7bb160945ebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496086262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1496086262
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3017602235
Short name T687
Test name
Test status
Simulation time 2035177624 ps
CPU time 1.69 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201248 kb
Host smart-a97156cb-b6ae-40d8-9bbe-c9f4e57bf21d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017602235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3017602235
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3218545534
Short name T488
Test name
Test status
Simulation time 3481356912 ps
CPU time 9.24 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:32:48 PM PDT 24
Peak memory 201300 kb
Host smart-e9114647-6643-4eb2-8a10-288039a3c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218545534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3218545534
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.36832137
Short name T95
Test name
Test status
Simulation time 153185555781 ps
CPU time 90.62 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:34:07 PM PDT 24
Peak memory 201472 kb
Host smart-4b6310b1-0da0-47ce-bb91-cb19c6186796
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36832137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_combo_detect.36832137
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2430578501
Short name T731
Test name
Test status
Simulation time 2462850909 ps
CPU time 2.24 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:32:37 PM PDT 24
Peak memory 201240 kb
Host smart-d291a167-1f89-4e84-b1fc-0489f72a8016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430578501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2430578501
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2610801090
Short name T194
Test name
Test status
Simulation time 2533628520 ps
CPU time 6.81 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201220 kb
Host smart-6101f343-87fb-42db-b03b-08c41250a5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610801090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2610801090
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3350730301
Short name T371
Test name
Test status
Simulation time 66261162860 ps
CPU time 46.96 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 201572 kb
Host smart-e3fa7de1-74aa-4db3-a006-6b00a3c7a5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350730301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3350730301
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.772897329
Short name T237
Test name
Test status
Simulation time 3841826319 ps
CPU time 2.46 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201232 kb
Host smart-0f70d08e-fcc0-4f70-810c-f76defddc97b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772897329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ec_pwr_on_rst.772897329
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3433694297
Short name T591
Test name
Test status
Simulation time 5253671103 ps
CPU time 7.4 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201220 kb
Host smart-09be34ce-b522-451f-b63a-48a363628042
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433694297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3433694297
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.624076921
Short name T490
Test name
Test status
Simulation time 2626903637 ps
CPU time 2.3 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201220 kb
Host smart-e85a0a61-7af6-4d47-bcc1-85ab2524950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624076921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.624076921
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1116489357
Short name T261
Test name
Test status
Simulation time 2476543920 ps
CPU time 6.89 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201240 kb
Host smart-838c72ab-b55d-450f-84dc-a61ed891e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116489357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1116489357
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1118881712
Short name T573
Test name
Test status
Simulation time 2084028256 ps
CPU time 5.59 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201188 kb
Host smart-eefe0670-8bd6-4d5e-9b73-44f506dfb0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118881712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1118881712
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.601876087
Short name T6
Test name
Test status
Simulation time 2513922513 ps
CPU time 7.21 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:44 PM PDT 24
Peak memory 201180 kb
Host smart-df24b561-1ec7-4b30-9f9d-4519d24d7c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601876087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.601876087
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3962676708
Short name T589
Test name
Test status
Simulation time 2132752367 ps
CPU time 1.99 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201124 kb
Host smart-853f9281-3f65-4633-ade0-f1039f60e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962676708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3962676708
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3013811182
Short name T609
Test name
Test status
Simulation time 12285610913 ps
CPU time 30.25 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:33:08 PM PDT 24
Peak memory 201212 kb
Host smart-056d28e5-390f-42e4-909c-4c60dcad67e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013811182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3013811182
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2469900520
Short name T239
Test name
Test status
Simulation time 27727974602 ps
CPU time 66.13 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:33:47 PM PDT 24
Peak memory 209824 kb
Host smart-e61dac3f-f5d5-42ca-9191-94dc1bd4ab7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469900520 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2469900520
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.3029901055
Short name T202
Test name
Test status
Simulation time 2021681680 ps
CPU time 3.09 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:34:34 PM PDT 24
Peak memory 201244 kb
Host smart-6dfe1aa0-5dfe-49ac-b708-2337ae96a647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029901055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.3029901055
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1949567649
Short name T437
Test name
Test status
Simulation time 3426387112 ps
CPU time 9.32 seconds
Started Jun 24 06:34:32 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 201312 kb
Host smart-06e53d56-6e78-4ec2-899b-2da94f397809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949567649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
949567649
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1518573821
Short name T545
Test name
Test status
Simulation time 108710993046 ps
CPU time 282.65 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:39:14 PM PDT 24
Peak memory 201452 kb
Host smart-ebc75b90-42f0-446d-8dc8-ba3388f57624
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518573821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1518573821
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1448324189
Short name T673
Test name
Test status
Simulation time 29080447643 ps
CPU time 81.42 seconds
Started Jun 24 06:34:34 PM PDT 24
Finished Jun 24 06:35:57 PM PDT 24
Peak memory 201616 kb
Host smart-f303c340-c65b-4727-a2be-3a771f420e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448324189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1448324189
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3348020747
Short name T434
Test name
Test status
Simulation time 4168932501 ps
CPU time 3.26 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201240 kb
Host smart-7c4ecb09-85ea-444c-b919-3ed778ece61b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348020747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.3348020747
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.775742725
Short name T653
Test name
Test status
Simulation time 2968397770 ps
CPU time 3.66 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201236 kb
Host smart-2283b5c8-486e-4af0-be1c-6d3717d9b4c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775742725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.775742725
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1456470978
Short name T431
Test name
Test status
Simulation time 2622846298 ps
CPU time 2.44 seconds
Started Jun 24 06:34:31 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201260 kb
Host smart-dabe69e0-a3aa-4e26-b763-3ff17bfaf214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456470978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1456470978
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.362585019
Short name T751
Test name
Test status
Simulation time 2475211124 ps
CPU time 2.15 seconds
Started Jun 24 06:34:31 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201272 kb
Host smart-0df2860c-d27e-403e-8a78-4d1b5e649396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362585019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.362585019
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4161050609
Short name T258
Test name
Test status
Simulation time 2137867821 ps
CPU time 3.25 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:34:34 PM PDT 24
Peak memory 201148 kb
Host smart-3b6c2b20-43d9-4030-a2de-9d213ec93e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161050609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.4161050609
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1423002935
Short name T685
Test name
Test status
Simulation time 2513858983 ps
CPU time 6.84 seconds
Started Jun 24 06:34:31 PM PDT 24
Finished Jun 24 06:34:39 PM PDT 24
Peak memory 201320 kb
Host smart-89f2309b-2cad-40a9-9d08-01fd0f930562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423002935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1423002935
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2270820905
Short name T754
Test name
Test status
Simulation time 2117643024 ps
CPU time 3.08 seconds
Started Jun 24 06:34:32 PM PDT 24
Finished Jun 24 06:34:36 PM PDT 24
Peak memory 201164 kb
Host smart-1c7a5a7d-d11d-4231-ac94-019a209a7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270820905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2270820905
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3866473613
Short name T162
Test name
Test status
Simulation time 7774395780 ps
CPU time 15.5 seconds
Started Jun 24 06:34:27 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201232 kb
Host smart-4e35bd68-e7a1-4937-b720-4af1b9e681d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866473613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3866473613
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.714318654
Short name T131
Test name
Test status
Simulation time 4437211753 ps
CPU time 6.26 seconds
Started Jun 24 06:34:32 PM PDT 24
Finished Jun 24 06:34:39 PM PDT 24
Peak memory 201220 kb
Host smart-6ed78e08-fe9b-4a40-b10f-a7d4c4bd91df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714318654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.714318654
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.2931394834
Short name T604
Test name
Test status
Simulation time 2008799313 ps
CPU time 5.85 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201148 kb
Host smart-0b9785b6-116d-4284-bbbb-6961d93c92cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931394834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.2931394834
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1101165939
Short name T538
Test name
Test status
Simulation time 3935393615 ps
CPU time 10.91 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 201532 kb
Host smart-f7abcc5b-2f1f-4315-bb8a-dae399803bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101165939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
101165939
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1027374137
Short name T670
Test name
Test status
Simulation time 64120499389 ps
CPU time 13.52 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201428 kb
Host smart-7d83f910-b476-4124-8002-b43bf80cc0ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027374137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1027374137
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1379267448
Short name T270
Test name
Test status
Simulation time 72936928856 ps
CPU time 166.7 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:37:27 PM PDT 24
Peak memory 201460 kb
Host smart-f01718de-817c-40e3-bdc6-5e905d61902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379267448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1379267448
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.911447772
Short name T215
Test name
Test status
Simulation time 3930835611 ps
CPU time 5.93 seconds
Started Jun 24 06:34:33 PM PDT 24
Finished Jun 24 06:34:40 PM PDT 24
Peak memory 201228 kb
Host smart-742a2559-43e6-46af-9ef3-c9905aec42a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911447772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.911447772
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.141560888
Short name T157
Test name
Test status
Simulation time 3165276397 ps
CPU time 6.25 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:34:38 PM PDT 24
Peak memory 201256 kb
Host smart-10a730c0-0995-44bb-b575-26a3894a786f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141560888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.141560888
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3133751052
Short name T173
Test name
Test status
Simulation time 2660879981 ps
CPU time 1.81 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201232 kb
Host smart-719efbb2-9690-4c8d-9260-2bf1bf6d4864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133751052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3133751052
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1280186883
Short name T649
Test name
Test status
Simulation time 2483582578 ps
CPU time 2.03 seconds
Started Jun 24 06:34:29 PM PDT 24
Finished Jun 24 06:34:33 PM PDT 24
Peak memory 201268 kb
Host smart-e5d6a25a-9b38-4da5-97a7-f6b0fb3228ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280186883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1280186883
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1069604146
Short name T167
Test name
Test status
Simulation time 2061702235 ps
CPU time 2 seconds
Started Jun 24 06:34:28 PM PDT 24
Finished Jun 24 06:34:32 PM PDT 24
Peak memory 201172 kb
Host smart-4194b123-402e-4f03-bde4-7f66adc02932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069604146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1069604146
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2350754531
Short name T669
Test name
Test status
Simulation time 2512720657 ps
CPU time 7.12 seconds
Started Jun 24 06:34:34 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 201312 kb
Host smart-50651513-40b3-4930-a14e-1b869b410f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350754531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2350754531
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1965529065
Short name T441
Test name
Test status
Simulation time 2113117911 ps
CPU time 5.81 seconds
Started Jun 24 06:34:34 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 201164 kb
Host smart-16c6a8ba-0955-4332-8cc2-72bd9b2928e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965529065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1965529065
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2729182336
Short name T598
Test name
Test status
Simulation time 11246126682 ps
CPU time 7.93 seconds
Started Jun 24 06:34:45 PM PDT 24
Finished Jun 24 06:34:54 PM PDT 24
Peak memory 201504 kb
Host smart-d0391c1f-d8ea-4771-9d5b-a1c22211a2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729182336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2729182336
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1509767611
Short name T233
Test name
Test status
Simulation time 22729004611 ps
CPU time 30.28 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:35:12 PM PDT 24
Peak memory 209776 kb
Host smart-de6bea29-2936-4661-ab2e-22b1023c9d6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509767611 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1509767611
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1812281335
Short name T616
Test name
Test status
Simulation time 3999950763 ps
CPU time 3.58 seconds
Started Jun 24 06:34:30 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 201244 kb
Host smart-78f75ad6-7b98-4e12-ba6f-3e663f4b7f0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812281335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1812281335
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.4031120294
Short name T532
Test name
Test status
Simulation time 2014889967 ps
CPU time 5.54 seconds
Started Jun 24 06:34:45 PM PDT 24
Finished Jun 24 06:34:51 PM PDT 24
Peak memory 201244 kb
Host smart-8ad7eed2-145a-4d35-9c7c-e6249753c51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031120294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.4031120294
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2895087842
Short name T759
Test name
Test status
Simulation time 3434866212 ps
CPU time 1.27 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201324 kb
Host smart-55ab8e5a-90f8-42b3-aae9-d45ac903cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895087842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
895087842
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3114050008
Short name T120
Test name
Test status
Simulation time 77954883047 ps
CPU time 67.72 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:35:48 PM PDT 24
Peak memory 201428 kb
Host smart-624b97c6-b2c8-4916-8cfc-655eee759c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114050008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3114050008
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3972138601
Short name T462
Test name
Test status
Simulation time 2929083994 ps
CPU time 4.1 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201232 kb
Host smart-b380acba-b0a3-4915-bec9-571c24888e6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972138601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3972138601
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.872797850
Short name T42
Test name
Test status
Simulation time 4969961865 ps
CPU time 1.6 seconds
Started Jun 24 06:34:43 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201240 kb
Host smart-e0eda0df-2e0a-434b-8ec9-46c850ba0c7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872797850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.872797850
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3051490678
Short name T690
Test name
Test status
Simulation time 2631821329 ps
CPU time 2.16 seconds
Started Jun 24 06:34:42 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201424 kb
Host smart-1d58f481-3137-4eb2-92f2-f813617295a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051490678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3051490678
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2791962176
Short name T228
Test name
Test status
Simulation time 2462009475 ps
CPU time 6.92 seconds
Started Jun 24 06:34:40 PM PDT 24
Finished Jun 24 06:34:48 PM PDT 24
Peak memory 201432 kb
Host smart-f8b915d8-511a-4e01-9628-d3e6b574b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791962176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2791962176
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4154587416
Short name T633
Test name
Test status
Simulation time 2249956405 ps
CPU time 6.44 seconds
Started Jun 24 06:34:40 PM PDT 24
Finished Jun 24 06:34:48 PM PDT 24
Peak memory 201188 kb
Host smart-29ca8027-74b6-4aaa-8340-67c19cfb918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154587416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.4154587416
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.210928234
Short name T650
Test name
Test status
Simulation time 2525185287 ps
CPU time 2.31 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 201320 kb
Host smart-2e5c0226-5e00-4193-90c1-fa154b13d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210928234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.210928234
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.3713549057
Short name T418
Test name
Test status
Simulation time 2124904524 ps
CPU time 2.03 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:41 PM PDT 24
Peak memory 201176 kb
Host smart-4b54d29f-f545-4876-a475-903920572ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713549057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.3713549057
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1984585752
Short name T163
Test name
Test status
Simulation time 12906993535 ps
CPU time 8.08 seconds
Started Jun 24 06:34:40 PM PDT 24
Finished Jun 24 06:34:49 PM PDT 24
Peak memory 201236 kb
Host smart-7eb08678-2bfa-4871-b784-dc587ed31a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984585752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1984585752
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1432313114
Short name T90
Test name
Test status
Simulation time 30144463897 ps
CPU time 67.78 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:35:47 PM PDT 24
Peak memory 209908 kb
Host smart-2bb11e83-7e1e-431b-844f-70f688cc453a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432313114 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1432313114
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3733257055
Short name T34
Test name
Test status
Simulation time 11164006415 ps
CPU time 2.74 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201220 kb
Host smart-97537e10-07cb-4a03-8085-129895905ec9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733257055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.3733257055
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2098412867
Short name T299
Test name
Test status
Simulation time 2010861376 ps
CPU time 5.23 seconds
Started Jun 24 06:34:40 PM PDT 24
Finished Jun 24 06:34:47 PM PDT 24
Peak memory 201256 kb
Host smart-2ca3c115-3e08-43ce-9b5f-e085d3d91da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098412867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.2098412867
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2045999398
Short name T717
Test name
Test status
Simulation time 3765362020 ps
CPU time 3.11 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201288 kb
Host smart-2aa23453-a480-46ae-ba67-ebd1dc50569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045999398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
045999398
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2862371087
Short name T217
Test name
Test status
Simulation time 69063357778 ps
CPU time 183.91 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:37:42 PM PDT 24
Peak memory 201404 kb
Host smart-d0d30269-1beb-4f64-b4dc-5eea7114ab22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862371087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2862371087
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3565331728
Short name T4
Test name
Test status
Simulation time 2778572404 ps
CPU time 8.04 seconds
Started Jun 24 06:34:43 PM PDT 24
Finished Jun 24 06:34:52 PM PDT 24
Peak memory 201228 kb
Host smart-48726a2f-3ee3-48a4-93ff-a353874d4761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565331728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3565331728
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3896591513
Short name T40
Test name
Test status
Simulation time 3114667838 ps
CPU time 2.17 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:41 PM PDT 24
Peak memory 201232 kb
Host smart-761fc560-8c8a-40a7-a59b-e5fc037dfb1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896591513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3896591513
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1377930963
Short name T743
Test name
Test status
Simulation time 2613060118 ps
CPU time 7.25 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201248 kb
Host smart-96532010-aa46-4d6f-8353-40c63988cc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377930963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1377930963
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3607763949
Short name T566
Test name
Test status
Simulation time 2464570125 ps
CPU time 7.23 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201260 kb
Host smart-7b99c943-aa74-46a1-ac8d-b0fb53dd3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607763949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3607763949
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1320261977
Short name T184
Test name
Test status
Simulation time 2166620255 ps
CPU time 6.38 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:34:49 PM PDT 24
Peak memory 201204 kb
Host smart-b08a851f-487c-40c6-a28c-c0aae6155d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320261977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1320261977
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1868490664
Short name T641
Test name
Test status
Simulation time 2536121077 ps
CPU time 2.34 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 201316 kb
Host smart-ca738561-db9c-4c06-a31e-028a6d99cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868490664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1868490664
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.1382600938
Short name T587
Test name
Test status
Simulation time 2138931852 ps
CPU time 1.53 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 201176 kb
Host smart-63f0d236-587d-49a6-814d-e626c5630199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382600938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.1382600938
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3151043237
Short name T471
Test name
Test status
Simulation time 7118860521 ps
CPU time 5.95 seconds
Started Jun 24 06:34:36 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 201248 kb
Host smart-770b39d3-3f22-40f3-a731-98f9b72346eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151043237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3151043237
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3837659254
Short name T305
Test name
Test status
Simulation time 9897485110 ps
CPU time 12.73 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 209692 kb
Host smart-8aef4dff-0d8c-45b8-8ae6-a7e277540e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837659254 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3837659254
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3114763528
Short name T79
Test name
Test status
Simulation time 6793330438 ps
CPU time 4.18 seconds
Started Jun 24 06:34:38 PM PDT 24
Finished Jun 24 06:34:43 PM PDT 24
Peak memory 201236 kb
Host smart-730f2779-5870-4149-962d-be8a4813a560
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114763528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.3114763528
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3148265119
Short name T234
Test name
Test status
Simulation time 2012972406 ps
CPU time 5.91 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:34:57 PM PDT 24
Peak memory 201248 kb
Host smart-45b0766d-263c-4535-92d3-8158acbad084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148265119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3148265119
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1574574772
Short name T527
Test name
Test status
Simulation time 3092543793 ps
CPU time 2.08 seconds
Started Jun 24 06:34:42 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201276 kb
Host smart-0df41dc6-a849-41ad-a1aa-9fbe1a4d5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574574772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1
574574772
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1892299438
Short name T345
Test name
Test status
Simulation time 154998375694 ps
CPU time 104.81 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:36:25 PM PDT 24
Peak memory 201468 kb
Host smart-f2946eae-fe6c-4af9-9b90-db3e6dd680c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892299438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1892299438
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2357253816
Short name T672
Test name
Test status
Simulation time 26584782220 ps
CPU time 35.4 seconds
Started Jun 24 06:34:52 PM PDT 24
Finished Jun 24 06:35:28 PM PDT 24
Peak memory 201568 kb
Host smart-1773b18c-9903-4303-bdd3-d1d5e836506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357253816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.2357253816
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3855277260
Short name T793
Test name
Test status
Simulation time 4214283308 ps
CPU time 1.39 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 201232 kb
Host smart-242fb1d5-a8f2-409d-a747-ed3151c9f56e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855277260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.3855277260
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2516828685
Short name T160
Test name
Test status
Simulation time 4448893989 ps
CPU time 7.31 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201240 kb
Host smart-5f2f780e-4ea8-49bb-9794-284e28869b7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516828685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.2516828685
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1773927373
Short name T556
Test name
Test status
Simulation time 2620230549 ps
CPU time 3.66 seconds
Started Jun 24 06:34:42 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 201232 kb
Host smart-6dca7094-837c-4354-88fd-4155bf035897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773927373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1773927373
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1446148684
Short name T21
Test name
Test status
Simulation time 2497902401 ps
CPU time 1.82 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:49 PM PDT 24
Peak memory 201216 kb
Host smart-c0adc9dd-f0e2-447b-a220-816571ba7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446148684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1446148684
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.269198250
Short name T119
Test name
Test status
Simulation time 2064820546 ps
CPU time 1.97 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:50 PM PDT 24
Peak memory 201216 kb
Host smart-c2e043b7-fdae-4b27-b72e-5aa1261c2a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269198250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.269198250
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.406448837
Short name T514
Test name
Test status
Simulation time 2511298260 ps
CPU time 7.25 seconds
Started Jun 24 06:34:40 PM PDT 24
Finished Jun 24 06:34:49 PM PDT 24
Peak memory 201328 kb
Host smart-6673f0e4-c1ca-4c4c-bf8d-1cb5c80370bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406448837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.406448837
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2398567951
Short name T625
Test name
Test status
Simulation time 2113449879 ps
CPU time 6.06 seconds
Started Jun 24 06:34:41 PM PDT 24
Finished Jun 24 06:34:48 PM PDT 24
Peak memory 201180 kb
Host smart-32c58b18-a9b9-47b3-9837-e5ef73524fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398567951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2398567951
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2843069928
Short name T553
Test name
Test status
Simulation time 6148687959 ps
CPU time 8.79 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201224 kb
Host smart-025cfc40-57b8-4de5-a568-273d9ff74928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843069928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2843069928
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2358631247
Short name T577
Test name
Test status
Simulation time 32809115443 ps
CPU time 72.89 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:36:01 PM PDT 24
Peak memory 209876 kb
Host smart-20ea3308-527b-422f-b270-bd7e88ce2bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358631247 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.2358631247
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1956440483
Short name T456
Test name
Test status
Simulation time 6571893103 ps
CPU time 4.07 seconds
Started Jun 24 06:34:39 PM PDT 24
Finished Jun 24 06:34:44 PM PDT 24
Peak memory 201268 kb
Host smart-a52fe62f-7e59-4d08-b174-7ee2c0d7aa82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956440483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1956440483
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3314069010
Short name T186
Test name
Test status
Simulation time 2011616908 ps
CPU time 5.48 seconds
Started Jun 24 06:34:51 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201232 kb
Host smart-7cd30af8-cf1b-4f0b-b503-725710dc21fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314069010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3314069010
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1072975873
Short name T51
Test name
Test status
Simulation time 3362068819 ps
CPU time 8.69 seconds
Started Jun 24 06:34:53 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 201352 kb
Host smart-a53ef90b-9263-4484-b1c4-bc128c7a7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072975873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
072975873
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3195762405
Short name T599
Test name
Test status
Simulation time 94716522874 ps
CPU time 130.5 seconds
Started Jun 24 06:34:53 PM PDT 24
Finished Jun 24 06:37:05 PM PDT 24
Peak memory 201488 kb
Host smart-5441b318-917b-4310-8e0e-4b67c53405b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195762405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3195762405
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.956746360
Short name T84
Test name
Test status
Simulation time 76824122516 ps
CPU time 201.44 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:38:10 PM PDT 24
Peak memory 201548 kb
Host smart-fe900910-914d-4b9d-9373-f134abf692a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956746360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.956746360
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3220438171
Short name T440
Test name
Test status
Simulation time 4213412782 ps
CPU time 1.22 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:51 PM PDT 24
Peak memory 201232 kb
Host smart-6fefef0b-260e-42dd-b8d5-9916996faa3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220438171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3220438171
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.4104717428
Short name T654
Test name
Test status
Simulation time 4150186486 ps
CPU time 5.2 seconds
Started Jun 24 06:34:52 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201276 kb
Host smart-b522a030-1611-429f-87b0-ea3197234ffd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104717428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.4104717428
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3872583292
Short name T389
Test name
Test status
Simulation time 2612959621 ps
CPU time 7.3 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201416 kb
Host smart-84284297-cca4-433f-b202-c5ff779a4d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872583292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3872583292
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4066541210
Short name T498
Test name
Test status
Simulation time 2469834514 ps
CPU time 3.59 seconds
Started Jun 24 06:34:51 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201236 kb
Host smart-b4f92437-7c36-4933-8df8-a2bfa477e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066541210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.4066541210
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3264187917
Short name T590
Test name
Test status
Simulation time 2194999416 ps
CPU time 1.91 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201228 kb
Host smart-dca16f8d-dad4-436b-9826-8368d5c8ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264187917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3264187917
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.867269149
Short name T231
Test name
Test status
Simulation time 2114572264 ps
CPU time 3.26 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:34:54 PM PDT 24
Peak memory 201136 kb
Host smart-085531a7-5606-4a4f-af13-a71659e1e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867269149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.867269149
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.384680829
Short name T416
Test name
Test status
Simulation time 7886742689 ps
CPU time 19.85 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:35:09 PM PDT 24
Peak memory 201340 kb
Host smart-c67a5413-6daf-4ab2-adb3-a43cdc405c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384680829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_st
ress_all.384680829
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.689216484
Short name T627
Test name
Test status
Simulation time 4228488769 ps
CPU time 1.14 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:50 PM PDT 24
Peak memory 201232 kb
Host smart-a854ce42-580e-4c69-870a-4318135630a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689216484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.689216484
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2414194895
Short name T614
Test name
Test status
Simulation time 2011053325 ps
CPU time 5.59 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201232 kb
Host smart-51f4cb4d-0757-4082-864c-20978ea35f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414194895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2414194895
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.294917592
Short name T464
Test name
Test status
Simulation time 3339993579 ps
CPU time 2.69 seconds
Started Jun 24 06:34:51 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201284 kb
Host smart-acbaa73e-53d3-4f9b-ad64-7851ab46fde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294917592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.294917592
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2831167907
Short name T246
Test name
Test status
Simulation time 58529368881 ps
CPU time 23.29 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:35:13 PM PDT 24
Peak memory 201596 kb
Host smart-315c7893-fd2c-4362-aeca-5e17524761ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831167907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.2831167907
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3257814258
Short name T732
Test name
Test status
Simulation time 3087965121 ps
CPU time 2.16 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:52 PM PDT 24
Peak memory 201232 kb
Host smart-87001c8a-4469-4ee9-9612-e4b8906baa68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257814258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.3257814258
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.4179805671
Short name T155
Test name
Test status
Simulation time 3183749634 ps
CPU time 8.08 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:56 PM PDT 24
Peak memory 201244 kb
Host smart-796c9a4b-c6d4-4155-b191-1070ffbee235
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179805671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.4179805671
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1517894812
Short name T630
Test name
Test status
Simulation time 2611846342 ps
CPU time 6.85 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:34:58 PM PDT 24
Peak memory 201216 kb
Host smart-a8846ea9-6a97-4313-8efe-a7cc23216c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517894812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1517894812
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1547582834
Short name T425
Test name
Test status
Simulation time 2472994020 ps
CPU time 2.25 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201424 kb
Host smart-8312af48-e2b5-4f6c-a18b-19abf204ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547582834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1547582834
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1952142508
Short name T509
Test name
Test status
Simulation time 2267316043 ps
CPU time 2.15 seconds
Started Jun 24 06:34:52 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201232 kb
Host smart-6c3108d1-180d-43a2-af0f-3daad4c79d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952142508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1952142508
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1000475433
Short name T168
Test name
Test status
Simulation time 2512148797 ps
CPU time 7.15 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:34:59 PM PDT 24
Peak memory 201288 kb
Host smart-e1d5a728-8b85-477c-802f-7762b98fe51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000475433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1000475433
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1222796332
Short name T749
Test name
Test status
Simulation time 2130236618 ps
CPU time 1.98 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:49 PM PDT 24
Peak memory 201184 kb
Host smart-37c8853f-ca10-4f07-afb7-9128fb82d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222796332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1222796332
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.538202384
Short name T83
Test name
Test status
Simulation time 9042143137 ps
CPU time 10.19 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 201212 kb
Host smart-9ef84e57-a9fc-45f7-8dd5-a83b92f91ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538202384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.538202384
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1154730461
Short name T223
Test name
Test status
Simulation time 38346625693 ps
CPU time 45.9 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:35:34 PM PDT 24
Peak memory 209804 kb
Host smart-3dca2a52-071c-41c1-882e-63d17a3582ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154730461 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1154730461
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3559566748
Short name T395
Test name
Test status
Simulation time 8121083457 ps
CPU time 5.18 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201288 kb
Host smart-09a49789-249e-4e53-b5b1-4b3ecea8fec2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559566748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3559566748
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1873386666
Short name T740
Test name
Test status
Simulation time 2021085535 ps
CPU time 3.07 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:04 PM PDT 24
Peak memory 201252 kb
Host smart-d5a38aad-832f-4946-95d8-d8b12439a4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873386666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1873386666
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2014959533
Short name T722
Test name
Test status
Simulation time 47713052865 ps
CPU time 49.89 seconds
Started Jun 24 06:34:49 PM PDT 24
Finished Jun 24 06:35:41 PM PDT 24
Peak memory 201284 kb
Host smart-8e97c71d-4ee2-4777-8e39-759f5eaa17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014959533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
014959533
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.4217059810
Short name T348
Test name
Test status
Simulation time 102340867159 ps
CPU time 57.59 seconds
Started Jun 24 06:34:46 PM PDT 24
Finished Jun 24 06:35:44 PM PDT 24
Peak memory 201464 kb
Host smart-657f614b-da75-4e9a-a116-76e4b2fecff9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217059810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.4217059810
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2272784508
Short name T243
Test name
Test status
Simulation time 72097897310 ps
CPU time 50.49 seconds
Started Jun 24 06:34:50 PM PDT 24
Finished Jun 24 06:35:42 PM PDT 24
Peak memory 201544 kb
Host smart-a09fa57d-a1ef-42ff-8790-f2c288e32f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272784508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2272784508
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3694014804
Short name T178
Test name
Test status
Simulation time 4104031879 ps
CPU time 3.09 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201204 kb
Host smart-e764035b-0cd8-4d64-934d-5cfe8f1a8257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694014804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3694014804
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3805350787
Short name T477
Test name
Test status
Simulation time 2790779640 ps
CPU time 1.93 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:52 PM PDT 24
Peak memory 201240 kb
Host smart-adffbf32-04e1-4f1a-8cb7-f65ad1b939aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805350787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.3805350787
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2163504725
Short name T525
Test name
Test status
Simulation time 2611168677 ps
CPU time 7.39 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:57 PM PDT 24
Peak memory 201236 kb
Host smart-834abf93-ad9f-40ac-af9c-0bbeaa4f5fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163504725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2163504725
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2933903360
Short name T382
Test name
Test status
Simulation time 2495004949 ps
CPU time 2.72 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201236 kb
Host smart-0edf437c-aa20-493b-a90b-5c7a0dcfe5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933903360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2933903360
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2077804804
Short name T584
Test name
Test status
Simulation time 2184781946 ps
CPU time 3.28 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:52 PM PDT 24
Peak memory 201256 kb
Host smart-c8fc529e-a775-4c03-9a74-cc51570e990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077804804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2077804804
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1841157431
Short name T586
Test name
Test status
Simulation time 2511684706 ps
CPU time 7.03 seconds
Started Jun 24 06:34:48 PM PDT 24
Finished Jun 24 06:34:57 PM PDT 24
Peak memory 201324 kb
Host smart-4dc4e336-01e0-4d9d-abac-c2467187fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841157431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1841157431
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.1179775130
Short name T482
Test name
Test status
Simulation time 2113086909 ps
CPU time 5.91 seconds
Started Jun 24 06:34:46 PM PDT 24
Finished Jun 24 06:34:53 PM PDT 24
Peak memory 201104 kb
Host smart-f1bd711f-2e21-4ba1-9449-23d6906f04c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179775130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1179775130
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.1182444802
Short name T662
Test name
Test status
Simulation time 7395818152 ps
CPU time 3.08 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:03 PM PDT 24
Peak memory 201232 kb
Host smart-68fc1e4c-2fc8-4242-9d5b-0b5da6661711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182444802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.1182444802
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.394951544
Short name T129
Test name
Test status
Simulation time 4616360822 ps
CPU time 7.06 seconds
Started Jun 24 06:34:47 PM PDT 24
Finished Jun 24 06:34:55 PM PDT 24
Peak memory 201204 kb
Host smart-3904a9b1-470b-45e7-b068-29c4012fca65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394951544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ultra_low_pwr.394951544
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3548113101
Short name T640
Test name
Test status
Simulation time 2014891289 ps
CPU time 6.38 seconds
Started Jun 24 06:35:00 PM PDT 24
Finished Jun 24 06:35:08 PM PDT 24
Peak memory 201212 kb
Host smart-3e6b1bae-a146-4096-b11d-a274b747be08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548113101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3548113101
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.589374746
Short name T104
Test name
Test status
Simulation time 2991416364 ps
CPU time 4.32 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:04 PM PDT 24
Peak memory 201316 kb
Host smart-27b1b6fb-6995-4bda-b9d3-cacbcfc7880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589374746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.589374746
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3003017222
Short name T578
Test name
Test status
Simulation time 65110137374 ps
CPU time 161.46 seconds
Started Jun 24 06:34:56 PM PDT 24
Finished Jun 24 06:37:39 PM PDT 24
Peak memory 201448 kb
Host smart-ee81cc0c-f2d3-4415-b962-121d7e39b1ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003017222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3003017222
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2604529507
Short name T667
Test name
Test status
Simulation time 26329669001 ps
CPU time 68.76 seconds
Started Jun 24 06:35:00 PM PDT 24
Finished Jun 24 06:36:11 PM PDT 24
Peak memory 201544 kb
Host smart-11546c99-5419-4353-80d1-63167cb66e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604529507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2604529507
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.262246858
Short name T399
Test name
Test status
Simulation time 2918831538 ps
CPU time 1.99 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:03 PM PDT 24
Peak memory 201228 kb
Host smart-6b61e8e8-9203-4f1d-a77e-4345b344972b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262246858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ec_pwr_on_rst.262246858
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.368159594
Short name T150
Test name
Test status
Simulation time 4621744529 ps
CPU time 4.07 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:04 PM PDT 24
Peak memory 201228 kb
Host smart-01444aa8-68ed-4cc4-b262-a61dd097cb57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368159594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctr
l_edge_detect.368159594
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3866907526
Short name T407
Test name
Test status
Simulation time 2619332653 ps
CPU time 3.81 seconds
Started Jun 24 06:34:58 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 201260 kb
Host smart-753e3488-dddf-43b8-a4e5-22b098e9c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866907526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3866907526
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1008200611
Short name T698
Test name
Test status
Simulation time 2487080614 ps
CPU time 3.36 seconds
Started Jun 24 06:35:01 PM PDT 24
Finished Jun 24 06:35:05 PM PDT 24
Peak memory 201424 kb
Host smart-297f19cb-ac14-4796-969f-fa47170a1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008200611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1008200611
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.277948813
Short name T444
Test name
Test status
Simulation time 2018252166 ps
CPU time 5.55 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:06 PM PDT 24
Peak memory 201172 kb
Host smart-24286413-62d1-4506-9028-166987befbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277948813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.277948813
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2436446122
Short name T17
Test name
Test status
Simulation time 2538988989 ps
CPU time 2.45 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:01 PM PDT 24
Peak memory 201316 kb
Host smart-b4fe7300-b7d0-4886-af21-67b7fe73bd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436446122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2436446122
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3330181846
Short name T205
Test name
Test status
Simulation time 2126154706 ps
CPU time 2.08 seconds
Started Jun 24 06:35:04 PM PDT 24
Finished Jun 24 06:35:07 PM PDT 24
Peak memory 201176 kb
Host smart-96019b6b-db14-49ec-b09a-627a4be79660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330181846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3330181846
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.2112249516
Short name T563
Test name
Test status
Simulation time 7631086055 ps
CPU time 19.89 seconds
Started Jun 24 06:34:56 PM PDT 24
Finished Jun 24 06:35:17 PM PDT 24
Peak memory 201292 kb
Host smart-b7c4c1f0-e3cd-43a5-b6b6-f5e912fd50e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112249516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.2112249516
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1132105786
Short name T96
Test name
Test status
Simulation time 30388234444 ps
CPU time 60.97 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:59 PM PDT 24
Peak memory 217556 kb
Host smart-4e444a2b-1da2-4772-aaa1-b02a92f3dfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132105786 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1132105786
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1876584164
Short name T171
Test name
Test status
Simulation time 2028672609 ps
CPU time 2.29 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:00 PM PDT 24
Peak memory 201236 kb
Host smart-13a57ba1-c202-4f1f-9a69-136119fa2470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876584164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1876584164
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2324462521
Short name T593
Test name
Test status
Simulation time 3565527216 ps
CPU time 3.25 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:01 PM PDT 24
Peak memory 201304 kb
Host smart-4f699bd4-cf26-4855-9ef9-fcd4ef097821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324462521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2
324462521
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3862142168
Short name T571
Test name
Test status
Simulation time 131332737516 ps
CPU time 42.57 seconds
Started Jun 24 06:34:56 PM PDT 24
Finished Jun 24 06:35:40 PM PDT 24
Peak memory 201584 kb
Host smart-b2783320-81f9-4c96-915f-9c0ccbbbe780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862142168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3862142168
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.835425655
Short name T544
Test name
Test status
Simulation time 3235428818 ps
CPU time 9.31 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:09 PM PDT 24
Peak memory 201236 kb
Host smart-f9a7ba57-6231-477b-ab40-f368a1109401
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835425655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.835425655
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2487856878
Short name T196
Test name
Test status
Simulation time 2935400686 ps
CPU time 5.99 seconds
Started Jun 24 06:35:00 PM PDT 24
Finished Jun 24 06:35:07 PM PDT 24
Peak memory 201272 kb
Host smart-963c02ab-9ded-475e-9fc1-a4dada6bcab8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487856878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2487856878
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3327929612
Short name T496
Test name
Test status
Simulation time 2628620558 ps
CPU time 2.84 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 201428 kb
Host smart-e42e4a16-6cc4-4a37-bed3-90150a00f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327929612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3327929612
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.89435089
Short name T300
Test name
Test status
Simulation time 2471241954 ps
CPU time 3.7 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:03 PM PDT 24
Peak memory 201264 kb
Host smart-6d06a570-1316-43bd-8fc8-0f9e8a5a99a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89435089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.89435089
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3434097206
Short name T222
Test name
Test status
Simulation time 2031391612 ps
CPU time 1.93 seconds
Started Jun 24 06:34:58 PM PDT 24
Finished Jun 24 06:35:00 PM PDT 24
Peak memory 201176 kb
Host smart-18a623c1-02ea-4c19-8557-ae9842ca9c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434097206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3434097206
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.675992298
Short name T494
Test name
Test status
Simulation time 2511290890 ps
CPU time 7.08 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:05 PM PDT 24
Peak memory 201300 kb
Host smart-0f7af72a-17a5-4c6e-bfc7-9580bab87a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675992298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.675992298
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.548171902
Short name T790
Test name
Test status
Simulation time 2116807763 ps
CPU time 3.31 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:03 PM PDT 24
Peak memory 201152 kb
Host smart-93fdc389-f375-4841-a1c5-d3b3f99c2c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548171902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.548171902
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.149665335
Short name T786
Test name
Test status
Simulation time 137870759003 ps
CPU time 82.61 seconds
Started Jun 24 06:35:00 PM PDT 24
Finished Jun 24 06:36:24 PM PDT 24
Peak memory 201428 kb
Host smart-797fa6fd-2fd6-4069-a1be-19b038540b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149665335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_st
ress_all.149665335
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1182554919
Short name T579
Test name
Test status
Simulation time 355960635178 ps
CPU time 50.61 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:35:52 PM PDT 24
Peak memory 209784 kb
Host smart-8c9b21c1-6727-4b96-8a75-d406cf34c095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182554919 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1182554919
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3845658074
Short name T621
Test name
Test status
Simulation time 1037361255386 ps
CPU time 10.68 seconds
Started Jun 24 06:35:03 PM PDT 24
Finished Jun 24 06:35:14 PM PDT 24
Peak memory 201216 kb
Host smart-f5b34a0e-ac10-4932-bd6c-4a8f85143dd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845658074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3845658074
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1373813577
Short name T458
Test name
Test status
Simulation time 2018128548 ps
CPU time 3.18 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201184 kb
Host smart-e7618ade-4f9f-491d-8205-02d3513db268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373813577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1373813577
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.66862425
Short name T204
Test name
Test status
Simulation time 3618470352 ps
CPU time 5.38 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201300 kb
Host smart-68469001-8983-484d-91d2-4c295a2299b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66862425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.66862425
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.298060087
Short name T619
Test name
Test status
Simulation time 143400759108 ps
CPU time 178.49 seconds
Started Jun 24 06:32:34 PM PDT 24
Finished Jun 24 06:35:33 PM PDT 24
Peak memory 201500 kb
Host smart-8a89263a-6931-4206-b8b3-abd30bed3cb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298060087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_combo_detect.298060087
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.226015506
Short name T750
Test name
Test status
Simulation time 62865965257 ps
CPU time 165.63 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:35:27 PM PDT 24
Peak memory 201612 kb
Host smart-af1dd068-99c8-49cc-9642-1811d87f7790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226015506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wit
h_pre_cond.226015506
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.514628553
Short name T520
Test name
Test status
Simulation time 4599962840 ps
CPU time 1.21 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:32:40 PM PDT 24
Peak memory 201236 kb
Host smart-857b2641-c80e-443a-b6c1-25ea904398be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514628553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.514628553
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3557857104
Short name T209
Test name
Test status
Simulation time 2429509205 ps
CPU time 4.18 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:41 PM PDT 24
Peak memory 201084 kb
Host smart-7638f6a4-370e-4461-9ad8-96c00b52483c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557857104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3557857104
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1393101920
Short name T512
Test name
Test status
Simulation time 2627048856 ps
CPU time 2.2 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:44 PM PDT 24
Peak memory 201240 kb
Host smart-a891e61e-4b76-4480-b8c4-909fbec0d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393101920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1393101920
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2999514365
Short name T403
Test name
Test status
Simulation time 2468843725 ps
CPU time 1.68 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201260 kb
Host smart-320126f2-70f7-4b1d-8333-362eb22c4ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999514365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2999514365
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1592255015
Short name T540
Test name
Test status
Simulation time 2247690864 ps
CPU time 0.97 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:38 PM PDT 24
Peak memory 201236 kb
Host smart-491f0142-1fec-411d-bce3-b20918c0a0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592255015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1592255015
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2616158622
Short name T301
Test name
Test status
Simulation time 2584311595 ps
CPU time 1.33 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:32:40 PM PDT 24
Peak memory 201316 kb
Host smart-4c534715-e8c6-44da-bf9f-701218bbb20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616158622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2616158622
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1911247738
Short name T435
Test name
Test status
Simulation time 2112897064 ps
CPU time 3.15 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:45 PM PDT 24
Peak memory 201160 kb
Host smart-afe7ba5e-81d6-4fe7-a3d3-9a2d235b3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911247738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1911247738
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.261701839
Short name T684
Test name
Test status
Simulation time 7614706054 ps
CPU time 10.12 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201272 kb
Host smart-85d20266-2466-4a11-9498-3c9815965cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261701839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_str
ess_all.261701839
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4284052254
Short name T77
Test name
Test status
Simulation time 7198122804 ps
CPU time 1.68 seconds
Started Jun 24 06:32:36 PM PDT 24
Finished Jun 24 06:32:39 PM PDT 24
Peak memory 201232 kb
Host smart-02ed2f0a-05e0-4b60-9040-de124851a9a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284052254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.4284052254
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2185366954
Short name T249
Test name
Test status
Simulation time 39939883958 ps
CPU time 90.77 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:36:31 PM PDT 24
Peak memory 201604 kb
Host smart-8ccf5cb1-014c-4a03-9898-b191659ef401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185366954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.2185366954
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1396998596
Short name T773
Test name
Test status
Simulation time 26582758787 ps
CPU time 62.91 seconds
Started Jun 24 06:35:03 PM PDT 24
Finished Jun 24 06:36:06 PM PDT 24
Peak memory 201576 kb
Host smart-cc2004b1-ed3f-4c8b-97f4-f0143d6f1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396998596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1396998596
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.139189259
Short name T350
Test name
Test status
Simulation time 50758050778 ps
CPU time 15.71 seconds
Started Jun 24 06:34:57 PM PDT 24
Finished Jun 24 06:35:14 PM PDT 24
Peak memory 201612 kb
Host smart-9ff06751-6c92-4093-a868-2e92506fc68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139189259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.139189259
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4064033196
Short name T459
Test name
Test status
Simulation time 136665856783 ps
CPU time 171.04 seconds
Started Jun 24 06:34:59 PM PDT 24
Finished Jun 24 06:37:51 PM PDT 24
Peak memory 201508 kb
Host smart-18b77bbb-63b1-4033-8eeb-87a671fa53f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064033196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.4064033196
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3873449626
Short name T762
Test name
Test status
Simulation time 24585723133 ps
CPU time 32.36 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:35:46 PM PDT 24
Peak memory 201636 kb
Host smart-b9b17cb3-e643-458e-b969-4b2ea74142f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873449626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.3873449626
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3864323514
Short name T101
Test name
Test status
Simulation time 71795739096 ps
CPU time 49.52 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:36:04 PM PDT 24
Peak memory 201628 kb
Host smart-66a9c537-dfe8-4663-ab6e-9b386d997e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864323514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3864323514
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1268126514
Short name T753
Test name
Test status
Simulation time 31194670192 ps
CPU time 8.92 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:35:25 PM PDT 24
Peak memory 201572 kb
Host smart-3161b256-2e40-4f07-82c6-699999083b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268126514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.1268126514
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.22263078
Short name T785
Test name
Test status
Simulation time 66209828737 ps
CPU time 88.63 seconds
Started Jun 24 06:35:15 PM PDT 24
Finished Jun 24 06:36:46 PM PDT 24
Peak memory 201556 kb
Host smart-6edb73d1-9dcd-4534-8434-49fe158aff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22263078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wit
h_pre_cond.22263078
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.85317061
Short name T402
Test name
Test status
Simulation time 2021178726 ps
CPU time 4.24 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:46 PM PDT 24
Peak memory 201236 kb
Host smart-77f7c7c8-466d-4001-aa4a-c27fdfd1ae6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85317061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.85317061
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1410777083
Short name T52
Test name
Test status
Simulation time 3620425322 ps
CPU time 9.95 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201492 kb
Host smart-18bb6fd9-a753-46d7-898f-90b2af9c2a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410777083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1410777083
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2040074460
Short name T272
Test name
Test status
Simulation time 140693895648 ps
CPU time 324.02 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:38:06 PM PDT 24
Peak memory 201472 kb
Host smart-f3bc585e-0c80-462c-9b84-ca542fb03503
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040074460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2040074460
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1847296464
Short name T478
Test name
Test status
Simulation time 3856715098 ps
CPU time 2.88 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:44 PM PDT 24
Peak memory 201248 kb
Host smart-d2ecdf59-c2a7-47e8-a3b6-1625bac8c37b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847296464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1847296464
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1044176035
Short name T197
Test name
Test status
Simulation time 4322739647 ps
CPU time 3.23 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201220 kb
Host smart-d384162b-25bf-499b-8f50-1d1d869d188b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044176035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1044176035
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2472303147
Short name T71
Test name
Test status
Simulation time 2616631782 ps
CPU time 3.8 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201232 kb
Host smart-dc560822-9cac-4a0d-988c-7e09e8f467a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472303147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2472303147
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1816618482
Short name T561
Test name
Test status
Simulation time 2467719479 ps
CPU time 6.73 seconds
Started Jun 24 06:32:35 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201224 kb
Host smart-36cf06da-d1ad-414e-818e-2785422395f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816618482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1816618482
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3863546429
Short name T651
Test name
Test status
Simulation time 2247893838 ps
CPU time 5.78 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:32:49 PM PDT 24
Peak memory 201252 kb
Host smart-17b7dc2b-8f93-4441-97f2-e58be2d86dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863546429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3863546429
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1917483561
Short name T708
Test name
Test status
Simulation time 2521150606 ps
CPU time 2.43 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201304 kb
Host smart-c3e0410e-c028-4724-9330-3c7fb5244a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917483561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1917483561
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3636852535
Short name T476
Test name
Test status
Simulation time 2121965139 ps
CPU time 3.27 seconds
Started Jun 24 06:32:37 PM PDT 24
Finished Jun 24 06:32:42 PM PDT 24
Peak memory 201080 kb
Host smart-c63ef5a6-a9fc-4c11-80fb-3cb766323e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636852535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3636852535
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.3242375629
Short name T198
Test name
Test status
Simulation time 15421951810 ps
CPU time 39.75 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:33:22 PM PDT 24
Peak memory 201276 kb
Host smart-22d84ae3-eb72-4bb4-97c5-b19999bde677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242375629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.3242375629
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3733590473
Short name T241
Test name
Test status
Simulation time 62080713256 ps
CPU time 38.52 seconds
Started Jun 24 06:32:43 PM PDT 24
Finished Jun 24 06:33:23 PM PDT 24
Peak memory 209924 kb
Host smart-f48ffe7e-0ae9-4aca-956b-f8b1ddb886f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733590473 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3733590473
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.558603660
Short name T468
Test name
Test status
Simulation time 6793023496 ps
CPU time 6.66 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:50 PM PDT 24
Peak memory 201236 kb
Host smart-95707f06-24d7-42c4-8437-df6897abaf01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558603660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ultra_low_pwr.558603660
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.861793170
Short name T483
Test name
Test status
Simulation time 45949547367 ps
CPU time 28.99 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:35:43 PM PDT 24
Peak memory 201568 kb
Host smart-9acc2a6e-27b4-4186-8f86-2a7742abc187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861793170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi
th_pre_cond.861793170
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4073805270
Short name T686
Test name
Test status
Simulation time 35439639691 ps
CPU time 24 seconds
Started Jun 24 06:35:15 PM PDT 24
Finished Jun 24 06:35:41 PM PDT 24
Peak memory 201604 kb
Host smart-7e529007-e9d9-4cad-886b-8e3ecbcfaf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073805270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.4073805270
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.276125676
Short name T592
Test name
Test status
Simulation time 104145594399 ps
CPU time 102.32 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:36:58 PM PDT 24
Peak memory 201520 kb
Host smart-14d9cb83-2320-4398-b1da-2a587a2b753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276125676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_wi
th_pre_cond.276125676
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2459927767
Short name T784
Test name
Test status
Simulation time 39543638963 ps
CPU time 110.23 seconds
Started Jun 24 06:35:11 PM PDT 24
Finished Jun 24 06:37:02 PM PDT 24
Peak memory 201572 kb
Host smart-eaabebb3-dd1c-42c4-8646-5ca8202a3953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459927767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.2459927767
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3850874043
Short name T116
Test name
Test status
Simulation time 61576296044 ps
CPU time 170.08 seconds
Started Jun 24 06:35:17 PM PDT 24
Finished Jun 24 06:38:10 PM PDT 24
Peak memory 201548 kb
Host smart-3535e3d9-ea29-4c9a-923c-881e2bd1474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850874043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3850874043
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2841383657
Short name T54
Test name
Test status
Simulation time 59490464827 ps
CPU time 29.22 seconds
Started Jun 24 06:35:12 PM PDT 24
Finished Jun 24 06:35:44 PM PDT 24
Peak memory 201564 kb
Host smart-c001f1ea-e0bc-4dc5-9651-7ecc5ad2d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841383657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2841383657
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.1269815791
Short name T721
Test name
Test status
Simulation time 2030400282 ps
CPU time 1.84 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201256 kb
Host smart-ef300587-2243-4efc-a9e6-5ae4d22164a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269815791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.1269815791
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.557725582
Short name T18
Test name
Test status
Simulation time 203520292859 ps
CPU time 520.5 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:41:22 PM PDT 24
Peak memory 201300 kb
Host smart-09ac4990-0749-46a2-8fdf-99783743aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557725582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.557725582
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3377823214
Short name T107
Test name
Test status
Simulation time 94222734822 ps
CPU time 232.67 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:36:34 PM PDT 24
Peak memory 201412 kb
Host smart-02566b77-f281-4a03-bcc8-5b930ccac4cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377823214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.3377823214
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1607966496
Short name T585
Test name
Test status
Simulation time 25590228968 ps
CPU time 31.22 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 201628 kb
Host smart-28571a72-be5e-4af4-bd81-241b2feacce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607966496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.1607966496
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2393043825
Short name T59
Test name
Test status
Simulation time 3948582901 ps
CPU time 10.45 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:52 PM PDT 24
Peak memory 201232 kb
Host smart-636cf29c-a64b-450b-ba08-a868bc79dcb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393043825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2393043825
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2412162823
Short name T191
Test name
Test status
Simulation time 4155878299 ps
CPU time 4.94 seconds
Started Jun 24 06:32:44 PM PDT 24
Finished Jun 24 06:32:50 PM PDT 24
Peak memory 201240 kb
Host smart-29048a29-07d8-4c8c-9b62-ac488f84c145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412162823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2412162823
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1267160086
Short name T536
Test name
Test status
Simulation time 2620497126 ps
CPU time 3.98 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:45 PM PDT 24
Peak memory 201256 kb
Host smart-958415aa-3b19-4f62-88f3-61e5ca3a2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267160086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1267160086
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2678574546
Short name T689
Test name
Test status
Simulation time 2498242830 ps
CPU time 2.12 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:32:45 PM PDT 24
Peak memory 201240 kb
Host smart-1d8f4138-2ef2-4ba8-85f7-8ad11e6f19bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678574546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2678574546
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.388444971
Short name T780
Test name
Test status
Simulation time 2052789082 ps
CPU time 3.19 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201200 kb
Host smart-24174e9d-f45e-4911-9952-363ba30a207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388444971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.388444971
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2383571770
Short name T422
Test name
Test status
Simulation time 2511276125 ps
CPU time 6.71 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:48 PM PDT 24
Peak memory 201320 kb
Host smart-ed85fe85-3b19-4773-9829-30f6f18b70dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383571770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2383571770
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3545785497
Short name T632
Test name
Test status
Simulation time 2112522391 ps
CPU time 5.7 seconds
Started Jun 24 06:32:39 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201172 kb
Host smart-d489e59f-4f9b-4a79-b4e1-dabe5138e4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545785497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3545785497
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.4082903519
Short name T421
Test name
Test status
Simulation time 7236606677 ps
CPU time 9.86 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:32:52 PM PDT 24
Peak memory 201232 kb
Host smart-4c100068-b095-4bba-b09e-723a62fe4254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082903519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.4082903519
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.862471750
Short name T128
Test name
Test status
Simulation time 1288666815486 ps
CPU time 93.83 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:34:17 PM PDT 24
Peak memory 201236 kb
Host smart-09498e25-9856-4e16-a16e-9f3b3c2e76c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862471750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ultra_low_pwr.862471750
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3803182999
Short name T100
Test name
Test status
Simulation time 99411158592 ps
CPU time 256.85 seconds
Started Jun 24 06:35:15 PM PDT 24
Finished Jun 24 06:39:35 PM PDT 24
Peak memory 201580 kb
Host smart-44dfba51-b95e-4cad-b09d-03e3ace25fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803182999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.3803182999
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1890893993
Short name T678
Test name
Test status
Simulation time 65407594751 ps
CPU time 169.27 seconds
Started Jun 24 06:35:14 PM PDT 24
Finished Jun 24 06:38:06 PM PDT 24
Peak memory 201608 kb
Host smart-a6d82499-006e-4b13-91bd-586b28201918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890893993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1890893993
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3737461368
Short name T576
Test name
Test status
Simulation time 73166198360 ps
CPU time 17.48 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:35:33 PM PDT 24
Peak memory 201608 kb
Host smart-302dc79b-d8f1-41ce-aecb-35f2148708ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737461368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3737461368
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2634471371
Short name T660
Test name
Test status
Simulation time 33981094691 ps
CPU time 44.94 seconds
Started Jun 24 06:35:13 PM PDT 24
Finished Jun 24 06:36:01 PM PDT 24
Peak memory 201520 kb
Host smart-eb2f59e5-ed7f-4f7e-8b36-80d147f10e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634471371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.2634471371
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2737531795
Short name T657
Test name
Test status
Simulation time 31842854179 ps
CPU time 25.3 seconds
Started Jun 24 06:35:14 PM PDT 24
Finished Jun 24 06:35:42 PM PDT 24
Peak memory 201500 kb
Host smart-ab88f58c-2abb-4cfb-bff6-d5a3612d2c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737531795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.2737531795
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3217111015
Short name T603
Test name
Test status
Simulation time 61357202081 ps
CPU time 39.52 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:58 PM PDT 24
Peak memory 201628 kb
Host smart-90e18e70-7b84-4f13-8a6a-ddc43cdcc9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217111015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.3217111015
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4176411665
Short name T550
Test name
Test status
Simulation time 26335054281 ps
CPU time 69.62 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:36:28 PM PDT 24
Peak memory 201576 kb
Host smart-60de1e96-3c35-4579-ab6c-755bded6278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176411665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.4176411665
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.421014753
Short name T744
Test name
Test status
Simulation time 2013123551 ps
CPU time 5.73 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:32:58 PM PDT 24
Peak memory 201252 kb
Host smart-9a34540a-915e-4b78-9b3a-7e16f95138c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421014753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test
.421014753
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1260921754
Short name T725
Test name
Test status
Simulation time 3782836749 ps
CPU time 5.46 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:49 PM PDT 24
Peak memory 201340 kb
Host smart-56a79969-187d-4e92-a442-93a7e742a76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260921754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1260921754
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3303965391
Short name T253
Test name
Test status
Simulation time 215417138578 ps
CPU time 125.93 seconds
Started Jun 24 06:32:38 PM PDT 24
Finished Jun 24 06:34:45 PM PDT 24
Peak memory 201420 kb
Host smart-4e6ff213-9f58-4834-8f29-c7b8284efab0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303965391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.3303965391
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4204550674
Short name T259
Test name
Test status
Simulation time 2724624564 ps
CPU time 6.95 seconds
Started Jun 24 06:32:43 PM PDT 24
Finished Jun 24 06:32:51 PM PDT 24
Peak memory 201228 kb
Host smart-77ac0a4f-d1e8-4449-a2a9-125257a0cc93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204550674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.4204550674
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2016817793
Short name T187
Test name
Test status
Simulation time 3006371401 ps
CPU time 2.59 seconds
Started Jun 24 06:32:43 PM PDT 24
Finished Jun 24 06:32:47 PM PDT 24
Peak memory 201236 kb
Host smart-778bffae-7c7d-48f9-8089-749e71183821
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016817793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2016817793
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1369277850
Short name T565
Test name
Test status
Simulation time 2639234826 ps
CPU time 1.69 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 201236 kb
Host smart-f4fd0f9a-6a49-40c4-a3ed-e7d25d7dc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369277850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1369277850
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3004560583
Short name T309
Test name
Test status
Simulation time 2456124346 ps
CPU time 2.41 seconds
Started Jun 24 06:32:41 PM PDT 24
Finished Jun 24 06:32:45 PM PDT 24
Peak memory 201244 kb
Host smart-1c1e2e7c-0ba1-4413-9c2b-b3efe9bd89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004560583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.3004560583
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3676456082
Short name T792
Test name
Test status
Simulation time 2212264582 ps
CPU time 2.08 seconds
Started Jun 24 06:32:43 PM PDT 24
Finished Jun 24 06:32:46 PM PDT 24
Peak memory 201256 kb
Host smart-3a82ac92-b751-4e1b-a603-45d8a0f04671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676456082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3676456082
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.447544276
Short name T374
Test name
Test status
Simulation time 2510799760 ps
CPU time 7.04 seconds
Started Jun 24 06:32:44 PM PDT 24
Finished Jun 24 06:32:52 PM PDT 24
Peak memory 201304 kb
Host smart-20ecd639-a9a0-4362-8f1a-1ff278dbce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447544276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.447544276
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.2020581336
Short name T210
Test name
Test status
Simulation time 2109333269 ps
CPU time 5.69 seconds
Started Jun 24 06:32:47 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201124 kb
Host smart-cac0df8b-688c-4bc5-9291-75dcb2343780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020581336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2020581336
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1297118719
Short name T424
Test name
Test status
Simulation time 12374688583 ps
CPU time 8.71 seconds
Started Jun 24 06:32:42 PM PDT 24
Finished Jun 24 06:32:52 PM PDT 24
Peak memory 201216 kb
Host smart-0f1574ee-a402-43c1-9be4-886d2c99c529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297118719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1297118719
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1020574812
Short name T183
Test name
Test status
Simulation time 34561574723 ps
CPU time 78.55 seconds
Started Jun 24 06:32:43 PM PDT 24
Finished Jun 24 06:34:03 PM PDT 24
Peak memory 213116 kb
Host smart-1ce8a234-eafa-462b-99e4-405e7ec5a8b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020574812 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1020574812
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1737785564
Short name T764
Test name
Test status
Simulation time 2644338454 ps
CPU time 6.19 seconds
Started Jun 24 06:32:40 PM PDT 24
Finished Jun 24 06:32:48 PM PDT 24
Peak memory 201236 kb
Host smart-1bbf2762-57a8-4288-b69f-dddea9b1485e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737785564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1737785564
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3566705750
Short name T263
Test name
Test status
Simulation time 51703461098 ps
CPU time 34.94 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:54 PM PDT 24
Peak memory 201576 kb
Host smart-33a214ff-f478-4a42-abdc-e16f1f5f2415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566705750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3566705750
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.193635072
Short name T48
Test name
Test status
Simulation time 108946197327 ps
CPU time 67.76 seconds
Started Jun 24 06:35:14 PM PDT 24
Finished Jun 24 06:36:24 PM PDT 24
Peak memory 201592 kb
Host smart-f3056cd9-2586-495d-9f96-7c240cc067ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193635072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.193635072
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1965104840
Short name T631
Test name
Test status
Simulation time 47915209279 ps
CPU time 32.57 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:52 PM PDT 24
Peak memory 201576 kb
Host smart-698eb6c3-cecb-4ed2-aa16-b48510e74f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965104840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1965104840
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3517323339
Short name T581
Test name
Test status
Simulation time 132666625706 ps
CPU time 81.75 seconds
Started Jun 24 06:35:19 PM PDT 24
Finished Jun 24 06:36:43 PM PDT 24
Peak memory 201540 kb
Host smart-cf50f7dc-627b-49ff-b845-acf920c27c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517323339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.3517323339
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1532829392
Short name T13
Test name
Test status
Simulation time 36564777609 ps
CPU time 47.88 seconds
Started Jun 24 06:35:15 PM PDT 24
Finished Jun 24 06:36:06 PM PDT 24
Peak memory 201596 kb
Host smart-d72cdc19-15e2-45bd-926b-72597f85c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532829392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1532829392
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1283852998
Short name T507
Test name
Test status
Simulation time 2035048996 ps
CPU time 2.21 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201236 kb
Host smart-81fa03d5-dcf3-4f7a-88f1-f757f6e1e664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283852998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1283852998
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.442152325
Short name T170
Test name
Test status
Simulation time 222787962286 ps
CPU time 100.56 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:34:30 PM PDT 24
Peak memory 201344 kb
Host smart-2021024a-ad7d-4678-9eaf-8bbe73cf9b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442152325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.442152325
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.1673318026
Short name T143
Test name
Test status
Simulation time 58805408261 ps
CPU time 21.64 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 201476 kb
Host smart-8043f200-7d6e-472e-8fd2-220b80d6193e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673318026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.1673318026
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2636545875
Short name T406
Test name
Test status
Simulation time 2925486512 ps
CPU time 2.46 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:55 PM PDT 24
Peak memory 201240 kb
Host smart-96106a3a-0179-4fc9-b03d-4e6f0297c00b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636545875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.2636545875
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3949204683
Short name T671
Test name
Test status
Simulation time 3309580967 ps
CPU time 5.95 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:33:00 PM PDT 24
Peak memory 201240 kb
Host smart-957b45fe-1dc5-4fff-ad34-d656bfed8d86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949204683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3949204683
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3259644724
Short name T375
Test name
Test status
Simulation time 2614216885 ps
CPU time 4.74 seconds
Started Jun 24 06:32:52 PM PDT 24
Finished Jun 24 06:32:59 PM PDT 24
Peak memory 201256 kb
Host smart-236929cc-d6e9-455d-869e-b93024d7cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259644724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3259644724
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.460874314
Short name T308
Test name
Test status
Simulation time 2464914427 ps
CPU time 3.54 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:32:56 PM PDT 24
Peak memory 201432 kb
Host smart-e2302973-7882-4e74-aaeb-28c39918e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460874314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.460874314
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4078005318
Short name T112
Test name
Test status
Simulation time 2080634691 ps
CPU time 3.3 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:53 PM PDT 24
Peak memory 201192 kb
Host smart-f97ed46c-5b58-4d85-b118-8bcda9c015ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078005318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.4078005318
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1273085317
Short name T733
Test name
Test status
Simulation time 2512611684 ps
CPU time 6.62 seconds
Started Jun 24 06:32:49 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201324 kb
Host smart-26cb1e74-4445-4b68-ab7b-18db762c9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273085317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1273085317
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.2707006289
Short name T404
Test name
Test status
Simulation time 2116915740 ps
CPU time 3.31 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:32:57 PM PDT 24
Peak memory 201204 kb
Host smart-51afb97f-251f-409d-9103-65a3774e9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707006289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2707006289
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.562075608
Short name T430
Test name
Test status
Simulation time 23318567631 ps
CPU time 62.54 seconds
Started Jun 24 06:32:51 PM PDT 24
Finished Jun 24 06:33:56 PM PDT 24
Peak memory 201728 kb
Host smart-ca4645f2-5080-4226-8653-63c8bf9d95c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562075608 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.562075608
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.792764100
Short name T574
Test name
Test status
Simulation time 8918506870 ps
CPU time 8.96 seconds
Started Jun 24 06:32:50 PM PDT 24
Finished Jun 24 06:33:01 PM PDT 24
Peak memory 201260 kb
Host smart-42d783d8-ec70-48ee-ba5a-8fa43b9ac423
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792764100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ultra_low_pwr.792764100
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4179243178
Short name T354
Test name
Test status
Simulation time 104199141857 ps
CPU time 273.42 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:39:52 PM PDT 24
Peak memory 201560 kb
Host smart-b1043983-f202-4ad4-8ee8-bbf734b1b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179243178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.4179243178
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2603882168
Short name T366
Test name
Test status
Simulation time 67550380442 ps
CPU time 87 seconds
Started Jun 24 06:35:18 PM PDT 24
Finished Jun 24 06:36:48 PM PDT 24
Peak memory 201532 kb
Host smart-bcb56628-3e7d-4989-9823-85e41bd34654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603882168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2603882168
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3133468697
Short name T244
Test name
Test status
Simulation time 27331287042 ps
CPU time 71.77 seconds
Started Jun 24 06:35:17 PM PDT 24
Finished Jun 24 06:36:31 PM PDT 24
Peak memory 201584 kb
Host smart-cddaa413-8dd5-4762-9b3c-4680bd47bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133468697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.3133468697
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1892315486
Short name T368
Test name
Test status
Simulation time 203459502709 ps
CPU time 148.54 seconds
Started Jun 24 06:35:19 PM PDT 24
Finished Jun 24 06:37:50 PM PDT 24
Peak memory 201648 kb
Host smart-db45c06b-e23d-45dc-9f06-4ef850dbc171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892315486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.1892315486
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2203499842
Short name T271
Test name
Test status
Simulation time 25331284375 ps
CPU time 63.32 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:36:23 PM PDT 24
Peak memory 201576 kb
Host smart-7ad6d1c5-68c9-4458-9bd4-27675706f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203499842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.2203499842
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.924277589
Short name T761
Test name
Test status
Simulation time 46946720351 ps
CPU time 28.48 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:47 PM PDT 24
Peak memory 201620 kb
Host smart-215efdf5-6d33-4db3-81c6-f829406c7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924277589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_wi
th_pre_cond.924277589
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.931991629
Short name T74
Test name
Test status
Simulation time 114715090368 ps
CPU time 293.73 seconds
Started Jun 24 06:35:17 PM PDT 24
Finished Jun 24 06:40:14 PM PDT 24
Peak memory 201496 kb
Host smart-e65eaf66-3f72-4227-be13-3f8bfbf3bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931991629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_wi
th_pre_cond.931991629
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.148881276
Short name T212
Test name
Test status
Simulation time 24849203022 ps
CPU time 17.69 seconds
Started Jun 24 06:35:16 PM PDT 24
Finished Jun 24 06:35:37 PM PDT 24
Peak memory 201596 kb
Host smart-f2f185b7-5b33-46b3-937b-2669137735d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148881276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wi
th_pre_cond.148881276
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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