SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_detect_action_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 460 | 1 | T4 | 1 | T5 | 9 | T9 | 10 | ||||
auto[1] | 156 | 1 | T8 | 2 | T39 | 5 | T114 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 244 | 1 | T5 | 9 | T8 | 2 | T50 | 2 | ||||
auto[1] | 372 | 1 | T4 | 1 | T9 | 10 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 314 | 1 | T50 | 3 | T10 | 1 | T59 | 8 | ||||
auto[1] | 302 | 1 | T4 | 1 | T5 | 9 | T8 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 284 | 1 | T4 | 1 | T5 | 9 | T50 | 4 | ||||
auto[1] | 332 | 1 | T8 | 2 | T9 | 10 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 450 | 1 | T5 | 9 | T9 | 10 | T50 | 4 | ||||
auto[1] | 166 | 1 | T4 | 1 | T8 | 2 | T13 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 472 | 1 | T4 | 1 | T5 | 9 | T8 | 2 | ||||
auto[1] | 144 | 1 | T50 | 1 | T79 | 6 | T37 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 433 | 1 | T50 | 3 | T10 | 2 | T59 | 8 | ||||
auto[1] | 183 | 1 | T4 | 1 | T5 | 9 | T8 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 577 | 1 | T5 | 9 | T8 | 2 | T9 | 10 | ||||
auto[1] | 39 | 1 | T4 | 1 | T50 | 1 | T13 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 564 | 1 | T4 | 1 | T5 | 9 | T8 | 2 | ||||
auto[1] | 52 | 1 | T50 | 1 | T256 | 1 | T352 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 578 | 1 | T4 | 1 | T5 | 9 | T8 | 2 | ||||
auto[1] | 38 | 1 | T13 | 3 | T114 | 5 | T255 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 573 | 1 | T4 | 1 | T5 | 9 | T8 | 2 | ||||
auto[1] | 43 | 1 | T39 | 5 | T255 | 5 | T257 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 571 | 1 | T4 | 1 | T5 | 9 | T8 | 2 | ||||
auto[1] | 45 | 1 | T254 | 2 | T369 | 5 | T366 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 451 | 1 | T5 | 9 | T8 | 2 | T9 | 10 | ||||
auto[1] | 165 | 1 | T4 | 1 | T50 | 1 | T13 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 306 | 1 | T8 | 2 | T13 | 3 | T36 | 2 | ||||
auto[1] | 310 | 1 | T4 | 1 | T5 | 9 | T9 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 448 | 1 | T4 | 1 | T9 | 2 | T50 | 4 | ||||
auto[1] | 127 | 1 | T5 | 7 | T263 | 1 | T38 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 286 | 1 | T5 | 7 | T50 | 2 | T10 | 1 | ||||
auto[1] | 289 | 1 | T4 | 1 | T9 | 2 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 304 | 1 | T5 | 7 | T50 | 3 | T10 | 1 | ||||
auto[1] | 271 | 1 | T4 | 1 | T9 | 2 | T50 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 310 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 265 | 1 | T10 | 1 | T13 | 6 | T39 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 434 | 1 | T4 | 1 | T50 | 2 | T10 | 2 | ||||
auto[1] | 141 | 1 | T5 | 7 | T9 | 2 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 443 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 132 | 1 | T59 | 5 | T36 | 4 | T92 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 430 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 145 | 1 | T50 | 2 | T92 | 1 | T263 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 548 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 27 | 1 | T36 | 4 | T369 | 3 | T376 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 517 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 58 | 1 | T82 | 6 | T369 | 3 | T81 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 543 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 32 | 1 | T50 | 2 | T256 | 7 | T345 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 533 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 42 | 1 | T59 | 5 | T36 | 4 | T255 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 513 | 1 | T4 | 1 | T5 | 7 | T9 | 2 | ||||
auto[1] | 62 | 1 | T50 | 2 | T59 | 5 | T247 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 419 | 1 | T4 | 1 | T5 | 7 | T50 | 4 | ||||
auto[1] | 156 | 1 | T9 | 2 | T263 | 1 | T38 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 308 | 1 | T5 | 7 | T9 | 2 | T13 | 3 | ||||
auto[1] | 267 | 1 | T4 | 1 | T50 | 4 | T10 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 454 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 113 | 1 | T10 | 2 | T82 | 8 | T259 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 297 | 1 | T9 | 6 | T50 | 2 | T10 | 1 | ||||
auto[1] | 270 | 1 | T4 | 1 | T50 | 2 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 268 | 1 | T9 | 6 | T50 | 3 | T10 | 1 | ||||
auto[1] | 299 | 1 | T4 | 1 | T50 | 1 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 300 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 267 | 1 | T10 | 1 | T13 | 6 | T39 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 389 | 1 | T4 | 1 | T50 | 3 | T59 | 8 | ||||
auto[1] | 178 | 1 | T9 | 6 | T50 | 1 | T10 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 164 | 1 | T13 | 5 | T39 | 4 | T36 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 420 | 1 | T4 | 1 | T50 | 4 | T59 | 8 | ||||
auto[1] | 147 | 1 | T9 | 6 | T10 | 2 | T13 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 527 | 1 | T4 | 1 | T9 | 6 | T50 | 3 | ||||
auto[1] | 40 | 1 | T50 | 1 | T13 | 5 | T36 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 511 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 56 | 1 | T13 | 5 | T39 | 4 | T97 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 517 | 1 | T4 | 1 | T9 | 6 | T50 | 3 | ||||
auto[1] | 50 | 1 | T50 | 1 | T10 | 2 | T256 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 516 | 1 | T4 | 1 | T9 | 6 | T50 | 3 | ||||
auto[1] | 51 | 1 | T50 | 1 | T39 | 4 | T36 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 493 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 74 | 1 | T10 | 2 | T97 | 2 | T114 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 422 | 1 | T4 | 1 | T9 | 6 | T50 | 4 | ||||
auto[1] | 145 | 1 | T13 | 5 | T39 | 4 | T258 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 277 | 1 | T9 | 6 | T13 | 3 | T36 | 2 | ||||
auto[1] | 290 | 1 | T4 | 1 | T50 | 4 | T10 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 432 | 1 | T4 | 1 | T50 | 4 | T59 | 8 | ||||
auto[1] | 154 | 1 | T5 | 2 | T8 | 1 | T9 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 296 | 1 | T8 | 1 | T50 | 2 | T10 | 1 | ||||
auto[1] | 290 | 1 | T4 | 1 | T5 | 2 | T9 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 283 | 1 | T5 | 2 | T8 | 1 | T50 | 3 | ||||
auto[1] | 303 | 1 | T4 | 1 | T9 | 4 | T50 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 280 | 1 | T4 | 1 | T5 | 2 | T50 | 4 | ||||
auto[1] | 306 | 1 | T8 | 1 | T9 | 4 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 429 | 1 | T4 | 1 | T8 | 1 | T9 | 4 | ||||
auto[1] | 157 | 1 | T5 | 2 | T59 | 3 | T97 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 464 | 1 | T5 | 2 | T50 | 4 | T10 | 2 | ||||
auto[1] | 122 | 1 | T4 | 1 | T8 | 1 | T9 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 422 | 1 | T50 | 4 | T59 | 5 | T12 | 1 | ||||
auto[1] | 164 | 1 | T4 | 1 | T5 | 2 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 526 | 1 | T5 | 2 | T8 | 1 | T9 | 4 | ||||
auto[1] | 60 | 1 | T4 | 1 | T59 | 3 | T97 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 543 | 1 | T4 | 1 | T5 | 2 | T8 | 1 | ||||
auto[1] | 43 | 1 | T13 | 8 | T114 | 2 | T254 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 556 | 1 | T4 | 1 | T5 | 2 | T8 | 1 | ||||
auto[1] | 30 | 1 | T10 | 2 | T114 | 2 | T352 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 554 | 1 | T4 | 1 | T5 | 2 | T8 | 1 | ||||
auto[1] | 32 | 1 | T255 | 7 | T367 | 1 | T354 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 508 | 1 | T4 | 1 | T5 | 2 | T8 | 1 | ||||
auto[1] | 78 | 1 | T10 | 2 | T59 | 3 | T255 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 458 | 1 | T9 | 4 | T50 | 4 | T10 | 2 | ||||
auto[1] | 128 | 1 | T4 | 1 | T5 | 2 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 281 | 1 | T5 | 2 | T9 | 4 | T13 | 3 | ||||
auto[1] | 305 | 1 | T4 | 1 | T8 | 1 | T50 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |